coreboot July 2010

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Trac reminder: list of new ticket(s)
by coreboot tracker 26 Jul '10

26 Jul '10

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Coreboot Makefile
by ali hagigat 26 Jul '10

26 Jul '10

I wonder if any body can say what is the major effect of INNER_SCANBUILD symbol in making the project?

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Asus M8A-VM
by kai_sch＠gmx.net 26 Jul '10

26 Jul '10

Hello everybody, I attended Peters talks on 25c3 and 26c3 (thanks! they were great) and finally found some time to play around with coreboot. Luckily I have a spare Asus M8A-VM (AMD690G). The board is listed as supported, but it is not in trunk/src/mainboard/asus. So what is the best way forward? I started to collect the files for a /m8a-vm directory from the kontron kt690 and adjusted them partially with snippets from a Gigabyte board and the Asus m8v-vm. Is that the right way to start or is there still a fileset for my board in the repo and I am just to thick to find it? If there is nothing available I have two questions: - How do I get the devicetree.cb file right? It looks like the lspci output with some extras. (e.g. the Kontron file contains the SuperIO, which is not listed in my lspci) - I try to get romstage.c working by copy&pasting and guessing. Is there a more systematic approach that I am missing? Ciao Kai -- GRATIS für alle GMX-Mitglieder: Die maxdome Movie-FLAT! Jetzt freischalten unter http://portal.gmx.net/de/go/maxdome01

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CentraLUG meeting, 2 August
by Joseph Smith 25 Jul '10

25 Jul '10

Brief summary about the presentation: 1. I plan on speaking a litle about myself, and how I got involved in coreboot (elaborate on above). 2. Give a brief history on coreboot and how it started. 3. Go over some of the features of coreboot. 4. Go over some of the great tools that have sprouted off of the coreboot tree. 5. Talk about how the code process flows and how you(audiance) can start to develop coreboot. 6. Open for Question and Answer time. -------------------------------------- Do you guys think there is anything else I should touch on? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

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#154: Flashing BIOSes from Fujitsu/Siemens is not supported
by coreboot 25 Jul '10

25 Jul '10

#154: Flashing BIOSes from Fujitsu/Siemens is not supported ---------------------------------------+------------------------------------ Reporter: johannesobermayr@… | Owner: carldani Type: enhancement | Status: new Priority: major | Milestone: Component: flashrom | Version: Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------------+------------------------------------ As summary says I cannot flash BIOSes provided by Fujitsu/Siemens. You can see BIOS architecture from Fujitsu/Siemens if you download for example this BIOS package (for D1326): http://dl- extern3.treiberupdate.de/download2/123525.EXE I also could not find a suitable converter... -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/154> coreboot <http://www.coreboot.org/>

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[PATCH] support for nuvoton WPCE775x/NPCE781x devices (update copyright)
by Amit.Maoz＠nuvoton.com 25 Jul '10

25 Jul '10

This is the same patch as before (2010/07/14) just with an updated copyright notice. Amit Maoz Advanced PC Division Nuvoton Israel, P.O.Box 3007, Hertzlia B, 46130 Israel Phone : +972-9-9702266 Fax : +972-9-9702001 Email : Amit.Maoz(a)nuvoton.com<mailto:Amit.Maoz@nuvoton.com> Index: nuvoton.c =================================================================== --- nuvoton.c (revision 0) +++ nuvoton.c (revision 0) @@ -0,0 +1,106 @@ +/* + * This file is part of the superiotool project. + * + * Copyright (C) 2010 Google Inc. + * Written by David Hendricks <dhendrix(a)google.com> for Nuvoton Technology Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "superiotool.h" + +#define DEVICE_ID_REG 0x20 /* Super I/O ID (SID) / family */ +#define DEVICE_REV_REG 0x27 /* Super I/O revision ID (SRID) */ + +static const struct superio_registers reg_table[] = { + {0xfc, "WPCE775x / NPCE781x", { + {NOLDN, NULL, + {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28, + 0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, + {0xFC,0x11,RSVD,RSVD,RSVD,0x00,0x00,MISC,0x00, + 0x04,RSVD,RSVD,RSVD,0x00,RSVD,RSVD,EOT}}, + {0x03, "CIR Port (CIRP)", /* where supported */ + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, + {0x00,0x03,0xf8,0x04,0x03,0x04,0x04,0x02,EOT}}, + {0x04, "Mobile System Wake-Up Control Config (MSWC)", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,EOT}, + {0x00,0x00,0x00,0x00,0x03,0x04,0x04,EOT}}, + {0x05, "Mouse config (KBC)", + {0x30,0x70,0x71,0x74,0x75,EOT}, + {0x00,0x0c,0x03,0x04,0x04,EOT}}, + {0x06, "Keyboard config (KBC)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0x74,0x75,EOT}, + {0x00,0x00,0x60,0x00,0x64,0x01,0x03,0x04,0x04,EOT}}, + {0x0f, "Shared memory (SHM)", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,0xf1,0xf2, + 0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xfb,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x04,0x04,MISC,0x07,RSVD, + RSVD,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x11, "Power management I/F Channel 1 (PM1)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0x74,0x75,EOT}, + {0x00,0x00,0x62,0x00,0x66,0x01,0x03,0x04,0x04,EOT}}, + {0x12, "Power management I/F Channel 2 (PM2)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0x74,0x75,EOT}, + {0x00,0x00,0x68,0x00,0x6c,0x01,0x03,0x04,0x04,EOT}}, + {0x15, "Enhanced Wake On CIR (EWOC)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0x74,0x75,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x04,0x04,EOT}}, + {0x17, "Power Management I/F Channel 3 (PM3)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0x74,0x75,EOT}, + {0x00,0x00,0x6a,0x00,0x6e,0x01,0x03,0x04,0x04,EOT}}, + {0x1a, "Serial Port with Fast Infrared Port (FIR)", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, + {0x00,0x02,0xf8,0x03,0x03,0x04,0x04,0x02,EOT}}, + {EOT}}}, + {EOT} +}; + +void probe_idregs_nuvoton(uint16_t port) +{ + uint8_t sid, srid; + uint8_t chip_id = 0, chip_rev = 0; + + probing_for("Nuvoton", "(sid=0xfc) ", port); + + sid = regval(port, DEVICE_ID_REG); + srid = regval(port, DEVICE_REV_REG); + + if (sid == 0xfc) { /* WPCE775xL family */ + /* + * bits 7-5: Chip ID + * bits 4-0: Chip revision + */ + chip_id = srid >> 5; + chip_rev = srid & 0x1f; + } + + if (superio_unknown(reg_table, sid)) { + if (verbose) + printf(NOTFOUND "sid=0x%02x, id=0x%02x, rev=0x%02x\n", + sid, chip_id, chip_rev); + return; + } + + printf("Found Nuvoton %s (id=0x%02x, rev=0x%02x) at 0x%x\n", + get_superio_name(reg_table, sid), chip_id, chip_rev, port); + chip_found = 1; + + dump_superio("Nuvoton", reg_table, port, sid, LDN_SEL); +} + +void print_nuvoton_chips(void) +{ + print_vendor_chips("Nuvoton", reg_table); +} Index: superiotool.h =================================================================== --- superiotool.h (revision 4892) +++ superiotool.h (working copy) @@ -133,6 +133,10 @@ void probe_idregs_nsc(uint16_t port); void print_nsc_chips(void); +/* nuvoton.c */ +void probe_idregs_nuvoton(uint16_t port); +void print_nuvoton_chips(void); + /* smsc.c */ void probe_idregs_smsc(uint16_t port); void print_smsc_chips(void); @@ -151,6 +155,9 @@ /* Only use 0x370 for ITE, but 0x3f0 or 0x3bd would also be valid. */ {probe_idregs_ite, {0x2e, 0x4e, 0x370, EOT}}, {probe_idregs_nsc, {0x2e, 0x4e, 0x15c, EOT}}, + /* I/O pairs on Nuvoton EC chips can be configured by firmware in + * addition to the following hardware strapping options. */ + {probe_idregs_nuvoton, {0x164e, 0x2e, EOT}}, {probe_idregs_smsc, {0x2e, 0x4e, 0x162e, 0x164e, 0x3f0, 0x370, EOT}}, {probe_idregs_winbond, {0x2e, 0x4e, 0x3f0, 0x370, 0x250, EOT}}, }; @@ -163,6 +170,7 @@ {print_fintek_chips}, {print_ite_chips}, {print_nsc_chips}, + {print_nuvoton_chips}, {print_smsc_chips}, {print_winbond_chips}, }; Index: Makefile =================================================================== --- Makefile (revision 4892) +++ Makefile (working copy) @@ -32,7 +32,7 @@ CFLAGS = -O2 -Wall -Werror -Wstrict-prototypes -Wundef -Wstrict-aliasing \ -Werror-implicit-function-declaration -ansi -pedantic $(SVNDEF) -OBJS = superiotool.o ali.o fintek.o ite.o nsc.o smsc.o winbond.o +OBJS = superiotool.o ali.o fintek.o ite.o nsc.o nuvoton.o smsc.o winbond.o OS_ARCH = $(shell uname) ifeq ($(OS_ARCH), Darwin) =========================================================================================== The privileged confidential information contained in this email is intended for use only by the addressees as indicated by the original sender of this email. If you are not the addressee indicated in this email or are not responsible for delivery of the email to such a person, please kindly reply to the sender indicating this fact and delete all copies of it from your computer and network server immediately. Your cooperation is highly appreciated. It is advised that any unauthorized use of confidential information of Nuvoton is strictly prohibited; and any information in this email irrelevant to the official business of Nuvoton shall be deemed as neither given nor endorsed by Nuvoton. =========================================================================================== The privileged confidential information contained in this email is intended for use only by the addressees as indicated by the original sender of this email. If you are not the addressee indicated in this email or are not responsible for delivery of the email to such a person, please kindly reply to the sender indicating this fact and delete all copies of it from your computer and network server immediately. Your cooperation is highly appreciated. It is advised that any unauthorized use of confidential information of Nuvoton is strictly prohibited; and any information in this email irrelevant to the official business of Nuvoton shall be deemed as neither given nor endorsed by Nuvoton.

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ASUS K8V-MX
by phenon＠gmx.com 25 Jul '10

25 Jul '10

Hello everyone... I have an ASUS K8V-MX that I'd like to test coreboot on. It has VIA's K8M800 / VT8237R as the chipset duo, and an Athlon 64 3000+ 2GHz 754 CPU (ADA3000AIK4BX). The board link: http://www.asus.com/product.aspx?P_ID=dJ2XP7zr8tzeYbLp Is it doable? I'm a first timer with coreboot... Cheers :)

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Re: [coreboot] compiling coreboot
by ali hagigat 25 Jul '10

25 Jul '10

The reason some of you do not like to answer is not lack of time. It is because you do not want other people know about the details of the project, to disappoint people or make their progress slow. I do not ask trivial questions and far from the real knowledge necessary for the project. I ask the questions which hurts you guys because it targets your core knowledge you do not want to talk about. The same behaviour is seen in Linux Kernel mailing list... Knowledge expands by discussing the darkest areas of the matter not to keep it secrete in my opinion. Hey, Rudolf, you wrote 6 lines attacking me instead of write one line to answer my questions. What is the reason for it you think? Rudolf, answering my questions take you not more than a few minutes of your time and it is not a waste of time. Answering technical questions are not a waste of time, never, as it is a kind of practice and helps people keep their knowledge updated or refreshed. I did not ask you about economics, politics and the subjects unrelated to computer science, how can i waste your time? It is something you can benefit from if you think about it unless you have other reasons (that I am aware of!!) I asked some questions to understand the overall framework of the work without going into the details. I knew about the wiki site of Coreboot before, how could i register at this mailing list while I found it by Coreboot site!!? Go read wiki or the source code are the solutions I knew myself, i have the source and the Internet connection... On Tue, Jul 20, 2010 at 7:17 PM, anders(a)jenbo.dk <anders(a)jenbo.dk> wrote: > All your questions are answered on the wiki, in the make file or in the > docs. Go read them. > > Mvh Anders > > ----- Reply message ----- > Fra: "Rudolf Marek" <r.marek(a)assembler.cz> > Dato: tir., jul. 20, 2010 15:52 > Emne: [coreboot] compiling coreboot > Til: "ali hagigat" <hagigatali(a)gmail.com> > Cc: <coreboot(a)coreboot.org> > > > You did not read my last email didn't you? Do you think we are an expert > system > to ask? Do you think we have time to waste with you? Of course not, if are > not > able to get this, go away and find some other people to bother. > > No, thanks, > Rudolf > > Dne 20.7.2010 13:14, ali hagigat napsal(a): > > If i execute only this command at the root folder of Coreboot source tree > : > > make > > > > Will the project be compiled with GCC of the system or GCC of the system > > will be patched and changed or it will be compiled exactly with regular > > GCC of the linux operating system? > > > > Besides will be the object files in elf format and when they are linked? > > Is there any possibility for other formats? > > > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > > > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot >

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Re: [coreboot] LinuxBios P6IWP-Fe
by Anders Jenbo 24 Jul '10

24 Jul '10

Here is a prebuild rom for 512KB rom chips (it was what was in my board from the beginning). Make sure you have anothere chip with the original bios on it incase some thing goes wrong or i made a mistake when i build the image. -Anders From: Alan Grossi Sent: Friday, July 23, 2010 3:02 PM To: anders(a)jenbo.dk Subject: Re: LinuxBios P6IWP-Fe Good Day Friend. Yes I will try and send the results. Too bad the Coreboot is no longer tied to Linux, but I want to study in depth and yes he still have bios. Was looking in my bios I found some scraps that I believe to work in ECS_P6IWP-Fe, bios 2MB. I really appreciate it if you send me a picture compiled. I'm still studying how to build the mine, but I do not see that long, I just risking. Thanks for everything. Sorry for any inconvenience. I have a vast collection of motherboards at home, or els with the test and then you step Coreboot results. So we can add even more to the list of cards supported. I'm not very good with English, so I'm using Google translator. Sorry the inconsistencies in the text. _______________________________________________________________________________________________________________________________________ > Subject: Re: LinuxBios P6IWP-Fe > From: anders(a)jenbo.dk > To: alan_roberto_grossi(a)hotmail.com > Date: Fri, 23 Jul 2010 00:45:33 +0200 > > Hi i ported this board 45 dayes ago :) > Here is the current status of the board > http://www.coreboot.org/ECS_P6IWP-Fe > If you test any thing make sure to send your result here so that we can > update the table. > > LinuxBIOS is now know as Coreboot, this is because it is nolonger tied > in to Linux (you still can do that if you want to). > > The rom flash chip on the board is fairly small, so putting a full linux > on it might not be posible. But you can still run coreboot, with either > FILO, GRUB or SeaBIOS as a payload and have one of them start up your > installed linux. > > I can send you a compiled image tomorrow, if you like. > > To compile one your self: > > 1: make sure that you have all the tools mentioned here: > http://www.coreboot.org/Development_Guidelines#Required_Toolchain > (you can stop when you get to "Coding Guidelines") > > 2: follow this guide. > http://www.coreboot.org/Build_HOWTO > pick SeaBIOS as your payload, it's a safe bet for starters. > > Before you flash your motherboard you should consider getting a second > flashrom-chip that you can safely flash, this way if things doesn't work > you can get your motherboard back to life by placing back the original > flashrom-chip. > The chip you will need is an Intel 82802AB, it can be found on some > other mother boards, i don't know if it is still possible to order it. > It will look some thing like this: > http://flashrom.org/File:Plcc32_in_socket.jpg > > -Anders > > tor, 22 07 2010 kl. 16:27 +0300, skrev Alan Grossi: > > Good Day Friend. > > > > My name is ALAN GROSSI, I'm a fan of Linux. > > > > I have the Motherboard P6IWP-Fe and now I'm getting to know the Linux > > BIOS project. > > > > I would like your help to configure and use this motherboard. > > > > Perhaps a bios ready. > > > > Sorry for the inconvenience. > > > > Thanks already. > > > > > > > > > > > > ______________________________________________________________________ > > O INTERNET EXPLORER 8 AJUDA VOCÊ A FICAR LONGE DOS VÍRUS. DESCUBRA > > COMO. > > -------------------------------------------------------------------------------- LEVE SEU MESSENGER PARA ONDE VOCÊ ESTIVER PELO SEU CELULAR. CLIQUE E VEJA COMO FAZER.

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[patch](trivial) Fix qemu target compilation with netconsole enabled
by Cristi Magherusan 24 Jul '10

24 Jul '10

Hi, See attached trivial patch. This fix might apply to other boards that only have -mcpu=i386 set in ROMCCFLAGS. Still, some won't work because of too large binaries that won't fit the ROM size when enabling the netconsole. Signed-off-by: Cristi Magherusan <cristi.magherusan(a)net.utcluj.ro> Regards, Cristi -- Cristi Măgherușan, alumnus System/Network Engineer Technical University of Cluj-Napoca, Romania http://cc.utcluj.ro +40264 401247

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coreboot July 2010