coreboot July 2010

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Re: [coreboot] [PATCH] Convert Geode GX2 boards to CAR
by Nils 27 Jul '10

27 Jul '10

Hi Joseph and Peter, Thanks for commiting my patch. Now i can dig up the next patch. Thanks,Nils.

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Gigabyte SuperIO problems
by Qing Pei Wang 27 Jul '10

27 Jul '10

hi all, since it's old topic, but i would like to arise this again. I am trying to port coreboot to two gigabyte mainboard. both of them have the same superIO ITE8718, one of the board is GA-MA78GM-UD2H . it is an 780+700+DDR2 mainboard, which is much similar with AMD Mahogany. The confusing things now is after the ITE8718 init, it continues reboot. This caused me thinking about the difference of ITE8718 between MA78GM and mahogany. Gigabyte may did some special hardware(or register)configuration to ITE8718. Is there any one who tried to port coreboot to Gigabyte dual bios mainboards? Vadim: I found your mail in flashrom mail list, it seems that you had the experience about the gigabyte dual bios things. Have you have any suggestion about my problems? -- Wang Qing Pei Phone: 86+13426369984

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build service results for r5670
by repository service 27 Jul '10

27 Jul '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stuge" checked in revision 5670 to the coreboot repository. This caused the following changes: Change Log: Add src/cpu/amd/model_gx2/cache_as_ram.inc missing from r5669 Part of converting GX2 to use CAR. Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl> Acked-by: Joseph Smith <joe(a)settoplinux.org> Acked-by: Peter Stuge <peter(a)stuge.se> Build Log: Compilation of amd:rumba has been fixed Compilation of lippert:frontrunner has been fixed Compilation of olpc:btest has been fixed Compilation of olpc:rev_a has been fixed Compilation of wyse:s50 has been fixed If something broke during this checkin please be a pain in stuge's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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build service results for r5669
by repository service 27 Jul '10

27 Jul '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "linux_junkie" checked in revision 5669 to the coreboot repository. This caused the following changes: Change Log: This patch converts the Geode GX2 boards to CAR. Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl> Acked-by: Joseph Smith <joe(a)settoplinux.org> Build Log: Compilation of amd:rumba has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5669&device=rumba&vendor=a… Compilation of lippert:frontrunner has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5669&device=frontrunner&ve… Compilation of olpc:btest has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5669&device=btest&vendor=o… Compilation of olpc:rev_a has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5669&device=rev_a&vendor=o… Compilation of wyse:s50 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5669&device=s50&vendor=wys… If something broke during this checkin please be a pain in linux_junkie's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r5670 - trunk/src/cpu/amd/model_gx2
by repository service 27 Jul '10

27 Jul '10

Author: stuge Date: Tue Jul 27 02:30:42 2010 New Revision: 5670 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5670 Log: Add src/cpu/amd/model_gx2/cache_as_ram.inc missing from r5669 Part of converting GX2 to use CAR. Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl> Acked-by: Joseph Smith <joe(a)settoplinux.org> Acked-by: Peter Stuge <peter(a)stuge.se> Added: trunk/src/cpu/amd/model_gx2/cache_as_ram.inc Added: trunk/src/cpu/amd/model_gx2/cache_as_ram.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/cpu/amd/model_gx2/cache_as_ram.inc Tue Jul 27 02:30:42 2010 (r5670) @@ -0,0 +1,207 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2010 Nils Jacobs + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define GX2_STACK_BASE CONFIG_DCACHE_RAM_BASE /* this is where the DCache will be mapped and be used as stack, It would be cool if it was the same base as coreboot normal stack */ +#define GX2_STACK_END GX2_STACK_BASE+(CONFIG_DCACHE_RAM_SIZE-1) + +#define GX2_NUM_CACHELINES 0x080 /* there are 128lines per way */ +#define GX2_CACHELINE_SIZE 0x020 /* there are 32bytes per line */ +#define GX2_CACHEWAY_SIZE (GX2_NUM_CACHELINES * GX2_CACHELINE_SIZE) +#define CR0_CD 0x40000000 /* bit 30 = Cache Disable */ +#define CR0_NW 0x20000000 /* bit 29 = Not Write Through */ +#include <cpu/amd/gx2def.h> +/*************************************************************************** +/** +/** DCacheSetup +/** +/** Setup data cache for use as RAM for a stack. +/** +/** Max. size data cache =0x4000 (16KB) +/** +/***************************************************************************/ +DCacheSetup: + /* Save the BIST result */ + movl %eax, %ebx + + invd + /* set cache properties */ + movl $CPU_RCONF_DEFAULT, %ecx + rdmsr + movl $0x010010000, %eax /*1MB system memory in write back 1|00100|00 */ + wrmsr + + /* in GX2 DCDIS is set after POR which disables the cache..., clear this bit */ + movl $CPU_DM_CONFIG0, %ecx + rdmsr + andl $(~(DM_CONFIG0_LOWER_DCDIS_SET)), %eax /* TODO: make consistent with i$ init, either whole reg = 0, or just this bit... */ + wrmsr + + /* Get cleaned up. */ + xorl %edi, %edi + xorl %esi, %esi + xorl %ebp, %ebp + + /* DCache Ways0 through Ways3 will be tagged for GX2_STACK_BASE + CONFIG_DCACHE_RAM_SIZE for holding stack */ + /* remember, there is NO stack yet... */ + + /* Tell cache we want to fill WAY 0 starting at the top */ + xorl %edx, %edx + xorl %eax, %eax + movl $CPU_DC_INDEX, %ecx + wrmsr + + /* startaddress for tag of Way0: ebp will hold the incrementing address. dont destroy! */ + movl $GX2_STACK_BASE, %ebp /* init to start address */ + orl $1, %ebp /* set valid bit and tag for this Way (B[31:12] : Cache tag value for line/way curr. selected by CPU_DC_INDEX */ + + /* start tag Ways 0 with 128 lines with 32bytes each: edi will hold the line counter. dont destroy! */ + movl $GX2_NUM_CACHELINES, %edi +DCacheSetupFillWay: + + /* fill with dummy data: zero it so we can tell it from PCI memory space (returns FFs). */ + /* We will now store a line (32 bytes = 4 x 8bytes = 4 quadWords) */ + movw $0x04, %si + xorl %edx, %edx + xorl %eax, %eax + movl $CPU_DC_DATA, %ecx +DCacheSetup_quadWordLoop: + wrmsr + decw %si + jnz DCacheSetup_quadWordLoop + + /* Set the tag for this line,need to do this for every new cache line to validate it! */ + /* accessing CPU_DC_TAG_I makes the LINE field in CPU_DC_INDEX increment and thus cont. in the next cache line... */ + xorl %edx, %edx + movl %ebp, %eax + movl $CPU_DC_TAG, %ecx + wrmsr + + /* switch to next line */ + /* lines are in Bits8:2 */ + /* when index is crossing 0x7F -> 0x80 writing a RSVD bit as 0x80 is not a valid CL anymore! */ + movl $CPU_DC_INDEX, %ecx + rdmsr + addl $0x04, %eax /* inc DC_LINE. TODO: prob. would be more elegant to calc. this from counter var edi... */ + wrmsr + + decl %edi + jnz DCacheSetupFillWay + + /* 1 Way has been filled, forward start address for next Way, terminate if we have reached end of desired address range */ + addl $GX2_CACHEWAY_SIZE, %ebp + cmpl $GX2_STACK_END, %ebp + jge leave_DCacheSetup + movl $GX2_NUM_CACHELINES, %edi + + /* switch to next way */ + movl $CPU_DC_INDEX, %ecx + rdmsr + addl $0x01, %eax + andl $0xFFFFFE03, %eax /* lets be sure: reset line index Bits8:2 */ + wrmsr + + jmp DCacheSetupFillWay + +leave_DCacheSetup: + xorl %edi, %edi + xorl %esi, %esi + xorl %ebp, %ebp + + /* Disable the cache, but ... DO NOT INVALIDATE the tags. */ + /* Memory reads and writes will all hit in the cache. */ + /* Cache updates and memory write-backs will not occur ! */ + movl %cr0, %eax + orl $(CR0_CD + CR0_NW), %eax /* set the CD and NW bits */ + movl %eax, %cr0 + + /* Now point sp to the cached stack. */ + /* The stack will be fully functional at this location. No system memory is required at all ! */ + /* set up the stack pointer */ + movl $GX2_STACK_END, %eax + movl %eax, %esp + + /* test the stack*/ + movl $0x0F0F05A5A, %edx + pushl %edx + popl %ecx + cmpl %ecx, %edx + je DCacheSetupGood + + post_code(0xc5) +DCacheSetupBad: + hlt /* issues */ + jmp DCacheSetupBad +DCacheSetupGood: + /* Go do early init and memory setup */ + + /* Restore the BIST result */ + movl %ebx, %eax + movl %esp, %ebp + pushl %eax + + post_code(0x23) + + /* Call romstage.c main function */ + call main +done_cache_as_ram_main: + + /* We now run over the stack-in-cache, copying it back to itself to invalidate the cache */ + + push %edi + mov $(CONFIG_DCACHE_RAM_SIZE/4),%ecx + push %esi + mov $(CONFIG_DCACHE_RAM_BASE),%edi + mov %edi,%esi + cld + rep movsl %ds:(%esi),%es:(%edi) + pop %esi + pop %edi + + /* Clear the cache out to ram */ + wbinvd + /* re-enable the cache */ + movl %cr0, %eax + xorl $(CR0_CD + CR0_NW), %eax /* clear the CD and NW bits */ + movl %eax, %cr0 + + /* clear boot_complete flag */ + xorl %ebp, %ebp +__main: + post_code(0x11) /* post 11 */ + + /* TODO For suspend/resume the cache will have to live between + * CONFIG_RAMBASE and CONFIG_RAMTOP + */ + + cld /* clear direction flag */ + + /* copy coreboot from it's initial load location to + * the location it is compiled to run at. + * Normally this is copying from FLASH ROM to RAM. + */ + movl %ebp, %esi + pushl %esi + call copy_and_run + +.Lhlt: + post_code(0xee) /* post fail ee */ + hlt + jmp .Lhlt +

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Re: [coreboot] [PATCH] Convert Geode GX2 boards to CAR
by Nils 27 Jul '10

27 Jul '10

This patch converts the Geode GX2 boards to CAR. It reduces the boot time with ~35 seconds in "Stage: loading fallback/coreboot_ram". After the conversion GCC gave a lot of build warnings in the old ROMCC code (especially in the southbridge CS5535 code used by the Lippert Frontrunner board) which i had to fix. It is ABUILD tested and boot tested on my Wyse S50. Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl> Acked-by: Joseph Smith <joe(a)settoplinux.org> V2: Add newline at end of file src/cpu/amd/model_gx2/Makefile.inc.(thanks to Peter for spotting this) Remove unused code in src/southbridge/amd/cs5535/ . Thanks,nils.

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[commit] r5669 - in trunk/src: cpu/amd/model_gx2 include/cpu/amd mainboard/amd/rumba mainboard/lippert/frontrunner mainboard/olpc/btest mainboard/olpc/rev_a mainboard/wyse/s50 northbridge/amd/gx2 s...
by repository service 27 Jul '10

27 Jul '10

Author: linux_junkie Date: Tue Jul 27 01:46:25 2010 New Revision: 5669 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5669 Log: This patch converts the Geode GX2 boards to CAR. Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl> Acked-by: Joseph Smith <joe(a)settoplinux.org> Modified: trunk/src/cpu/amd/model_gx2/Kconfig trunk/src/cpu/amd/model_gx2/Makefile.inc trunk/src/cpu/amd/model_gx2/cpureginit.c trunk/src/cpu/amd/model_gx2/syspreinit.c trunk/src/include/cpu/amd/gx2def.h trunk/src/mainboard/amd/rumba/Kconfig trunk/src/mainboard/amd/rumba/romstage.c trunk/src/mainboard/lippert/frontrunner/Kconfig trunk/src/mainboard/lippert/frontrunner/romstage.c trunk/src/mainboard/olpc/btest/Kconfig trunk/src/mainboard/olpc/btest/romstage.c trunk/src/mainboard/olpc/rev_a/Kconfig trunk/src/mainboard/olpc/rev_a/romstage.c trunk/src/mainboard/wyse/s50/Kconfig trunk/src/mainboard/wyse/s50/romstage.c trunk/src/northbridge/amd/gx2/pll_reset.c trunk/src/northbridge/amd/gx2/raminit.c trunk/src/northbridge/amd/gx2/raminit.h trunk/src/southbridge/amd/cs5535/chipsetinit.c trunk/src/southbridge/amd/cs5535/cs5535.h trunk/src/southbridge/amd/cs5535/cs5535_early_setup.c trunk/src/southbridge/amd/cs5535/cs5535_early_smbus.c trunk/src/southbridge/amd/cs5535/cs5535_smbus.h Modified: trunk/src/cpu/amd/model_gx2/Kconfig ============================================================================== --- trunk/src/cpu/amd/model_gx2/Kconfig Mon Jul 26 23:45:11 2010 (r5668) +++ trunk/src/cpu/amd/model_gx2/Kconfig Tue Jul 27 01:46:25 2010 (r5669) @@ -22,12 +22,12 @@ config DCACHE_RAM_BASE hex - default 0xc0000 + default 0xc8000 depends on CPU_AMD_GX2 config DCACHE_RAM_SIZE hex - default 0x01000 + default 0x04000 depends on CPU_AMD_GX2 config GEODE_VSA Modified: trunk/src/cpu/amd/model_gx2/Makefile.inc ============================================================================== --- trunk/src/cpu/amd/model_gx2/Makefile.inc Mon Jul 26 23:45:11 2010 (r5668) +++ trunk/src/cpu/amd/model_gx2/Makefile.inc Tue Jul 27 01:46:25 2010 (r5669) @@ -2,5 +2,8 @@ subdirs-y += ../../x86/lapic subdirs-y += ../../x86/cache subdirs-y += ../../x86/smm + driver-y += model_gx2_init.o obj-y += cpubug.o + +cpu_incs += $(src)/cpu/amd/model_gx2/cache_as_ram.inc Modified: trunk/src/cpu/amd/model_gx2/cpureginit.c ============================================================================== --- trunk/src/cpu/amd/model_gx2/cpureginit.c Mon Jul 26 23:45:11 2010 (r5668) +++ trunk/src/cpu/amd/model_gx2/cpureginit.c Tue Jul 27 01:46:25 2010 (r5669) @@ -1,81 +1,9 @@ - -/* ***************************************************************************/ -/* **/ -/* * BIST */ -/* **/ -/* * GX2 BISTs need to be run before BTB or caches are enabled.*/ -/* * BIST result left in registers on failure to be checked with FS2.*/ -/* **/ -/* ***************************************************************************/ -static void -BIST(void){ - int msrnum; - msr_t msr; - - /* DM*/ - msrnum = CPU_DM_CONFIG0; - msr = rdmsr(msrnum); - msr.lo |= DM_CONFIG0_LOWER_DCDIS_SET; - wrmsr(msrnum, msr); - - msr.lo = 0x00000003F; - msr.hi = 0x000000000; - msrnum = CPU_DM_BIST; - wrmsr(msrnum, msr); - - outb(POST_CPU_DM_BIST_FAILURE, 0x80); /* 0x29*/ - msr = rdmsr(msrnum); /* read back for pass fail*/ - msr.lo &= 0x0F3FF0000; - if (msr.lo != 0xfeff0000) - goto BISTFail; - - msrnum = CPU_DM_CONFIG0; - msr = rdmsr(msrnum); - msr.lo &= ~ DM_CONFIG0_LOWER_DCDIS_SET; - wrmsr(msrnum, msr); - - /* FPU*/ - msr.lo = 0x000000131; - msr.hi = 0; - msrnum = CPU_FP_UROM_BIST; - wrmsr(msrnum, msr); - - outb(POST_CPU_FPU_BIST_FAILURE, 0x80); /* 0x89*/ - inb(0x80); /* IO delay*/ - msr = rdmsr(msrnum); /* read back for pass fail*/ - while ((msr.lo&0x884) != 0x884) - msr = rdmsr(msrnum); /* Endless loop if BIST is broken*/ - if ((msr.lo&0x642) != 0x642) - goto BISTFail; - - msr.lo = msr.hi = 0; /* clear FPU BIST bits*/ - msrnum = CPU_FP_UROM_BIST; - wrmsr(msrnum, msr); - - - /* BTB*/ - msr.lo = 0x000000303; - msr.hi = 0x000000000; - msrnum = CPU_PF_BTBRMA_BIST; - wrmsr(msrnum, msr); - - outb(POST_CPU_BTB_BIST_FAILURE , 0x80); /* 0x8A*/ - msr = rdmsr(msrnum); /* read back for pass fail*/ - if ((msr.lo & 0x3030) != 0x3030) - goto BISTFail; - - return; - -BISTFail: - print_err("BIST failed!\n"); - while(1); -} /* ***************************************************************************/ /* * cpuRegInit*/ /* ***************************************************************************/ -void -cpuRegInit (void){ +void cpuRegInit (void) +{ int msrnum; msr_t msr; /* Turn on BTM for early debug based on setup. */ @@ -197,16 +125,6 @@ msr.lo |= 0x08; wrmsr(msrnum, msr); - -/* */ -/* BIST*/ -/* */ - /*if (getnvram( TOKEN_BIST_ENABLE) & == TVALUE_DISABLE) {*/ - { -// BIST(); - } - - /* */ /* Enable BTB*/ /* */ @@ -260,45 +178,3 @@ } #endif } - - - - -/* ***************************************************************************/ -/* **/ -/* * MTestPinCheckBX*/ -/* **/ -/* * Set MTEST pins to expected values from OPTIONS.INC/NVRAM*/ -/* * This version is called when there isn't a stack available*/ -/* **/ -/* ***************************************************************************/ -static void -MTestPinCheckBX (void){ - int msrnum; - msr_t msr; - - /*if (getnvram( TOKEN_MTEST_ENABLE) ==TVALUE_DISABLE ) {*/ - /* return ; */ - /* } */ - - /* Turn on MTEST*/ - msrnum = MC_CFCLK_DBUG; - msr = rdmsr(msrnum); - msr.hi |= CFCLK_UPPER_MTST_B2B_DIS_SET | CFCLK_UPPER_MTEST_EN_SET; - wrmsr(msrnum, msr); - - msrnum = GLCP_SYS_RSTPLL /* Get SDR/DDR mode from GLCP*/; - msr = rdmsr(msrnum); - msr.lo >>= RSTPPL_LOWER_SDRMODE_SHIFT; - if (msr.lo & 1) { - msrnum = MC_CFCLK_DBUG; /* Turn on SDR MTEST stuff*/ - msr = rdmsr(msrnum); - msr.lo |= CFCLK_LOWER_SDCLK_SET; - msr.hi |= CFCLK_UPPER_MTST_DQS_EN_SET; - wrmsr(msrnum, msr); - } - - /* Lock the cache down here.*/ - __asm__("wbinvd\n"); - -} Modified: trunk/src/cpu/amd/model_gx2/syspreinit.c ============================================================================== --- trunk/src/cpu/amd/model_gx2/syspreinit.c Mon Jul 26 23:45:11 2010 (r5668) +++ trunk/src/cpu/amd/model_gx2/syspreinit.c Tue Jul 27 01:46:25 2010 (r5669) @@ -7,17 +7,17 @@ /* * Destroys: Al,*/ /* **/ /* ***************************************************************************/ -static void -StartTimer1(void) +static void StartTimer1(void) { outb(0x56, 0x43); outb(0x12, 0x41); } -void -SystemPreInit(void) +void SystemPreInit(void) { /* they want a jump ... */ - __asm__("jmp .+2\ninvd\njmp.+2\n"); +#ifndef CONFIG_USE_DCACHE_RAM + __asm__ __volatile__("jmp .+2\ninvd\njmp .+2\n"); +#endif StartTimer1(); } Modified: trunk/src/include/cpu/amd/gx2def.h ============================================================================== --- trunk/src/include/cpu/amd/gx2def.h Mon Jul 26 23:45:11 2010 (r5668) +++ trunk/src/include/cpu/amd/gx2def.h Tue Jul 27 01:46:25 2010 (r5669) @@ -435,14 +435,15 @@ #define VIP_GLD_MSR_CAP (MSR_VIP + 0x2000) #define VIP_GLD_MSR_CONFIG (MSR_VIP + 0x2001) #define VIP_GLD_MSR_PM (MSR_VIP + 0x2004) -#define VIP_BIST (MSR_VIP + 0x2005) +#define VIP_BIST (MSR_VIP + 0x2005) +#define VIP_GIO_MSR_SEL (MSR_VIP + 0x2010) /* */ /* AES GLIU1 port 6*/ /* */ #define AES_GLD_MSR_CAP (MSR_AES + 0x2000) #define AES_GLD_MSR_CONFIG (MSR_AES + 0x2001) #define AES_GLD_MSR_PM (MSR_AES + 0x2004) -#define AES_CONTROL (MSR_AES + 0x2006) +#define AES_CONTROL (MSR_AES + 0x2006) /* more fun stuff */ #define BM 1 /* Base Mask - map power of 2 size aligned region*/ #define BMO 2 /* BM with an offset*/ @@ -695,9 +696,10 @@ #if !defined(__ROMCC__) && !defined(ASSEMBLY) #if defined(__PRE_RAM__) -#else -void cpubug(void); +void cpuRegInit(void); +void SystemPreInit(void); #endif +void cpubug(void); #endif #endif /* CPU_AMD_GX2DEF_H */ Modified: trunk/src/mainboard/amd/rumba/Kconfig ============================================================================== --- trunk/src/mainboard/amd/rumba/Kconfig Mon Jul 26 23:45:11 2010 (r5668) +++ trunk/src/mainboard/amd/rumba/Kconfig Tue Jul 27 01:46:25 2010 (r5669) @@ -23,8 +23,9 @@ select CPU_AMD_GX2 select NORTHBRIDGE_AMD_GX2 select SOUTHBRIDGE_AMD_CS5536 - select ROMCC select UDELAY_TSC + select USE_DCACHE_RAM + select USE_PRINTK_IN_CAR select HAVE_PIRQ_TABLE select BOARD_ROMSIZE_KB_256 Modified: trunk/src/mainboard/amd/rumba/romstage.c ============================================================================== --- trunk/src/mainboard/amd/rumba/romstage.c Mon Jul 26 23:45:11 2010 (r5668) +++ trunk/src/mainboard/amd/rumba/romstage.c Tue Jul 27 01:46:25 2010 (r5669) @@ -2,7 +2,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> #include "lib/ramtest.c" @@ -99,22 +98,9 @@ #include "northbridge/amd/gx2/pll_reset.c" #include "cpu/amd/model_gx2/cpureginit.c" #include "cpu/amd/model_gx2/syspreinit.c" -static void msr_init(void) -{ - /* total physical memory */ - __builtin_wrmsr(0x1808, 0x10f3bf00, 0x22fffc02); - - /* traditional memory 0kB-512kB, 512kB-1MB */ - __builtin_wrmsr(0x10000020, 0xfff80, 0x20000000); - __builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000); +#include "cpu/amd/model_lx/msrinit.c" - __builtin_wrmsr(0x40000020, 0xfff80, 0x20000000); - __builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000); - - /* put code in northbridge[init].c here */ -} - -static void main(unsigned long bist) +void main(unsigned long bist) { static const struct mem_controller memctrl [] = { {.channel0 = {(0xa<<3)|0, (0xa<<3)|1}} @@ -122,13 +108,15 @@ SystemPreInit(); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); cs5536_early_setup(); + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + pll_reset(); cpuRegInit(); Modified: trunk/src/mainboard/lippert/frontrunner/Kconfig ============================================================================== --- trunk/src/mainboard/lippert/frontrunner/Kconfig Mon Jul 26 23:45:11 2010 (r5668) +++ trunk/src/mainboard/lippert/frontrunner/Kconfig Tue Jul 27 01:46:25 2010 (r5669) @@ -4,8 +4,9 @@ select CPU_AMD_GX2 select NORTHBRIDGE_AMD_GX2 select SOUTHBRIDGE_AMD_CS5535 - select ROMCC select UDELAY_TSC + select USE_DCACHE_RAM + select USE_PRINTK_IN_CAR select HAVE_PIRQ_TABLE select BOARD_ROMSIZE_KB_256 Modified: trunk/src/mainboard/lippert/frontrunner/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/frontrunner/romstage.c Mon Jul 26 23:45:11 2010 (r5668) +++ trunk/src/mainboard/lippert/frontrunner/romstage.c Tue Jul 27 01:46:25 2010 (r5669) @@ -2,7 +2,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> #include "lib/ramtest.c" @@ -10,6 +9,7 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/gx2def.h> +#include "southbridge/amd/cs5535/cs5535.h" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -46,31 +46,9 @@ #include "northbridge/amd/gx2/pll_reset.c" #include "cpu/amd/model_gx2/cpureginit.c" #include "cpu/amd/model_gx2/syspreinit.c" -static void msr_init(void) -{ - __builtin_wrmsr(0x1808, 0x10f3bf00, 0x22fffc02); - - __builtin_wrmsr(0x10000020, 0xfff80, 0x20000000); - __builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000); - __builtin_wrmsr(0x10000026, 0x400fffc0, 0x2cfbc040); - __builtin_wrmsr(0x10000027, 0xfff00000, 0xff); - __builtin_wrmsr(0x10000028, 0x7bf00100, 0x2000000f); - __builtin_wrmsr(0x1000002c, 0xff030003, 0x20000000); - - __builtin_wrmsr(0x10000080, 0x3, 0x0); - - __builtin_wrmsr(0x40000020, 0xfff80, 0x20000000); - __builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000); - __builtin_wrmsr(0x40000023, 0x400fffc0, 0x20000040); - __builtin_wrmsr(0x40000024, 0xff4ffffc, 0x200000ef); - __builtin_wrmsr(0x40000029, 0x7bf00100, 0x2000000f); - __builtin_wrmsr(0x4000002d, 0xff030003, 0x20000000); - - __builtin_wrmsr(0x50002001, 0x27, 0x0); - __builtin_wrmsr(0x4c002001, 0x1, 0x0); -} +#include "cpu/amd/model_lx/msrinit.c" -static void main(unsigned long bist) +void main(unsigned long bist) { static const struct mem_controller memctrl [] = { {.channel0 = {(0xa<<3)|0, (0xa<<3)|1}} @@ -85,6 +63,10 @@ cs5535_early_setup(); print_err("done cs5535 early\n"); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + pll_reset(); print_err("done pll_reset\n"); Modified: trunk/src/mainboard/olpc/btest/Kconfig ============================================================================== --- trunk/src/mainboard/olpc/btest/Kconfig Mon Jul 26 23:45:11 2010 (r5668) +++ trunk/src/mainboard/olpc/btest/Kconfig Tue Jul 27 01:46:25 2010 (r5669) @@ -4,8 +4,9 @@ select CPU_AMD_GX2 select NORTHBRIDGE_AMD_GX2 select SOUTHBRIDGE_AMD_CS5536 - select ROMCC select UDELAY_TSC + select USE_DCACHE_RAM + select USE_PRINTK_IN_CAR select HAVE_PIRQ_TABLE select BOARD_ROMSIZE_KB_256 Modified: trunk/src/mainboard/olpc/btest/romstage.c ============================================================================== --- trunk/src/mainboard/olpc/btest/romstage.c Mon Jul 26 23:45:11 2010 (r5668) +++ trunk/src/mainboard/olpc/btest/romstage.c Tue Jul 27 01:46:25 2010 (r5669) @@ -2,7 +2,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> #include "lib/ramtest.c" @@ -132,16 +131,7 @@ #include "northbridge/amd/gx2/pll_reset.c" #include "cpu/amd/model_gx2/cpureginit.c" #include "cpu/amd/model_gx2/syspreinit.c" -static void msr_init(void) -{ - __builtin_wrmsr(0x1808, 0x10f3bf00, 0x22fffc02); - - __builtin_wrmsr(0x10000020, 0xfff80, 0x20000000); - __builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000); - - __builtin_wrmsr(0x40000020, 0xfff80, 0x20000000); - __builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000); -} +#include "cpu/amd/model_lx/msrinit.c" static void gpio_init(void) { @@ -155,7 +145,7 @@ outl(m, GPIOL_EVENTS_ENABLE); } -static void main(unsigned long bist) +void main(unsigned long bist) { static const struct mem_controller memctrl [] = { {.channel0 = {(0xa<<3)|0, (0xa<<3)|1}} @@ -175,6 +165,9 @@ uart_init(); console_init(); + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + pll_reset(); cpuRegInit(); Modified: trunk/src/mainboard/olpc/rev_a/Kconfig ============================================================================== --- trunk/src/mainboard/olpc/rev_a/Kconfig Mon Jul 26 23:45:11 2010 (r5668) +++ trunk/src/mainboard/olpc/rev_a/Kconfig Tue Jul 27 01:46:25 2010 (r5669) @@ -4,8 +4,9 @@ select CPU_AMD_GX2 select NORTHBRIDGE_AMD_GX2 select SOUTHBRIDGE_AMD_CS5536 - select ROMCC select UDELAY_TSC + select USE_DCACHE_RAM + select USE_PRINTK_IN_CAR select HAVE_PIRQ_TABLE select BOARD_ROMSIZE_KB_256 Modified: trunk/src/mainboard/olpc/rev_a/romstage.c ============================================================================== --- trunk/src/mainboard/olpc/rev_a/romstage.c Mon Jul 26 23:45:11 2010 (r5668) +++ trunk/src/mainboard/olpc/rev_a/romstage.c Tue Jul 27 01:46:25 2010 (r5669) @@ -2,7 +2,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> #include "lib/ramtest.c" @@ -132,16 +131,7 @@ #include "northbridge/amd/gx2/pll_reset.c" #include "cpu/amd/model_gx2/cpureginit.c" #include "cpu/amd/model_gx2/syspreinit.c" -static void msr_init(void) -{ - __builtin_wrmsr(0x1808, 0x10f3bf00, 0x22fffc02); - - __builtin_wrmsr(0x10000020, 0xfff80, 0x20000000); - __builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000); - - __builtin_wrmsr(0x40000020, 0xfff80, 0x20000000); - __builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000); -} +#include "cpu/amd/model_lx/msrinit.c" static void gpio_init(void) { @@ -155,7 +145,7 @@ outl(m, GPIOL_EVENTS_ENABLE); } -static void main(unsigned long bist) +void main(unsigned long bist) { static const struct mem_controller memctrl [] = { {.channel0 = {(0xa<<3)|0, (0xa<<3)|1}} @@ -175,6 +165,9 @@ uart_init(); console_init(); + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + pll_reset(); cpuRegInit(); Modified: trunk/src/mainboard/wyse/s50/Kconfig ============================================================================== --- trunk/src/mainboard/wyse/s50/Kconfig Mon Jul 26 23:45:11 2010 (r5668) +++ trunk/src/mainboard/wyse/s50/Kconfig Tue Jul 27 01:46:25 2010 (r5669) @@ -23,8 +23,9 @@ select CPU_AMD_GX2 select NORTHBRIDGE_AMD_GX2 select SOUTHBRIDGE_AMD_CS5536 - select ROMCC select UDELAY_TSC + select USE_DCACHE_RAM + select USE_PRINTK_IN_CAR select HAVE_PIRQ_TABLE select PIRQ_ROUTE select BOARD_ROMSIZE_KB_256 Modified: trunk/src/mainboard/wyse/s50/romstage.c ============================================================================== --- trunk/src/mainboard/wyse/s50/romstage.c Mon Jul 26 23:45:11 2010 (r5668) +++ trunk/src/mainboard/wyse/s50/romstage.c Tue Jul 27 01:46:25 2010 (r5669) @@ -23,7 +23,6 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> #include "lib/ramtest.c" @@ -122,32 +121,9 @@ #include "northbridge/amd/gx2/pll_reset.c" #include "cpu/amd/model_gx2/cpureginit.c" #include "cpu/amd/model_gx2/syspreinit.c" +#include "cpu/amd/model_lx/msrinit.c" -static void msr_init(void) -{ - /* Setup access to cache under 1MB. - __builtin_wrmsr(CPU_RCONF_DEFAULT, 0x1000a000, 0x24fffc02); /* Rom Properties: Write Serialize, WriteProtect. - * RomBase: 0xFFFC0 - * SysTop to RomBase Properties: Write Serialize, Cache Disable. - * SysTop: 0x000A0 - * System Memory Properties: (Write Back) */ - - __builtin_wrmsr(CPU_RCONF_A0_BF, 0x00000000, 0x00000000); /* 0xA0000-0xBFFFF : (Write Back) */ - __builtin_wrmsr(CPU_RCONF_C0_DF, 0x00000000, 0x00000000); /* 0xC0000-0xDFFFF : (Write Back) */ - __builtin_wrmsr(CPU_RCONF_E0_FF, 0x00000000, 0x00000000); /* 0xE0000-0xFFFFF : (Write Back) */ - - /* Setup access to memory under 1MB. Note: VGA hole at 0xA0000-0xBFFFF */ - __builtin_wrmsr(MSR_GLIU0_BASE1, 0x000fff80, 0x20000000); /* 0x00000-0x7FFFF */ - __builtin_wrmsr(MSR_GLIU0_BASE2, 0x080fffe0, 0x20000000); /* 0x80000-0x9FFFF */ - __builtin_wrmsr(MSR_GLIU0_SHADOW, 0xffff0003, 0x2000ffff); /* 0xC0000-0xFFFFF */ - __builtin_wrmsr(MSR_GLIU1_BASE1, 0x000fff80, 0x20000000); /* 0x00000-0x7FFFF */ - __builtin_wrmsr(MSR_GLIU1_BASE2, 0x080fffe0, 0x20000000); /* 0x80000-0x9FFFF */ - __builtin_wrmsr(MSR_GLIU1_SHADOW, 0xffff0003, 0x2000ffff); /* 0xC0000-0xFFFFF */ - - /* put code in northbridge[init].c here */ -} - -static void main(unsigned long bist) +void main(unsigned long bist) { static const struct mem_controller memctrl [] = { {.channel0 = {(0xa<<3)|0, (0xa<<3)|1}} @@ -166,6 +142,9 @@ uart_init(); console_init(); + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + pll_reset(); cpuRegInit(); Modified: trunk/src/northbridge/amd/gx2/pll_reset.c ============================================================================== --- trunk/src/northbridge/amd/gx2/pll_reset.c Mon Jul 26 23:45:11 2010 (r5668) +++ trunk/src/northbridge/amd/gx2/pll_reset.c Tue Jul 27 01:46:25 2010 (r5669) @@ -4,6 +4,7 @@ #define CALIBRATE_INTERVAL ((20*CLOCK_TICK_RATE)/1000) /* 20ms */ #define CALIBRATE_DIVISOR (20*1000) /* 20ms / 20000 == 1usec */ +#if 0 static unsigned int calibrate_tsc(void) { /* Set the Gate high, disable speaker */ @@ -64,6 +65,7 @@ print_err("bad_ctc\n"); return 0; } +#endif /* spll_raw_clk = SYSREF * FbDIV, * GLIU Clock = spll_raw_clk / MDIV Modified: trunk/src/northbridge/amd/gx2/raminit.c ============================================================================== --- trunk/src/northbridge/amd/gx2/raminit.c Mon Jul 26 23:45:11 2010 (r5668) +++ trunk/src/northbridge/amd/gx2/raminit.c Tue Jul 27 01:46:25 2010 (r5669) @@ -102,17 +102,14 @@ msr.lo = 0x8ea0ad6a; wrmsr(0x4c00000f, msr); - /* Fixes from Jordan Crouse of AMD. */ - - /* make sure there is nothing stale in the cache */ - __asm__("wbinvd\n"); - - print_debug("RAM DLL lock\n"); /* The RAM dll needs a write to lock on so generate a few dummy writes */ + /* Note: The descriptor needs to be enabled to point at memory */ volatile unsigned long *ptr; - for (i=0;i<5;i++) { + for (i = 0; i < 5; i++) { ptr = (void *)i; *ptr = (unsigned long)i; } + print_info("RAM DLL lock\n"); + } Modified: trunk/src/northbridge/amd/gx2/raminit.h ============================================================================== --- trunk/src/northbridge/amd/gx2/raminit.h Mon Jul 26 23:45:11 2010 (r5668) +++ trunk/src/northbridge/amd/gx2/raminit.h Tue Jul 27 01:46:25 2010 (r5669) @@ -7,4 +7,6 @@ uint16_t channel0[DIMM_SOCKETS]; }; +void sdram_initialize(int controllers, const struct mem_controller *ctrl); + #endif /* RAMINIT_H */ Modified: trunk/src/southbridge/amd/cs5535/chipsetinit.c ============================================================================== --- trunk/src/southbridge/amd/cs5535/chipsetinit.c Mon Jul 26 23:45:11 2010 (r5668) +++ trunk/src/southbridge/amd/cs5535/chipsetinit.c Tue Jul 27 01:46:25 2010 (r5669) @@ -13,8 +13,6 @@ #include <cpu/x86/msr.h> #include <cpu/x86/cache.h> #include "southbridge/amd/cs5535/cs5535.h" -// This code uses some cs5536 includes because cs5535 includes are empty: -#include "southbridge/amd/cs5536/cs5536.h" /* the structs in this file only set msr.lo. But ... that may not always be true */ Modified: trunk/src/southbridge/amd/cs5535/cs5535.h ============================================================================== --- trunk/src/southbridge/amd/cs5535/cs5535.h Mon Jul 26 23:45:11 2010 (r5668) +++ trunk/src/southbridge/amd/cs5535/cs5535.h Tue Jul 27 01:46:25 2010 (r5669) @@ -1,4 +1,125 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Nils Jacobs + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + #ifndef _CS5535_H #define _CS5535_H +/* SouthBridge Equates */ +#define CS5535_GLINK_PORT_NUM 0x02 /* port of the SouthBridge */ +#define NB_PCI ((2 << 29) + (4 << 26)) /* NB GLPCI is in the same location on all Geodes. */ +#define MSR_SB ((CS5535_GLINK_PORT_NUM << 23) + NB_PCI) /* address to the SouthBridge */ +#define SB_SHIFT 20 /* 29 -> 26 -> 23 -> 20...... When making a SB address uses this shift. */ + +#define CS5535_DEV_NUM 0x0F /* default PCI device number for CS5535 */ +#define SMBUS_IO_BASE 0x6000 +#define GPIO_IO_BASE 0x6100 +#define MFGPT_IO_BASE 0x6200 +#define ACPI_IO_BASE 0x9C00 +#define PMS_IO_BASE 0x9D00 + +/* Cs5536 as follows. */ +/* SB_GLIU */ +/* port0 - GLIU */ +/* port1 - GLPCI */ +/* port2 - USB Controller #2 */ +/* port3 - ATA-5 Controller */ +/* port4 - MDD */ +/* port5 - AC97 */ +/* port6 - USB Controller #1 */ +/* port7 - GLCP */ + +#define MSR_SB_GLIU ((9 << 14) + MSR_SB) /* 51024xxx or 510*xxxx - fake out just like GL0 on CPU. */ +#define MSR_SB_GLPCI (MSR_SB) /* 5100xxxx - don't go to the GLIU */ +#define MSR_SB_USB2 ((2 << SB_SHIFT) + MSR_SB) /* 5120xxxx */ +#define MSR_SB_ATA ((3 << SB_SHIFT) + MSR_SB) /* 5130xxxx */ +#define MSR_SB_MDD ((4 << SB_SHIFT) + MSR_SB) /* 5140xxxx, a.k.a. DIVIL = Diverse Integrated Logic device */ +#define MSR_SB_AC97 ((5 << SB_SHIFT) + MSR_SB) /* 5150xxxx */ +#define MSR_SB_USB1 ((6 << SB_SHIFT) + MSR_SB) /* 5160xxxx */ +#define MSR_SB_GLCP ((7 << SB_SHIFT) + MSR_SB) /* 5170xxxx */ + +/* GLIU */ +#define GLIU_SB_GLD_MSR_PM (MSR_SB_GLIU + 0x04) + +/* USB1 */ +#define USB1_SB_GLD_MSR_CONF (MSR_SB_USB1 + 0x01) +#define USB1_SB_GLD_MSR_PM (MSR_SB_USB1 + 0x04) + +/* USB2 */ +#define USB2_SB_GLD_MSR_CONF (MSR_SB_USB2 + 0x01) +#define USB2_SB_GLD_MSR_PM (MSR_SB_USB2 + 0x04) + +/* ATA */ +#define ATA_SB_GLD_MSR_CONF (MSR_SB_ATA + 0x01) +#define ATA_SB_GLD_MSR_ERR (MSR_SB_ATA + 0x03) +#define ATA_SB_GLD_MSR_PM (MSR_SB_ATA + 0x04) + +/* AC97 */ +#define AC97_SB_GLD_MSR_CONF (MSR_SB_AC97 + 0x01) +#define AC97_SB_GLD_MSR_PM (MSR_SB_AC97 + 0x04) + +/* GLPCI */ +#define GLPCI_SB_GLD_MSR_PM (MSR_SB_GLPCI + 0x04) +#define GLPCI_SB_CTRL (MSR_SB_GLPCI + 0x10) +#define GLPCI_CRTL_PPIDE_SET (1 << 17) + +/* GLCP */ +#define GLCP_SB_GLD_MSR_PM (MSR_SB_GLCP + 0x04) + +/* MDD */ +#define MDD_SB_GLD_MSR_CONF (MSR_SB_MDD + 0x01) +#define MDD_SB_GLD_MSR_PM (MSR_SB_MDD + 0x04) +#define MDD_LBAR_SMB (MSR_SB_MDD + 0x0B) +#define MDD_LBAR_GPIO (MSR_SB_MDD + 0x0C) +#define MDD_LBAR_MFGPT (MSR_SB_MDD + 0x0D) +#define MDD_LBAR_ACPI (MSR_SB_MDD + 0x0E) +#define MDD_LBAR_PMS (MSR_SB_MDD + 0x0F) +#define MDD_LBAR_FLSH0 (MSR_SB_MDD + 0x010) +#define MDD_LBAR_FLSH1 (MSR_SB_MDD + 0x011) +#define MDD_LBAR_FLSH2 (MSR_SB_MDD + 0x012) +#define MDD_LBAR_FLSH3 (MSR_SB_MDD + 0x013) +#define MDD_PIN_OPT (MSR_SB_MDD + 0x015) +#define MDD_NORF_CNTRL (MSR_SB_MDD + 0x018) + +/* GPIO */ +#define GPIOL_2_SET (1 << 2) + +/* GPIO LOW Bank Bit Registers */ +#define GPIOL_INPUT_ENABLE (0x20) +#define GPIOL_IN_AUX1_SELECT (0x34) + +/* FLASH device macros */ +#define FLASH_TYPE_NONE 0 /* No flash device installed */ +#define FLASH_TYPE_NAND 1 /* NAND device */ + +#define FLASH_IF_MEM 1 /* Memory or memory-mapped I/O interface for Flash device */ + +/* Flash Memory Mask values */ +#define FLASH_MEM_4K 0xFFFFF000 + +#if !defined(ASSEMBLY) && !defined(__ROMCC__) +#if defined(__PRE_RAM__) +void cs5535_disable_internal_uart(void); +#else +void chipsetinit(void); #endif +#endif + +#endif /* _CS5535_H */ Modified: trunk/src/southbridge/amd/cs5535/cs5535_early_setup.c ============================================================================== --- trunk/src/southbridge/amd/cs5535/cs5535_early_setup.c Mon Jul 26 23:45:11 2010 (r5668) +++ trunk/src/southbridge/amd/cs5535/cs5535_early_setup.c Tue Jul 27 01:46:25 2010 (r5669) @@ -8,9 +8,6 @@ * */ -#define CS5535_GLINK_PORT_NUM 0x02 /* the geode link port number to the CS5535 */ -#define CS5535_DEV_NUM 0x0F /* default PCI device number for CS5535 */ - /** * @brief Setup PCI IDSEL for CS5535 * @@ -51,46 +48,33 @@ } } -static int cs5535_setup_iobase(void) +static void cs5535_setup_iobase(void) { msr_t msr; - /* setup LBAR for SMBus controller */ - __builtin_wrmsr(0x5140000b, 0x00006000, 0x0000f001); + msr.hi = 0x0000f001; + msr.lo = SMBUS_IO_BASE; + wrmsr(MDD_LBAR_SMB, msr); + /* setup LBAR for GPIO */ - __builtin_wrmsr(0x5140000c, 0x00006100, 0x0000f001); + msr.hi = 0x0000f001; + msr.lo = GPIO_IO_BASE; + wrmsr(MDD_LBAR_GPIO, msr); + /* setup LBAR for MFGPT */ - __builtin_wrmsr(0x5140000d, 0x00006200, 0x0000f001); - /* setup LBAR for ACPI */ - __builtin_wrmsr(0x5140000e, 0x00009c00, 0x0000f001); - /* setup LBAR for PM Support */ - __builtin_wrmsr(0x5140000f, 0x00009d00, 0x0000f001); -} + msr.hi = 0x0000f001; + msr.lo = MFGPT_IO_BASE; + wrmsr(MDD_LBAR_MFGPT, msr); -static void cs5535_setup_power_bottun(void) -{ - /* not implemented yet */ -#if 0 - pwrBtn_setup: - ; - ; Power Button Setup - ; - ;mov eax, 0C0020000h ; 4 seconds + lock - mov eax, 040020000h ; 4 seconds no lock - mov dx, PMLogic_BASE + 40h - out dx, eax - - ; setup GPIO24, it is the external signal for 5535 vsb_work_aux - ; which controls all voltage rails except Vstandby & Vmem. - ; We need to enable, OUT_AUX1 and OUTPUT_ENABLE in this order. - ; If GPIO24 is not enabled then soft-off will not work. - mov dx, GPIOH_OUT_AUX1_SELECT - mov eax, GPIOH_24_SET - out dx, eax - mov dx, GPIOH_OUTPUT_ENABLE - out dx, eax + /* setup LBAR for ACPI */ + msr.hi = 0x0000f001; + msr.lo = ACPI_IO_BASE; + wrmsr(MDD_LBAR_ACPI, msr); -#endif + /* setup LBAR for PM Support */ + msr.hi = 0x0000f001; + msr.lo = PMS_IO_BASE; + wrmsr(MDD_LBAR_PMS, msr); } static void cs5535_setup_gpio(void) @@ -115,27 +99,8 @@ //outl(val, 0x6100 + 0x34); } -static void cs5535_disable_internal_uart(void) +void cs5535_disable_internal_uart(void) { - /* not implemented yet */ -#if 0 - ; The UARTs default to enabled. - ; Disable and reset them and configure them later. (SIO init) - mov ecx, MDD_UART1_CONF - RDMSR - mov eax, 1h ; reset - WRMSR - mov eax, 0h ; disabled - WRMSR - - mov ecx, MDD_UART2_CONF - RDMSR - mov eax, 1h ; reset - WRMSR - mov eax, 0h ; disabled - WRMSR - -#endif } static void cs5535_setup_cis_mode(void) @@ -143,19 +108,21 @@ msr_t msr; /* setup CPU interface serial to mode C on both sides */ - msr = __builtin_rdmsr(0x51000010); + msr = rdmsr(GLPCI_SB_CTRL); msr.lo &= ~0x18; msr.lo |= 0x10; - __builtin_wrmsr(0x51000010, msr.lo, msr.hi); + wrmsr(GLPCI_SB_CTRL, msr); //Only do this if we are building for 5535 - __builtin_wrmsr(0x54002010, 0x00000002, 0x00000000); + msr.lo = 0x2; + msr.hi = 0x0; + wrmsr(VIP_GIO_MSR_SEL, msr); } static void dummy(void) { } -static int cs5535_early_setup(void) +static void cs5535_early_setup(void) { msr_t msr; Modified: trunk/src/southbridge/amd/cs5535/cs5535_early_smbus.c ============================================================================== --- trunk/src/southbridge/amd/cs5535/cs5535_early_smbus.c Mon Jul 26 23:45:11 2010 (r5668) +++ trunk/src/southbridge/amd/cs5535/cs5535_early_smbus.c Tue Jul 27 01:46:25 2010 (r5669) @@ -3,7 +3,7 @@ #define SMBUS_IO_BASE 0x6000 /* initialization for SMBus Controller */ -static int cs5535_enable_smbus(void) +static void cs5535_enable_smbus(void) { unsigned char val; @@ -20,26 +20,3 @@ val |= (0xEF | SMB_ADD_SAEN); outb(val, SMBUS_IO_BASE + SMB_ADD); } - -static int smbus_read_byte(unsigned device, unsigned address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address-1); -} - -#if 0 -static int smbus_recv_byte(unsigned device) -{ - return do_smbus_recv_byte(SMBUS_IO_BASE, device); -} - -static int smbus_send_byte(unsigned device, unsigned char val) -{ - return do_smbus_send_byte(SMBUS_IO_BASE, device, val); -} - - -static int smbus_write_byte(unsigned device, unsigned address, unsigned char val) -{ - return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val); -} -#endif Modified: trunk/src/southbridge/amd/cs5535/cs5535_smbus.h ============================================================================== --- trunk/src/southbridge/amd/cs5535/cs5535_smbus.h Mon Jul 26 23:45:11 2010 (r5668) +++ trunk/src/southbridge/amd/cs5535/cs5535_smbus.h Tue Jul 27 01:46:25 2010 (r5669) @@ -44,137 +44,3 @@ #define SMBUS_STATUS_MASK 0xfbff #define SMBUS_IO_BASE 0x6000 - -static void smbus_delay(void) -{ - outb(0x80, 0x80); -} - -/* generate a smbus start condition */ -static int smbus_start_condition(unsigned smbus_io_base) -{ - unsigned char val; - unsigned long loops; - loops = SMBUS_TIMEOUT; - - /* issue a START condition */ - val = inb(smbus_io_base + SMB_CTRL1); - outb(val | SMB_CTRL1_START, smbus_io_base + SMB_CTRL1); - - /* check for bus conflict */ - val = inb(smbus_io_base + SMB_STS); - if ((val & SMB_STS_BER) != 0) - return SMBUS_ERROR; - - /* check for SDA status */ - do { - smbus_delay(); - val = inw(smbus_io_base + SMB_STS); - if ((val & SMB_STS_SDAST) != 0) { - break; - } - } while(--loops); - return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT; -} - -static int smbus_check_stop_condition(unsigned smbus_io_base) -{ - unsigned char val; - unsigned long loops; - loops = SMBUS_TIMEOUT; - /* check for SDA status */ - do { - smbus_delay(); - val = inw(smbus_io_base + SMB_CTRL1); - if ((val & SMB_CTRL1_STOP) == 0) { - break; - } - } while(--loops); - return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT; -} - -static int smbus_stop_condition(unsigned smbus_io_base) -{ - unsigned char val; - val = inb(smbus_io_base + SMB_CTRL1); - outb(SMB_CTRL1_STOP, smbus_io_base + SMB_CTRL1); -} - -static int smbus_send_slave_address(unsigned smbus_io_base, unsigned char device) -{ - unsigned char val; - unsigned long loops; - loops = SMBUS_TIMEOUT; - - /* send the slave address */ - outb(device, smbus_io_base + SMB_SDA); - - /* check for bus conflict and NACK */ - val = inb(smbus_io_base + SMB_STS); - if (((val & SMB_STS_BER) != 0) || - ((val & SMB_STS_NEGACK) != 0)) - return SMBUS_ERROR; - - /* check for SDA status */ - do { - smbus_delay(); - val = inw(smbus_io_base + SMB_STS); - if ((val & SMB_STS_SDAST) != 0) { - break; - } - } while(--loops); - return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT; -} - -static int smbus_send_command(unsigned smbus_io_base, unsigned char command) -{ - unsigned char val; - unsigned long loops; - loops = SMBUS_TIMEOUT; - - /* send the command */ - outb(command, smbus_io_base + SMB_SDA); - - /* check for bus conflict and NACK */ - val = inb(smbus_io_base + SMB_STS); - if (((val & SMB_STS_BER) != 0) || - ((val & SMB_STS_NEGACK) != 0)) - return SMBUS_ERROR; - - /* check for SDA status */ - do { - smbus_delay(); - val = inw(smbus_io_base + SMB_STS); - if ((val & SMB_STS_SDAST) != 0) { - break; - } - } while(--loops); - return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT; -} - -static unsigned char do_smbus_read_byte(unsigned smbus_io_base, unsigned char device, unsigned char address) -{ - unsigned char val, val1; - - smbus_check_stop_condition(smbus_io_base); - - smbus_start_condition(smbus_io_base); - - smbus_send_slave_address(smbus_io_base, device); - - smbus_send_command(smbus_io_base, address); - - smbus_start_condition(smbus_io_base); - - smbus_send_slave_address(smbus_io_base, device | 0x01); - - /* send NACK to slave */ - val = inb(smbus_io_base + SMB_CTRL1); - outb(val | SMB_CTRL1_ACK, smbus_io_base + SMB_CTRL1); - - val = inb(smbus_io_base + SMB_SDA); - - //smbus_stop_condition(smbus_io_base); - - return val; -}

1 0

Re: [coreboot] Broken include paths
by Nils 26 Jul '10

26 Jul '10

Myles wrote: >Linux does it that way. It keeps all of the architecture-specific >code and includes under arch/ > >include_path.diff: fix the ones that are broken for me. >include_path2.diff: fix the ones that look identical but work anyway. >include_path3.diff: fix <../path/file.h> to be "../../../path/file.h" >to make it obvious that they're not in src/include > >Abuild tested. > >Signed-off-by: Myles Watson <mylesgw at gmail.com> I like that. Acked-by: Nils Jacobs <njacobs8(a)hetnet.nl> Thanks,Nils.

2 1

[commit] r5668 - in trunk/src: mainboard/amd/dbm690t mainboard/amd/mahogany mainboard/amd/mahogany_fam10 mainboard/amd/pistachio mainboard/amd/serengeti_cheetah mainboard/amd/tilapia_fam10 mainboar...
by repository service 26 Jul '10

26 Jul '10

Author: myles Date: Mon Jul 26 23:45:11 2010 New Revision: 5668 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5668 Log: Make include paths more consistent. Fixes compilation errors for me. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Nils Jacobs <njacobs8(a)hetnet.nl> Modified: trunk/src/mainboard/amd/dbm690t/acpi_tables.c trunk/src/mainboard/amd/dbm690t/fadt.c trunk/src/mainboard/amd/mahogany/acpi_tables.c trunk/src/mainboard/amd/mahogany/fadt.c trunk/src/mainboard/amd/mahogany_fam10/fadt.c trunk/src/mainboard/amd/pistachio/acpi_tables.c trunk/src/mainboard/amd/pistachio/fadt.c trunk/src/mainboard/amd/serengeti_cheetah/acpi_tables.c trunk/src/mainboard/amd/tilapia_fam10/fadt.c trunk/src/mainboard/asrock/939a785gmh/acpi_tables.c trunk/src/mainboard/asrock/939a785gmh/fadt.c trunk/src/mainboard/asus/a8v-e_se/acpi_tables.c trunk/src/mainboard/asus/a8v-e_se/mptable.c trunk/src/mainboard/asus/m2v-mx_se/acpi_tables.c trunk/src/mainboard/gigabyte/m57sli/acpi_tables.c trunk/src/mainboard/iwill/dk8_htx/acpi_tables.c trunk/src/mainboard/kontron/kt690/acpi_tables.c trunk/src/mainboard/kontron/kt690/fadt.c trunk/src/mainboard/msi/ms9652_fam10/acpi_tables.c trunk/src/mainboard/technexion/tim5690/acpi_tables.c trunk/src/mainboard/technexion/tim5690/fadt.c trunk/src/mainboard/technexion/tim5690/speaker.c trunk/src/mainboard/technexion/tim8690/acpi_tables.c trunk/src/mainboard/technexion/tim8690/fadt.c trunk/src/mainboard/tyan/s2891/acpi_tables.c trunk/src/mainboard/tyan/s2892/acpi_tables.c trunk/src/mainboard/tyan/s2895/acpi_tables.c trunk/src/mainboard/via/epia-m700/acpi_tables.c trunk/src/mainboard/via/epia-m700/fadt.c trunk/src/mainboard/via/pc2500e/mptable.c trunk/src/northbridge/via/vx800/examples/chipset_init.c Modified: trunk/src/mainboard/amd/dbm690t/acpi_tables.c ============================================================================== --- trunk/src/mainboard/amd/dbm690t/acpi_tables.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/amd/dbm690t/acpi_tables.c Mon Jul 26 23:45:11 2010 (r5668) @@ -25,7 +25,7 @@ #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/amdk8_sysconf.h> -#include <../../../northbridge/amd/amdk8/amdk8_acpi.h> +#include "../../../northbridge/amd/amdk8/amdk8_acpi.h" #include <arch/cpu.h> #include <cpu/amd/model_fxx_powernow.h> Modified: trunk/src/mainboard/amd/dbm690t/fadt.c ============================================================================== --- trunk/src/mainboard/amd/dbm690t/fadt.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/amd/dbm690t/fadt.c Mon Jul 26 23:45:11 2010 (r5668) @@ -26,7 +26,7 @@ #include <arch/acpi.h> #include <arch/io.h> #include <device/device.h> -#include <../southbridge/amd/sb600/sb600.h> +#include "../../../southbridge/amd/sb600/sb600.h" /*extern*/ u16 pm_base = 0x800; /* pm_base should be set in sb acpi */ Modified: trunk/src/mainboard/amd/mahogany/acpi_tables.c ============================================================================== --- trunk/src/mainboard/amd/mahogany/acpi_tables.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/amd/mahogany/acpi_tables.c Mon Jul 26 23:45:11 2010 (r5668) @@ -25,7 +25,7 @@ #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/amdk8_sysconf.h> -#include <../../../northbridge/amd/amdk8/amdk8_acpi.h> +#include "../../../northbridge/amd/amdk8/amdk8_acpi.h" #include <arch/cpu.h> #include <cpu/amd/model_fxx_powernow.h> Modified: trunk/src/mainboard/amd/mahogany/fadt.c ============================================================================== --- trunk/src/mainboard/amd/mahogany/fadt.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/amd/mahogany/fadt.c Mon Jul 26 23:45:11 2010 (r5668) @@ -26,7 +26,7 @@ #include <arch/acpi.h> #include <arch/io.h> #include <device/device.h> -#include <../southbridge/amd/sb700/sb700.h> +#include "../../../southbridge/amd/sb700/sb700.h" /*extern*/ u16 pm_base = 0x800; /* pm_base should be set in sb acpi */ Modified: trunk/src/mainboard/amd/mahogany_fam10/fadt.c ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/fadt.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/amd/mahogany_fam10/fadt.c Mon Jul 26 23:45:11 2010 (r5668) @@ -26,7 +26,7 @@ #include <arch/acpi.h> #include <arch/io.h> #include <device/device.h> -#include <../southbridge/amd/sb700/sb700.h> +#include "../../../southbridge/amd/sb700/sb700.h" /*extern*/ u16 pm_base = 0x800; /* pm_base should be set in sb acpi */ Modified: trunk/src/mainboard/amd/pistachio/acpi_tables.c ============================================================================== --- trunk/src/mainboard/amd/pistachio/acpi_tables.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/amd/pistachio/acpi_tables.c Mon Jul 26 23:45:11 2010 (r5668) @@ -25,7 +25,7 @@ #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/amdk8_sysconf.h> -#include <../../../northbridge/amd/amdk8/amdk8_acpi.h> +#include "../../../northbridge/amd/amdk8/amdk8_acpi.h" #include <arch/cpu.h> #include <cpu/amd/model_fxx_powernow.h> Modified: trunk/src/mainboard/amd/pistachio/fadt.c ============================================================================== --- trunk/src/mainboard/amd/pistachio/fadt.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/amd/pistachio/fadt.c Mon Jul 26 23:45:11 2010 (r5668) @@ -26,7 +26,7 @@ #include <arch/acpi.h> #include <arch/io.h> #include <device/device.h> -#include <../southbridge/amd/sb600/sb600.h> +#include "../../../southbridge/amd/sb600/sb600.h" /*extern*/ u16 pm_base = 0x800; /* pm_base should be set in sb acpi */ Modified: trunk/src/mainboard/amd/serengeti_cheetah/acpi_tables.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah/acpi_tables.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/amd/serengeti_cheetah/acpi_tables.c Mon Jul 26 23:45:11 2010 (r5668) @@ -16,7 +16,7 @@ #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/amdk8_sysconf.h> -#include <../../../northbridge/amd/amdk8/amdk8_acpi.h> +#include "../../../northbridge/amd/amdk8/amdk8_acpi.h" #include "mb_sysconf.h" Modified: trunk/src/mainboard/amd/tilapia_fam10/fadt.c ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/fadt.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/amd/tilapia_fam10/fadt.c Mon Jul 26 23:45:11 2010 (r5668) @@ -26,7 +26,7 @@ #include <arch/acpi.h> #include <arch/io.h> #include <device/device.h> -#include <../southbridge/amd/sb700/sb700.h> +#include "../../../southbridge/amd/sb700/sb700.h" /*extern*/ u16 pm_base = 0x800; /* pm_base should be set in sb acpi */ Modified: trunk/src/mainboard/asrock/939a785gmh/acpi_tables.c ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/acpi_tables.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/asrock/939a785gmh/acpi_tables.c Mon Jul 26 23:45:11 2010 (r5668) @@ -25,7 +25,7 @@ #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/amdk8_sysconf.h> -#include <../../../northbridge/amd/amdk8/amdk8_acpi.h> +#include "../../../northbridge/amd/amdk8/amdk8_acpi.h" #include <arch/cpu.h> #include <cpu/amd/model_fxx_powernow.h> Modified: trunk/src/mainboard/asrock/939a785gmh/fadt.c ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/fadt.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/asrock/939a785gmh/fadt.c Mon Jul 26 23:45:11 2010 (r5668) @@ -26,7 +26,7 @@ #include <arch/acpi.h> #include <arch/io.h> #include <device/device.h> -#include <../southbridge/amd/sb700/sb700.h> +#include "../../../southbridge/amd/sb700/sb700.h" /*extern*/ u16 pm_base = 0x800; /* pm_base should be set in sb acpi */ Modified: trunk/src/mainboard/asus/a8v-e_se/acpi_tables.c ============================================================================== --- trunk/src/mainboard/asus/a8v-e_se/acpi_tables.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/asus/a8v-e_se/acpi_tables.c Mon Jul 26 23:45:11 2010 (r5668) @@ -28,8 +28,8 @@ #include <arch/smp/mpspec.h> #include <device/device.h> #include <device/pci_ids.h> -#include <../../../southbridge/via/vt8237r/vt8237r.h> -#include <../../../southbridge/via/k8t890/k8t890.h> +#include "../../../southbridge/via/vt8237r/vt8237r.h" +#include "../../../southbridge/via/k8t890/k8t890.h" extern const unsigned char AmlCode[]; Modified: trunk/src/mainboard/asus/a8v-e_se/mptable.c ============================================================================== --- trunk/src/mainboard/asus/a8v-e_se/mptable.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/asus/a8v-e_se/mptable.c Mon Jul 26 23:45:11 2010 (r5668) @@ -20,8 +20,8 @@ #include <string.h> #include <stdint.h> #include <arch/smp/mpspec.h> -#include <../../../southbridge/via/vt8237r/vt8237r.h> -#include <../../../southbridge/via/k8t890/k8t890.h> +#include "../../../southbridge/via/vt8237r/vt8237r.h" +#include "../../../southbridge/via/k8t890/k8t890.h" static void *smp_write_config_table(void *v) { Modified: trunk/src/mainboard/asus/m2v-mx_se/acpi_tables.c ============================================================================== --- trunk/src/mainboard/asus/m2v-mx_se/acpi_tables.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/asus/m2v-mx_se/acpi_tables.c Mon Jul 26 23:45:11 2010 (r5668) @@ -28,9 +28,9 @@ #include <arch/smp/mpspec.h> #include <device/device.h> #include <device/pci_ids.h> -#include <../../../southbridge/via/vt8237r/vt8237r.h> -#include <../../../southbridge/via/k8t890/k8t890.h> -#include <../../../northbridge/amd/amdk8/amdk8_acpi.h> +#include "../../../southbridge/via/vt8237r/vt8237r.h" +#include "../../../southbridge/via/k8t890/k8t890.h" +#include "../../../northbridge/amd/amdk8/amdk8_acpi.h" #include <cpu/amd/model_fxx_powernow.h> extern const unsigned char AmlCode[]; Modified: trunk/src/mainboard/gigabyte/m57sli/acpi_tables.c ============================================================================== --- trunk/src/mainboard/gigabyte/m57sli/acpi_tables.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/gigabyte/m57sli/acpi_tables.c Mon Jul 26 23:45:11 2010 (r5668) @@ -29,7 +29,7 @@ #include <arch/smp/mpspec.h> #include <device/device.h> #include <device/pci_ids.h> -#include <../../../northbridge/amd/amdk8/amdk8_acpi.h> +#include "../../../northbridge/amd/amdk8/amdk8_acpi.h" #include <cpu/amd/model_fxx_powernow.h> #include <device/pci.h> #include <cpu/amd/amdk8_sysconf.h> Modified: trunk/src/mainboard/iwill/dk8_htx/acpi_tables.c ============================================================================== --- trunk/src/mainboard/iwill/dk8_htx/acpi_tables.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/iwill/dk8_htx/acpi_tables.c Mon Jul 26 23:45:11 2010 (r5668) @@ -16,7 +16,7 @@ #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/amdk8_sysconf.h> -#include <../../../northbridge/amd/amdk8/amdk8_acpi.h> +#include "../../../northbridge/amd/amdk8/amdk8_acpi.h" #include "mb_sysconf.h" Modified: trunk/src/mainboard/kontron/kt690/acpi_tables.c ============================================================================== --- trunk/src/mainboard/kontron/kt690/acpi_tables.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/kontron/kt690/acpi_tables.c Mon Jul 26 23:45:11 2010 (r5668) @@ -25,7 +25,7 @@ #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/amdk8_sysconf.h> -#include <../../../northbridge/amd/amdk8/amdk8_acpi.h> +#include "../../../northbridge/amd/amdk8/amdk8_acpi.h" #include <arch/cpu.h> #include <cpu/amd/model_fxx_powernow.h> Modified: trunk/src/mainboard/kontron/kt690/fadt.c ============================================================================== --- trunk/src/mainboard/kontron/kt690/fadt.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/kontron/kt690/fadt.c Mon Jul 26 23:45:11 2010 (r5668) @@ -26,7 +26,7 @@ #include <arch/acpi.h> #include <arch/io.h> #include <device/device.h> -#include <../southbridge/amd/sb600/sb600.h> +#include "../../../southbridge/amd/sb600/sb600.h" /*extern*/ u16 pm_base = 0x800; /* pm_base should be set in sb acpi */ Modified: trunk/src/mainboard/msi/ms9652_fam10/acpi_tables.c ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/acpi_tables.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/msi/ms9652_fam10/acpi_tables.c Mon Jul 26 23:45:11 2010 (r5668) @@ -29,7 +29,7 @@ #include <arch/smp/mpspec.h> #include <device/device.h> #include <device/pci_ids.h> -//#include <../../../northbridge/amd/amdfam10/amdfam10_acpi.h> +//#include "../../../northbridge/amd/amdfam10/amdfam10_acpi.h" #include <cpu/amd/model_fxx_powernow.h> #include <device/pci.h> #include <cpu/amd/amdfam10_sysconf.h> Modified: trunk/src/mainboard/technexion/tim5690/acpi_tables.c ============================================================================== --- trunk/src/mainboard/technexion/tim5690/acpi_tables.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/technexion/tim5690/acpi_tables.c Mon Jul 26 23:45:11 2010 (r5668) @@ -25,7 +25,7 @@ #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/amdk8_sysconf.h> -#include <../../../northbridge/amd/amdk8/amdk8_acpi.h> +#include "../../../northbridge/amd/amdk8/amdk8_acpi.h" #include <arch/cpu.h> #include <cpu/amd/model_fxx_powernow.h> Modified: trunk/src/mainboard/technexion/tim5690/fadt.c ============================================================================== --- trunk/src/mainboard/technexion/tim5690/fadt.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/technexion/tim5690/fadt.c Mon Jul 26 23:45:11 2010 (r5668) @@ -26,7 +26,7 @@ #include <arch/acpi.h> #include <arch/io.h> #include <device/device.h> -#include <../southbridge/amd/sb600/sb600.h> +#include "../../../southbridge/amd/sb600/sb600.h" /*extern*/ u16 pm_base = 0x800; /* pm_base should be set in sb acpi */ Modified: trunk/src/mainboard/technexion/tim5690/speaker.c ============================================================================== --- trunk/src/mainboard/technexion/tim5690/speaker.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/technexion/tim5690/speaker.c Mon Jul 26 23:45:11 2010 (r5668) @@ -29,7 +29,7 @@ #include <arch/io.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <../southbridge/amd/sb600/sb600.h> +#include "../../../southbridge/amd/sb600/sb600.h" #include <delay.h> #endif /* __PRE_RAM__ */ Modified: trunk/src/mainboard/technexion/tim8690/acpi_tables.c ============================================================================== --- trunk/src/mainboard/technexion/tim8690/acpi_tables.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/technexion/tim8690/acpi_tables.c Mon Jul 26 23:45:11 2010 (r5668) @@ -25,7 +25,7 @@ #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/amdk8_sysconf.h> -#include <../../../northbridge/amd/amdk8/amdk8_acpi.h> +#include "../../../northbridge/amd/amdk8/amdk8_acpi.h" #include <arch/cpu.h> #include <cpu/amd/model_fxx_powernow.h> Modified: trunk/src/mainboard/technexion/tim8690/fadt.c ============================================================================== --- trunk/src/mainboard/technexion/tim8690/fadt.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/technexion/tim8690/fadt.c Mon Jul 26 23:45:11 2010 (r5668) @@ -26,7 +26,7 @@ #include <arch/acpi.h> #include <arch/io.h> #include <device/device.h> -#include <../southbridge/amd/sb600/sb600.h> +#include "../../../southbridge/amd/sb600/sb600.h" /*extern*/ u16 pm_base = 0x800; /* pm_base should be set in sb acpi */ Modified: trunk/src/mainboard/tyan/s2891/acpi_tables.c ============================================================================== --- trunk/src/mainboard/tyan/s2891/acpi_tables.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/tyan/s2891/acpi_tables.c Mon Jul 26 23:45:11 2010 (r5668) @@ -17,7 +17,7 @@ #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/amdk8_sysconf.h> -#include <../../../northbridge/amd/amdk8/amdk8_acpi.h> +#include "../../../northbridge/amd/amdk8/amdk8_acpi.h" #include <cpu/amd/model_fxx_powernow.h> extern const unsigned char AmlCode[]; Modified: trunk/src/mainboard/tyan/s2892/acpi_tables.c ============================================================================== --- trunk/src/mainboard/tyan/s2892/acpi_tables.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/tyan/s2892/acpi_tables.c Mon Jul 26 23:45:11 2010 (r5668) @@ -17,7 +17,7 @@ #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/amdk8_sysconf.h> -#include <../../../northbridge/amd/amdk8/amdk8_acpi.h> +#include "../../../northbridge/amd/amdk8/amdk8_acpi.h" #include <cpu/amd/model_fxx_powernow.h> extern const unsigned char AmlCode[]; Modified: trunk/src/mainboard/tyan/s2895/acpi_tables.c ============================================================================== --- trunk/src/mainboard/tyan/s2895/acpi_tables.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/tyan/s2895/acpi_tables.c Mon Jul 26 23:45:11 2010 (r5668) @@ -17,7 +17,7 @@ #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/amdk8_sysconf.h> -#include <../../../northbridge/amd/amdk8/amdk8_acpi.h> +#include "../../../northbridge/amd/amdk8/amdk8_acpi.h" #include <cpu/amd/model_fxx_powernow.h> extern const unsigned char AmlCode[]; Modified: trunk/src/mainboard/via/epia-m700/acpi_tables.c ============================================================================== --- trunk/src/mainboard/via/epia-m700/acpi_tables.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/via/epia-m700/acpi_tables.c Mon Jul 26 23:45:11 2010 (r5668) @@ -33,7 +33,7 @@ #include <arch/acpi.h> #include <device/device.h> #include <device/pci_ids.h> -#include <../../../northbridge/via/vx800/vx800.h> +#include "../../../northbridge/via/vx800/vx800.h" extern const unsigned char AmlCode_dsdt[]; extern const unsigned char AmlCode_ssdt[]; Modified: trunk/src/mainboard/via/epia-m700/fadt.c ============================================================================== --- trunk/src/mainboard/via/epia-m700/fadt.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/via/epia-m700/fadt.c Mon Jul 26 23:45:11 2010 (r5668) @@ -21,7 +21,7 @@ #include <string.h> #include <arch/acpi.h> -#include <../../../northbridge/via/vx800/vx800.h> +#include "../../../northbridge/via/vx800/vx800.h" void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) { Modified: trunk/src/mainboard/via/pc2500e/mptable.c ============================================================================== --- trunk/src/mainboard/via/pc2500e/mptable.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/mainboard/via/pc2500e/mptable.c Mon Jul 26 23:45:11 2010 (r5668) @@ -27,7 +27,7 @@ #include <device/pci.h> #include <string.h> #include <stdint.h> -#include <../../../southbridge/via/vt8237r/vt8237r.h> +#include "../../../southbridge/via/vt8237r/vt8237r.h" #define bus_isa 2 Modified: trunk/src/northbridge/via/vx800/examples/chipset_init.c ============================================================================== --- trunk/src/northbridge/via/vx800/examples/chipset_init.c Fri Jul 23 00:56:44 2010 (r5667) +++ trunk/src/northbridge/via/vx800/examples/chipset_init.c Mon Jul 26 23:45:11 2010 (r5668) @@ -21,7 +21,7 @@ #if CONFIG_HAVE_ACPI_RESUME == 1 #include <arch/acpi.h> #endif -#include <../northbridge/via/vx800/vx800.h> +#include "../vx800.h" #include <arch/io.h> #include "pci_rawops.h"

1 0

Broken include paths
by Myles Watson 26 Jul '10

26 Jul '10

There are a couple of boards that don't compile for me with crossgcc. Here's a representative error: src/mainboard/asus/a8v-e_se/mptable.c:23:54: error: src/include/../../../southbridge/via/vt8237r/vt8237r.h: Permission denied The problem is that the compiler is looking for the file ../../../southbridge... starting from src/include, since it was specified with <> There are many ways to fix it, but I'm not sure which one is the correct (most future-proof) way. Here are three of the possible fixes: 1. Use "" so the path is relative to the file. Index: svn/src/mainboard/asus/a8v-e_se/mptable.c =================================================================== --- svn/src/mainboard/asus/a8v-e_se/mptable.c (revision 5667) +++ svn/src/mainboard/asus/a8v-e_se/mptable.c (working copy) @@ -20,8 +20,8 @@ #include <string.h> #include <stdint.h> #include <arch/smp/mpspec.h> -#include <../../../southbridge/via/vt8237r/vt8237r.h> -#include <../../../southbridge/via/k8t890/k8t890.h> +#include "../../../southbridge/via/vt8237r/vt8237r.h" +#include "../../../southbridge/via/k8t890/k8t890.h" static void *smp_write_config_table(void *v) { 2. Make the path valid from src/include Index: svn/src/mainboard/asus/a8v-e_se/mptable.c =================================================================== --- svn/src/mainboard/asus/a8v-e_se/mptable.c (revision 5667) +++ svn/src/mainboard/asus/a8v-e_se/mptable.c (working copy) @@ -20,8 +20,8 @@ #include <string.h> #include <stdint.h> #include <arch/smp/mpspec.h> -#include <../../../southbridge/via/vt8237r/vt8237r.h> -#include <../../../southbridge/via/k8t890/k8t890.h> +#include <../southbridge/via/vt8237r/vt8237r.h> +#include <../southbridge/via/k8t890/k8t890.h> static void *smp_write_config_table(void *v) { 3. Just use the path Index: svn/src/mainboard/asus/a8v-e_se/mptable.c =================================================================== --- svn.orig/src/mainboard/asus/a8v-e_se/mptable.c +++ svn/src/mainboard/asus/a8v-e_se/mptable.c @@ -20,8 +20,8 @@ #include <string.h> #include <stdint.h> #include <arch/smp/mpspec.h> -#include <../../../southbridge/via/vt8237r/vt8237r.h> -#include <../../../southbridge/via/k8t890/k8t890.h> +#include <southbridge/via/vt8237r/vt8237r.h> +#include <southbridge/via/k8t890/k8t890.h> static void *smp_write_config_table(void *v) { They all compile for me. Thanks, Myles

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coreboot July 2010