coreboot July 2010

coreboot@coreboot.org

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142 discussions

Re: [coreboot] coreboot halts at "doing early_mtrr"
by austinro＠msu.edu 31 Jul '10

31 Jul '10

Quoting Corey Osgood <corey.osgood(a)gmail.com>: > Just to clarify, I'm the guy who originally wrote support for the > CN700/VT8237R and J7F2 port, and I've got a little time right now that > I can check the log out to see what's going on, so the sooner you can > get that to me, the better ;) > > -Corey > > On Fri, Jul 30, 2010 at 4:29 PM, Corey Osgood <corey.osgood(a)gmail.com> wrote: >> On Fri, Jul 30, 2010 at 2:20 PM, <austinro(a)msu.edu> wrote: >>> Quoting Patrick Georgi <patrick(a)georgi-clan.de>: >>> >>>> Am 30.07.2010 19:35, schrieb austinro(a)msu.edu: >>>>> >>>>> I have a Jetway 7F4K1G5S-LF board I'm trying to get working. >>>> >>>> Just to make things clear - that's a Via C7 board, yes? >>> >>> Yes. >>> >>>>> Any ideas? >>>> >>>> We moved the C7 boards over to CAR (cache as RAM), but couldn't test all >>>> of them (due to availability etc). Disabling cache before RAM is >>>> available (and all data structures, esp. the stack are moved to RAM) >>>> makes the system hang. >>>> >>>> From looking at the board's romstage.c, it seems that early_mtrr_init is >>>> ran before RAM init, but after CAR enable. >>>> >>>> Do you get further after disabling early_mtrr_init (which disables >>>> caching to activate the new MTRR config) completely? >>> >>> Commenting out the call to early_mtrr_init() lets coreboot run to >>> completion. >>> >>> That's odd. I assumed the call to "write_cr0(cr0)" in cache.h was >>> responsible somehow, since that was where it stopped when "early_mtrr_init" >>> called "disable_cache", but I left the print statements in disable_cache, >>> and they were all printed repeatedly this time, so "write_cr0" >>> only causes a >>> problem when called early (during "early_mtrr_init")? >>> >>> ... >>> >>> Tried it again and with memtest as the payload and it doesn't see any >>> memory. Memtest pops up on the screen : >>> L1 cache: 64K >>> L2 cache: 128K >>> L3 cache: none >>> Memory : 0K >>> (That last one is a zero K). >>> >>> Hmmm. >> >> Can you send me a boot log, with output level set to DEBUG or SPEW level? >> >> Thanks, >> Corey >> > > Okay, I set it to debug, this is what I got: PCI: 00:0a.0: enabled 1 PCI: 00:0f.0: enabled 1 PCI: 00:0f.1: enabled 1 PCI: 00:10.0: enabled 1 PCI: 00:10.1: enabled 1 PCI: 00:10.2: enabled 1 PCI: 00:10.3: enabled 1 PCI: 00:10.4: enabled 1 PCI: 00:11.0: enabled 1 PNP: 002e.0: enabled 0 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 1 PNP: 002e.b: enabled 1 PCI: 00:11.5: enabled 1 PCI: 00:12.0: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 Compare with tree... Root Device: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.1: enabled 1 PCI: 00:00.2: enabled 1 PCI: 00:00.3: enabled 1 PCI: 00:00.4: enabled 1 PCI: 00:00.7: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:0a.0: enabled 1 PCI: 00:0f.0: enabled 1 PCI: 00:0f.1: enabled 1 PCI: 00:10.0: enabled 1 PCI: 00:10.1: enabled 1 PCI: 00:10.2: enabled 1 PCI: 00:10.3: enabled 1 PCI: 00:10.4: enabled 1 PCI: 00:11.0: enabled 1 PNP: 002e.0: enabled 0 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 1 PNP: 002e.b: enabled 1 PCI: 00:11.5: enabled 1 PCI: 00:12.0: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 scan_static_bus for Root Device In cn700 enable_dev for device PCI_DOMAIN: 0000. Finding PCI configuration type. PCI: Using configuration type 1 POST: 0x5f PCI_DOMAIN: 0000 enabled In cn700 enable_dev for device APIC_CLUSTER: 0. APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 POST: 0x24 In cn700 enable_dev for device PCI: 00:00.0. PCI: 00:00.0 [1106/0314] ops PCI: 00:00.0 [1106/0314] enabled In cn700 enable_dev for device PCI: 00:00.1. PCI: 00:00.1 [1106/1314] enabled In cn700 enable_dev for device PCI: 00:00.2. PCI: 00:00.2 [1106/2314] enabled In cn700 enable_dev for device PCI: 00:00.3. PCI: 00:00.3 [1106/3208] ops PCI: 00:00.3 [1106/3208] enabled In cn700 enable_dev for device PCI: 00:00.4. PCI: 00:00.4 [1106/4314] enabled In cn700 enable_dev for device PCI: 00:00.7. PCI: 00:00.7 [1106/7314] enabled In cn700 enable_dev for device PCI: 00:01.0. PCI: 00:01.0 [1106/b198] bus ops PCI: 00:01.0 [1106/b198] enabled malloc Enter, size 68, free_mem_ptr 00020000 malloc 00020000 PCI: 00:09.0 [10ec/8167] enabled PCI: Static device PCI: 00:0a.0 not found, disabling it. malloc Enter, size 68, free_mem_ptr 00020044 malloc 00020044 PCI: 00:0b.0 [10ec/8167] enabled PCI: 00:0f.0 [1106/3149] ops PCI: 00:0f.0 [1106/3149] enabled PCI: 00:0f.1 [1106/0571] ops PCI: 00:0f.1 [1106/0571] enabled PCI: 00:10.0 [1106/3038] ops PCI: 00:10.0 [1106/3038] enabled PCI: 00:10.1 [1106/3038] ops PCI: 00:10.1 [1106/3038] enabled PCI: 00:10.2 [1106/3038] ops PCI: 00:10.2 [1106/3038] enabled PCI: 00:10.3 [1106/3038] ops PCI: 00:10.3 [1106/3038] enabled PCI: 00:10.4 [1106/3104] ops PCI: 00:10.4 [1106/3104] enabled malloc Enter, size 68, free_mem_ptr 00020088 malloc 00020088 PCI: 00:10.5 [1106/d104] enabled PCI: 00:11.0 [1106/3227] bus ops PCI: 00:11.0 [1106/3227] enabled PCI: 00:11.5 [1106/3059] enabled PCI: 00:12.0 [1106/3065] ops PCI: 00:12.0 [1106/3065] enabled POST: 0x25 do_pci_scan_bridge for PCI: 00:01.0 malloc Enter, size 24, free_mem_ptr 000200cc malloc 000200cc PCI: pci_scan_bus for bus 01 POST: 0x24 malloc Enter, size 68, free_mem_ptr 000200e4 malloc 000200e4 PCI: 01:00.0 [1106/3344] ops PCI: 01:00.0 [1106/3344] enabled POST: 0x25 PCI: pci_scan_bus returning with max=001 POST: 0x55 do_pci_scan_bridge returns max 1 scan_static_bus for PCI: 00:11.0 malloc Enter, size 2560, free_mem_ptr 00020128 malloc 00020128 malloc Enter, size 68, free_mem_ptr 00020b28 malloc 00020b28 malloc Enter, size 68, free_mem_ptr 00020b6c malloc 00020b6c malloc Enter, size 68, free_mem_ptr 00020bb0 malloc 00020bb0 PNP: 002e.0 disabled PNP: 002e.1 enabled PNP: 002e.2 enabled PNP: 002e.3 enabled PNP: 002e.b enabled PNP: 002e.4 enabled PNP: 002e.6 enabled PNP: 002e.a enabled scan_static_bus for PCI: 00:11.0 done PCI: pci_scan_bus returning with max=001 POST: 0x55 scan_static_bus for Root Device done done POST: 0x66 Setting up VGA for PCI: 01:00.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:01.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 PCI_DOMAIN: 0000 read_resources bus 0 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 done PCI: 00:11.0 read_resources bus 0 link: 0 PNP: 002e.b missing read_resources PCI: 00:11.0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done APIC_CLUSTER: 0 read_resources bus 0 link: 0 APIC: 00 missing read_resources APIC_CLUSTER: 0 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 PCI_DOMAIN: 0000 PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 400400 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40 PCI: 00:00.0 PCI: 00:00.1 PCI: 00:00.2 PCI: 00:00.3 PCI: 00:00.4 PCI: 00:00.7 PCI: 00:01.0 child on link 0 PCI: 01:00.0 PCI: 01:00.0 PCI: 01:00.0 resource base 0 size 4000000 align 26 gran 26 limit ffffffff f0 PCI: 01:00.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffff f4 PCI: 01:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff fla0 PCI: 00:09.0 PCI: 00:09.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 in0 PCI: 00:09.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 204 PCI: 00:09.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flag0 PCI: 00:0a.0 PCI: 00:0b.0 PCI: 00:0b.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 in0 PCI: 00:0b.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 204 PCI: 00:0b.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flag0 PCI: 00:0f.0 PCI: 00:0f.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 inde0 PCI: 00:0f.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 inde4 PCI: 00:0f.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 inde8 PCI: 00:0f.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 indec PCI: 00:0f.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 ind0 PCI: 00:0f.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 in4 PCI: 00:0f.1 PCI: 00:0f.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 ind0 PCI: 00:10.0 PCI: 00:10.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 ind0 PCI: 00:10.1 PCI: 00:10.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 ind0 PCI: 00:10.2 PCI: 00:10.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 ind0 PCI: 00:10.3 PCI: 00:10.3 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 ind0 PCI: 00:10.4 PCI: 00:10.4 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 PCI: 00:10.5 PCI: 00:10.5 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 PCI: 00:11.0 child on link 0 PNP: 002e.0 PCI: 00:11.0 resource base 500 size 80 align 0 gran 0 limit ffff flags e00008 PCI: 00:11.0 resource base 4d0 size 2 align 0 gran 0 limit ffff flags e000013 PCI: 00:11.0 resource base 400 size 10 align 0 gran 0 limit ffff flags e00000 PCI: 00:11.0 resource base fec00000 size 100 align 8 gran 8 limit ffffffff f4 PCI: 00:11.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c00001 PNP: 002e.0 PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c0000100 PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 in0 PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 in4 PNP: 002e.1 PNP: 002e.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags c0000100 PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 in0 PNP: 002e.1 resource base 3 size 0 align 0 gran 0 limit 0 flags c0000800 in4 PNP: 002e.2 PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 in0 PNP: 002e.3 PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 in0 PNP: 002e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 002e.b PNP: 002e.b resource base ec00 size 0 align 0 gran 0 limit 0 flags c00001000 PNP: 002e.4 PNP: 002e.4 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index0 PNP: 002e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.6 PNP: 002e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.a PCI: 00:11.5 PCI: 00:11.5 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 in0 PCI: 00:12.0 PCI: 00:12.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 in0 PCI: 00:12.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 204 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: f PCI: 00:09.0 10 * [0x0 - 0xff] io PCI: 00:0b.0 10 * [0x400 - 0x4ff] io PCI: 00:0f.0 24 * [0x800 - 0x8ff] io PCI: 00:11.5 10 * [0xc00 - 0xcff] io PCI: 00:12.0 10 * [0x1000 - 0x10ff] io PCI: 00:10.0 20 * [0x1400 - 0x141f] io PCI: 00:10.1 20 * [0x1420 - 0x143f] io PCI: 00:10.2 20 * [0x1440 - 0x145f] io PCI: 00:10.3 20 * [0x1460 - 0x147f] io PCI: 00:0f.0 20 * [0x1480 - 0x148f] io PCI: 00:0f.1 20 * [0x1490 - 0x149f] io PCI: 00:0f.0 10 * [0x14a0 - 0x14a7] io PCI: 00:0f.0 18 * [0x14a8 - 0x14af] io PCI: 00:0f.0 14 * [0x14b0 - 0x14b3] io PCI: 00:0f.0 1c * [0x14b4 - 0x14b7] io PCI_DOMAIN: 0000 compute_resources_io: base: 14b8 size: 14b8 align: 8 gran: 0 le PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit:f PCI: 00:09.0 30 * [0x0 - 0x1ffff] mem PCI: 00:0b.0 30 * [0x20000 - 0x3ffff] mem PCI: 00:09.0 14 * [0x40000 - 0x400ff] mem PCI: 00:0b.0 14 * [0x40100 - 0x401ff] mem PCI: 00:10.4 10 * [0x40200 - 0x402ff] mem PCI: 00:10.5 10 * [0x40300 - 0x403ff] mem PCI: 00:12.0 14 * [0x40400 - 0x404ff] mem PCI_DOMAIN: 0000 compute_resources_mem: base: 40500 size: 40500 align: 17 gran:e avoid_fixed_resources: PCI_DOMAIN: 0000 avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI_DOMAIN: 0000 constrain_resources: PCI: 00:00.0 constrain_resources: PCI: 00:00.1 constrain_resources: PCI: 00:00.2 constrain_resources: PCI: 00:00.3 constrain_resources: PCI: 00:00.4 constrain_resources: PCI: 00:00.7 constrain_resources: PCI: 00:01.0 constrain_resources: PCI: 01:00.0 constrain_resources: PCI: 00:09.0 constrain_resources: PCI: 00:0b.0 constrain_resources: PCI: 00:0f.0 constrain_resources: PCI: 00:0f.1 constrain_resources: PCI: 00:10.0 constrain_resources: PCI: 00:10.1 constrain_resources: PCI: 00:10.2 constrain_resources: PCI: 00:10.3 constrain_resources: PCI: 00:10.4 constrain_resources: PCI: 00:10.5 constrain_resources: PCI: 00:11.0 constrain_resources: PNP: 002e.1 skipping PNP: 002e.1@74 fixed resource, size=0! constrain_resources: PNP: 002e.2 constrain_resources: PNP: 002e.3 constrain_resources: PNP: 002e.b skipping PNP: 002e.b@60 fixed resource, size=0! constrain_resources: PNP: 002e.4 constrain_resources: PNP: 002e.6 constrain_resources: PNP: 002e.a constrain_resources: PCI: 00:11.5 constrain_resources: PCI: 00:12.0 avoid_fixed_resources2: PCI_DOMAIN: 0000@10000000 limit 0000ffff lim->base 00001000 lim->limit 0000ffff avoid_fixed_resources2: PCI_DOMAIN: 0000@10000100 limit ffffffff lim->base 00000000 lim->limit febfffff Setting resources... PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:14b8 align:8 gran:0 limif Assigned: PCI: 00:09.0 10 * [0x1000 - 0x10ff] io Assigned: PCI: 00:0b.0 10 * [0x1400 - 0x14ff] io Assigned: PCI: 00:0f.0 24 * [0x1800 - 0x18ff] io Assigned: PCI: 00:11.5 10 * [0x1c00 - 0x1cff] io Assigned: PCI: 00:12.0 10 * [0x2000 - 0x20ff] io Assigned: PCI: 00:10.0 20 * [0x2400 - 0x241f] io Assigned: PCI: 00:10.1 20 * [0x2420 - 0x243f] io Assigned: PCI: 00:10.2 20 * [0x2440 - 0x245f] io Assigned: PCI: 00:10.3 20 * [0x2460 - 0x247f] io Assigned: PCI: 00:0f.0 20 * [0x2480 - 0x248f] io Assigned: PCI: 00:0f.1 20 * [0x2490 - 0x249f] io Assigned: PCI: 00:0f.0 10 * [0x24a0 - 0x24a7] io Assigned: PCI: 00:0f.0 18 * [0x24a8 - 0x24af] io Assigned: PCI: 00:0f.0 14 * [0x24b0 - 0x24b3] io Assigned: PCI: 00:0f.0 1c * [0x24b4 - 0x24b7] io PCI_DOMAIN: 0000 allocate_resources_io: next_base: 24b8 size: 14b8 align: 8 grae PCI_DOMAIN: 0000 allocate_resources_mem: base:feba0000 size:40500 align:17 granf Assigned: PCI: 00:09.0 30 * [0xfeba0000 - 0xfebbffff] mem Assigned: PCI: 00:0b.0 30 * [0xfebc0000 - 0xfebdffff] mem Assigned: PCI: 00:09.0 14 * [0xfebe0000 - 0xfebe00ff] mem Assigned: PCI: 00:0b.0 14 * [0xfebe0100 - 0xfebe01ff] mem Assigned: PCI: 00:10.4 10 * [0xfebe0200 - 0xfebe02ff] mem Assigned: PCI: 00:10.5 10 * [0xfebe0300 - 0xfebe03ff] mem Assigned: PCI: 00:12.0 14 * [0xfebe0400 - 0xfebe04ff] mem PCI_DOMAIN: 0000 allocate_resources_mem: next_base: febe0500 size: 40500 align:e Root Device assign_resources, bus 0 link: 0 Entering cn700 pci_domain_set_resources. Entering find_pci_tolm Leaving find_pci_tolm tomk is 0x100000 tom: 40000000, high_tables_base: 3dff0000, high_tables_size: 10000 PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:09.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io PCI: 00:09.0 14 <- [0x00febe0000 - 0x00febe00ff] size 0x00000100 gran 0x08 mem PCI: 00:09.0 30 <- [0x00feba0000 - 0x00febbffff] size 0x00020000 gran 0x11 romem PCI: 00:0b.0 10 <- [0x0000001400 - 0x00000014ff] size 0x00000100 gran 0x08 io PCI: 00:0b.0 14 <- [0x00febe0100 - 0x00febe01ff] size 0x00000100 gran 0x08 mem PCI: 00:0b.0 30 <- [0x00febc0000 - 0x00febdffff] size 0x00020000 gran 0x11 romem PCI: 00:0f.0 10 <- [0x00000024a0 - 0x00000024a7] size 0x00000008 gran 0x03 io PCI: 00:0f.0 14 <- [0x00000024b0 - 0x00000024b3] size 0x00000004 gran 0x02 io PCI: 00:0f.0 18 <- [0x00000024a8 - 0x00000024af] size 0x00000008 gran 0x03 io PCI: 00:0f.0 1c <- [0x00000024b4 - 0x00000024b7] size 0x00000004 gran 0x02 io PCI: 00:0f.0 20 <- [0x0000002480 - 0x000000248f] size 0x00000010 gran 0x04 io PCI: 00:0f.0 24 <- [0x0000001800 - 0x00000018ff] size 0x00000100 gran 0x08 io PCI: 00:0f.1 20 <- [0x0000002490 - 0x000000249f] size 0x00000010 gran 0x04 io PCI: 00:10.0 20 <- [0x0000002400 - 0x000000241f] size 0x00000020 gran 0x05 io PCI: 00:10.1 20 <- [0x0000002420 - 0x000000243f] size 0x00000020 gran 0x05 io PCI: 00:10.2 20 <- [0x0000002440 - 0x000000245f] size 0x00000020 gran 0x05 io PCI: 00:10.3 20 <- [0x0000002460 - 0x000000247f] size 0x00000020 gran 0x05 io PCI: 00:10.4 10 <- [0x00febe0200 - 0x00febe02ff] size 0x00000100 gran 0x08 mem PCI: 00:10.5 10 <- [0x00febe0300 - 0x00febe03ff] size 0x00000100 gran 0x08 mem PCI: 00:11.0 assign_resources, bus 0 link: 0 PNP: 002e.1 60 <- [0x0000000378 - 0x000000037f] size 0x00000008 gran 0x03 io PNP: 002e.1 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq PNP: 002e.1 74 <- [0x0000000003 - 0x0000000002] size 0x00000000 gran 0x00 drq PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq PNP: 002e.3 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io PNP: 002e.3 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq ERROR: PNP: 002e.3 74 drq size: 0x0000000001 not assigned PNP: 002e.b missing set_resources ERROR: PNP: 002e.4 60 io size: 0x0000000008 not assigned ERROR: PNP: 002e.4 70 irq size: 0x0000000001 not assigned ERROR: PNP: 002e.6 70 irq size: 0x0000000001 not assigned PCI: 00:11.0 assign_resources, bus 0 link: 0 PCI: 00:11.5 10 <- [0x0000001c00 - 0x0000001cff] size 0x00000100 gran 0x08 io PCI: 00:12.0 10 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io PCI: 00:12.0 14 <- [0x00febe0400 - 0x00febe04ff] size 0x00000100 gran 0x08 mem PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 PCI_DOMAIN: 0000 PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0 PCI_DOMAIN: 0000 resource base 1000 size 14b8 align 8 gran 0 limit ffff flags0 PCI_DOMAIN: 0000 resource base feba0000 size 40500 align 17 gran 0 limit febf0 PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e000a PCI_DOMAIN: 0000 resource base c0000 size 3df40000 align 0 gran 0 limit 0 flab PCI: 00:00.0 PCI: 00:00.1 PCI: 00:00.2 PCI: 00:00.3 PCI: 00:00.4 PCI: 00:00.7 PCI: 00:01.0 child on link 0 PCI: 01:00.0 PCI: 01:00.0 PCI: 01:00.0 resource base 0 size 4000000 align 26 gran 26 limit ffffffff f0 PCI: 01:00.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffff f4 PCI: 01:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff fla0 PCI: 00:09.0 PCI: 00:09.0 resource base 1000 size 100 align 8 gran 8 limit ffff flags 6000 PCI: 00:09.0 resource base febe0000 size 100 align 8 gran 8 limit febfffff f4 PCI: 00:09.0 resource base feba0000 size 20000 align 17 gran 17 limit febfff0 PCI: 00:0a.0 PCI: 00:0b.0 PCI: 00:0b.0 resource base 1400 size 100 align 8 gran 8 limit ffff flags 6000 PCI: 00:0b.0 resource base febe0100 size 100 align 8 gran 8 limit febfffff f4 PCI: 00:0b.0 resource base febc0000 size 20000 align 17 gran 17 limit febfff0 PCI: 00:0f.0 PCI: 00:0f.0 resource base 24a0 size 8 align 3 gran 3 limit ffff flags 600000 PCI: 00:0f.0 resource base 24b0 size 4 align 2 gran 2 limit ffff flags 600004 PCI: 00:0f.0 resource base 24a8 size 8 align 3 gran 3 limit ffff flags 600008 PCI: 00:0f.0 resource base 24b4 size 4 align 2 gran 2 limit ffff flags 60000c PCI: 00:0f.0 resource base 2480 size 10 align 4 gran 4 limit ffff flags 60000 PCI: 00:0f.0 resource base 1800 size 100 align 8 gran 8 limit ffff flags 6004 PCI: 00:0f.1 PCI: 00:0f.1 resource base 2490 size 10 align 4 gran 4 limit ffff flags 60000 PCI: 00:10.0 PCI: 00:10.0 resource base 2400 size 20 align 5 gran 5 limit ffff flags 60000 PCI: 00:10.1 PCI: 00:10.1 resource base 2420 size 20 align 5 gran 5 limit ffff flags 60000 PCI: 00:10.2 PCI: 00:10.2 resource base 2440 size 20 align 5 gran 5 limit ffff flags 60000 PCI: 00:10.3 PCI: 00:10.3 resource base 2460 size 20 align 5 gran 5 limit ffff flags 60000 PCI: 00:10.4 PCI: 00:10.4 resource base febe0200 size 100 align 8 gran 8 limit febfffff f0 PCI: 00:10.5 PCI: 00:10.5 resource base febe0300 size 100 align 8 gran 8 limit febfffff f0 PCI: 00:11.0 child on link 0 PNP: 002e.0 PCI: 00:11.0 resource base 500 size 80 align 0 gran 0 limit ffff flags e00008 PCI: 00:11.0 resource base 4d0 size 2 align 0 gran 0 limit ffff flags e000013 PCI: 00:11.0 resource base 400 size 10 align 0 gran 0 limit ffff flags e00000 PCI: 00:11.0 resource base fec00000 size 100 align 8 gran 8 limit ffffffff f4 PCI: 00:11.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c00001 PNP: 002e.0 PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c0000100 PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 in0 PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 in4 PNP: 002e.1 PNP: 002e.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags e0000100 PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags e0000400 in0 PNP: 002e.1 resource base 3 size 0 align 0 gran 0 limit 0 flags e0000800 in4 PNP: 002e.2 PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 in0 PNP: 002e.3 PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags e0000100 PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags e0000400 in0 PNP: 002e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 002e.b PNP: 002e.b resource base ec00 size 0 align 0 gran 0 limit 0 flags c00001000 PNP: 002e.4 PNP: 002e.4 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index0 PNP: 002e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.6 PNP: 002e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.a PCI: 00:11.5 PCI: 00:11.5 resource base 1c00 size 100 align 8 gran 8 limit ffff flags 6000 PCI: 00:12.0 PCI: 00:12.0 resource base 2000 size 100 align 8 gran 8 limit ffff flags 6000 PCI: 00:12.0 resource base febe0400 size 100 align 8 gran 8 limit febfffff f4 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 Done allocating resources. POST: 0x88 Enabling resources... PCI: 00:00.0 cmd <- 06 PCI: 00:00.1 subsystem <- 00/00 PCI: 00:00.1 cmd <- 06 PCI: 00:00.2 subsystem <- 00/00 PCI: 00:00.2 cmd <- 06 PCI: 00:00.4 subsystem <- 00/00 PCI: 00:00.4 cmd <- 06 PCI: 00:00.7 subsystem <- 00/00 PCI: 00:00.7 cmd <- 06 PCI: 00:01.0 bridge ctrl <- 000b PCI: 00:01.0 cmd <- 07 PCI: 00:09.0 cmd <- 03 PCI: 00:0b.0 cmd <- 03 PCI: 00:0f.0 cmd <- 01 PCI: 00:0f.1 cmd <- 81 PCI: 00:10.0 cmd <- 01 PCI: 00:10.1 cmd <- 01 PCI: 00:10.2 cmd <- 01 PCI: 00:10.3 cmd <- 01 PCI: 00:10.4 cmd <- 02 PCI: 00:10.5 cmd <- 02 PCI: 00:11.0 cmd <- 07 PCI: 00:11.5 subsystem <- 00/00 PCI: 00:11.5 cmd <- 01 PCI: 00:12.0 cmd <- 83 PCI: 01:00.0 cmd <- 03 done. Initializing devices... APIC_CLUSTER: 0 init Initializing CPU #0 CPU: vendor Centaur device 6d0 CPU: family 06, model 0d, stepping 00 Detected VIA Model D C7 Enabling improved C7 clock and voltage. Voltage: 956mV (min 956mV; max 1004mV) CPU multiplier: 8x (min 8x; max 15x) msr.lo = 8000810 new msr.lo = 810 Current voltage: 956mV Current CPU multiplier: 8x POST: 0x60 Enabling cache Setting fixed MTRRs(0-88) Type: UC Setting fixed MTRRs(0-16) Type: WB Setting fixed MTRRs(24-88) Type: WB DONE fixed MTRRs call enable_fixed_mtrr() Setting variable MTRR 0, base: 0MB, range: 512MB, type WB ADDRESS_MASK_HIGH=0xf Setting variable MTRR 1, base: 512MB, range: 256MB, type WB ADDRESS_MASK_HIGH=0xf Setting variable MTRR 2, base: 768MB, range: 128MB, type WB ADDRESS_MASK_HIGH=0xf Setting variable MTRR 3, base: 896MB, range: 64MB, type WB ADDRESS_MASK_HIGH=0xf Setting variable MTRR 4, base: 960MB, range: 32MB, type WB ADDRESS_MASK_HIGH=0xf Zero-sized MTRR range @0KB DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs POST: 0x6a MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Setting up local apic... apic_id: 0x00 done. POST: 0x9b CPU #0 initialized PCI: 00:00.0 init Enabling AGP. PCI: 00:00.1 init Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram CBFS: follow chain: fff80000 + 38 + 8370 + align -> fff883c0 Check fallback/payload CBFS: follow chain: fff883c0 + 38 + 4265 + align -> fff8c680 Check pci1106,3344.rom CBFS: follow chain: fff8c680 + 38 + 10000 + align -> fff9c6c0 Check CBFS: follow chain: fff9c6c0 + 28 + 538f8 + align -> ffff0000 CBFS: Could not find file pci1106,1314.rom PCI: 00:00.2 init Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram CBFS: follow chain: fff80000 + 38 + 8370 + align -> fff883c0 Check fallback/payload CBFS: follow chain: fff883c0 + 38 + 4265 + align -> fff8c680 Check pci1106,3344.rom CBFS: follow chain: fff8c680 + 38 + 10000 + align -> fff9c6c0 Check CBFS: follow chain: fff9c6c0 + 28 + 538f8 + align -> ffff0000 CBFS: Could not find file pci1106,2314.rom PCI: 00:00.3 init PCI: 00:00.4 init Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram CBFS: follow chain: fff80000 + 38 + 8370 + align -> fff883c0 Check fallback/payload CBFS: follow chain: fff883c0 + 38 + 4265 + align -> fff8c680 Check pci1106 coreboot-4.0-r5659:5673M Fri Jul 30 18:52:48 EDT 2010 starting... In romstage.c:main() After reset status: 0040 Waiting for SMBus to warm upDIMM 0050 OFFSET 0002 After reset status: 0040 Waiting until SMBus ready Waiting until SMBus ready Read: 0008 After reset status: 0040 .Done doing early_mtrr Enabling mainboard devices DIMM 0050 OFFSET 0005 After reset status: 0040 Waiting until SMBus ready Waiting until SMBus ready Read: 0000 After reset status: 0040 DIMM 0050 OFFSET 001f After reset status: 0040 Waiting until SMBus ready Waiting until SMBus ready Read: 0001 After reset status: 0040 DIMM 0050 OFFSET 0011 After reset status: 0040 Waiting until SMBus ready Waiting until SMBus ready Read: 0008 After reset status: 0040 DIMM 0050 OFFSET 0004 After reset status: 0040 Waiting until SMBus ready Waiting until SMBus ready Read: 000a After reset status: 0040 RAM Enable 1: Apply NOP RAM Enable 2: Precharge all RAM Enable 4: Mode register set RAM Enable 2: Precharge all RAM Enable 3: CBR RAM Enable 4: Mode register set RAM Enable 5: Normal operation Leaving romstage.c:main() Loading stage image. Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x4000 (131072 bytes), entry @ 0x4000 Stage: done loading. Jumping to image. POST: 0x80 POST: 0x39 coreboot-4.0-r5659:5673M Fri Jul 30 18:52:48 EDT 2010 booting... POST: 0x40 Calibrating delay loop... end 545df619, start f5df60c 32-bit delta 1104 calibrate_tsc 32-bit result is 1104 clocks_per_usec: 1104 Enumerating buses... Show all devs...Before Device Enumeration. Root Device: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.1: enabled 1 PCI: 00:00.2: enabled 1 PCI: 00:00.3: enabled 1 PCI: 00:00.4: enabled 1 PCI: 00:00.7: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:0a.0: enabled 1 PCI: 00:0f.0: enabled 1 PCI: 00:0f.1: enabled 1 PCI: 00:10.0: enabled 1 PCI: 00:10.1: enabled 1 PCI: 00:10.2: enabled 1 PCI: 00:10.3: enabled 1 PCI: 00:10.4: enabled 1 PCI: 00:11.0: enabled 1 PNP: 002e.0: enabled 0 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 1 PNP: 002e.b: enabled 1 PCI: 00:11.5: enabled 1 PCI: 00:12.0: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 Compare with tree... Root Device: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.1: enabled 1 PCI: 00:00.2: enabled 1 PCI: 00:00.3: enabled 1 PCI: 00:00.4: enabled 1 PCI: 00:00.7: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:0a.0: enabled 1 PCI: 00:0f.0: enabled 1 PCI: 00:0f.1: enabled 1 PCI: 00:10.0: enabled 1 PCI: 00:10.1: enabled 1 PCI: 00:10.2: enabled 1 PCI: 00:10.3: enabled 1 PCI: 00:10.4: enabled 1 PCI: 00:11.0: enabled 1 PNP: 002e.0: enabled 0 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 1 PNP: 002e.b: enabled 1 PCI: 00:11.5: enabled 1 PCI: 00:12.0: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 scan_static_bus for Root Device In cn700 enable_dev for device PCI_DOMAIN: 0000. Finding PCI configuration type. PCI: Using configuration type 1 POST: 0x5f PCI_DOMAIN: 0000 enabled In cn700 enable_dev for device APIC_CLUSTER: 0. APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 POST: 0x24 In cn700 enable_dev for device PCI: 00:00.0. PCI: 00:00.0 [1106/0314] ops PCI: 00:00.0 [1106/0314] enabled In cn700 enable_dev for device PCI: 00:00.1. PCI: 00:00.1 [1106/1314] enabled In cn700 enable_dev for device PCI: 00:00.2. PCI: 00:00.2 [1106/2314] enabled In cn700 enable_dev for device PCI: 00:00.3. PCI: 00:00.3 [1106/3208] ops PCI: 00:00.3 [1106/3208] enabled In cn700 enable_dev for device PCI: 00:00.4. PCI: 00:00.4 [1106/4314] enabled In cn700 enable_dev for device PCI: 00:00.7. PCI: 00:00.7 [1106/7314] enabled In cn700 enable_dev for device PCI: 00:01.0. PCI: 00:01.0 [1106/b198] bus ops PCI: 00:01.0 [1106/b198] enabled malloc Enter, size 68, free_mem_ptr 00020000 malloc 00020000 PCI: 00:09.0 [10ec/8167] enabled PCI: Static device PCI: 00:0a.0 not found, disabling it. malloc Enter, size 68, free_mem_ptr 00020044 malloc 00020044 PCI: 00:0b.0 [10ec/8167] enabled PCI: 00:0f.0 [1106/3149] ops PCI: 00:0f.0 [1106/3149] enabled PCI: 00:0f.1 [1106/0571] ops PCI: 00:0f.1 [1106/0571] enabled PCI: 00:10.0 [1106/3038] ops PCI: 00:10.0 [1106/3038] enabled PCI: 00:10.1 [1106/3038] ops PCI: 00:10.1 [1106/3038] enabled PCI: 00:10.2 [1106/3038] ops PCI: 00:10.2 [1106/3038] enabled PCI: 00:10.3 [1106/3038] ops PCI: 00:10.3 [1106/3038] enabled PCI: 00:10.4 [1106/3104] ops PCI: 00:10.4 [1106/3104] enabled malloc Enter, size 68, free_mem_ptr 00020088 malloc 00020088 PCI: 00:10.5 [1106/d104] enabled PCI: 00:11.0 [1106/3227] bus ops PCI: 00:11.0 [1106/3227] enabled PCI: 00:11.5 [1106/3059] enabled PCI: 00:12.0 [1106/3065] ops PCI: 00:12.0 [1106/3065] enabled POST: 0x25 do_pci_scan_bridge for PCI: 00:01.0 malloc Enter, size 24, free_mem_ptr 000200cc malloc 000200cc PCI: pci_scan_bus for bus 01 POST: 0x24 malloc Enter, size 68, free_mem_ptr 000200e4 malloc 000200e4 PCI: 01:00.0 [1106/3344] ops PCI: 01:00.0 [1106/3344] enabled POST: 0x25 PCI: pci_scan_bus returning with max=001 POST: 0x55 do_pci_scan_bridge returns max 1 scan_static_bus for PCI: 00:11.0 malloc Enter, size 2560, free_mem_ptr 00020128 malloc 00020128 malloc Enter, size 68, free_mem_ptr 00020b28 malloc 00020b28 malloc Enter, size 68, free_mem_ptr 00020b6c malloc 00020b6c malloc Enter, size 68, free_mem_ptr 00020bb0 malloc 00020bb0 PNP: 002e.0 disabled PNP: 002e.1 enabled PNP: 002e.2 enabled PNP: 002e.3 enabled PNP: 002e.b enabled PNP: 002e.4 enabled PNP: 002e.6 enabled PNP: 002e.a enabled scan_static_bus for PCI: 00:11.0 done PCI: pci_scan_bus returning with max=001 POST: 0x55 scan_static_bus for Root Device done done POST: 0x66 Setting up VGA for PCI: 01:00.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:01.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 PCI_DOMAIN: 0000 read_resources bus 0 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 done PCI: 00:11.0 read_resources bus 0 link: 0 PNP: 002e.b missing read_resources PCI: 00:11.0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done APIC_CLUSTER: 0 read_resources bus 0 link: 0 APIC: 00 missing read_resources APIC_CLUSTER: 0 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 PCI_DOMAIN: 0000 PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 400400 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40 PCI: 00:00.0 PCI: 00:00.1 PCI: 00:00.2 PCI: 00:00.3 PCI: 00:00.4 PCI: 00:00.7 PCI: 00:01.0 child on link 0 PCI: 01:00.0 PCI: 01:00.0 PCI: 01:00.0 resource base 0 size 4000000 align 26 gran 26 limit ffffffff f0 PCI: 01:00.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffff f4 PCI: 01:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff fla0 PCI: 00:09.0 PCI: 00:09.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 in0 PCI: 00:09.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 204 PCI: 00:09.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flag0 PCI: 00:0a.0 PCI: 00:0b.0 PCI: 00:0b.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 in0 PCI: 00:0b.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 204 PCI: 00:0b.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flag0 PCI: 00:0f.0 PCI: 00:0f.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 inde0 PCI: 00:0f.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 inde4 PCI: 00:0f.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 inde8 PCI: 00:0f.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 indec PCI: 00:0f.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 ind0 PCI: 00:0f.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 in4 PCI: 00:0f.1 PCI: 00:0f.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 ind0 PCI: 00:10.0 PCI: 00:10.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 ind0 PCI: 00:10.1 PCI: 00:10.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 ind0 PCI: 00:10.2 PCI: 00:10.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 ind0 PCI: 00:10.3 PCI: 00:10.3 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 ind0 PCI: 00:10.4 PCI: 00:10.4 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 PCI: 00:10.5 PCI: 00:10.5 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 PCI: 00:11.0 child on link 0 PNP: 002e.0 PCI: 00:11.0 resource base 500 size 80 align 0 gran 0 limit ffff flags e00008 PCI: 00:11.0 resource base 4d0 size 2 align 0 gran 0 limit ffff flags e000013 PCI: 00:11.0 resource base 400 size 10 align 0 gran 0 limit ffff flags e00000 PCI: 00:11.0 resource base fec00000 size 100 align 8 gran 8 limit ffffffff f4 PCI: 00:11.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c00001 PNP: 002e.0 PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c0000100 PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 in0 PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 in4 PNP: 002e.1 PNP: 002e.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags c0000100 PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 in0 PNP: 002e.1 resource base 3 size 0 align 0 gran 0 limit 0 flags c0000800 in4 PNP: 002e.2 PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 in0 PNP: 002e.3 PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 in0 PNP: 002e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 002e.b PNP: 002e.b resource base ec00 size 0 align 0 gran 0 limit 0 flags c00001000 PNP: 002e.4 PNP: 002e.4 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index0 PNP: 002e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.6 PNP: 002e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.a PCI: 00:11.5 PCI: 00:11.5 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 in0 PCI: 00:12.0 PCI: 00:12.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 in0 PCI: 00:12.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 204 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: f PCI: 00:09.0 10 * [0x0 - 0xff] io PCI: 00:0b.0 10 * [0x400 - 0x4ff] io PCI: 00:0f.0 24 * [0x800 - 0x8ff] io PCI: 00:11.5 10 * [0xc00 - 0xcff] io PCI: 00:12.0 10 * [0x1000 - 0x10ff] io PCI: 00:10.0 20 * [0x1400 - 0x141f] io PCI: 00:10.1 20 * [0x1420 - 0x143f] io PCI: 00:10.2 20 * [0x1440 - 0x145f] io PCI: 00:10.3 20 * [0x1460 - 0x147f] io PCI: 00:0f.0 20 * [0x1480 - 0x148f] io PCI: 00:0f.1 20 * [0x1490 - 0x149f] io PCI: 00:0f.0 10 * [0x14a0 - 0x14a7] io PCI: 00:0f.0 18 * [0x14a8 - 0x14af] io PCI: 00:0f.0 14 * [0x14b0 - 0x14b3] io PCI: 00:0f.0 1c * [0x14b4 - 0x14b7] io PCI_DOMAIN: 0000 compute_resources_io: base: 14b8 size: 14b8 align: 8 gran: 0 le PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit:f PCI: 00:09.0 30 * [0x0 - 0x1ffff] mem PCI: 00:0b.0 30 * [0x20000 - 0x3ffff] mem PCI: 00:09.0 14 * [0x40000 - 0x400ff] mem PCI: 00:0b.0 14 * [0x40100 - 0x401ff] mem PCI: 00:10.4 10 * [0x40200 - 0x402ff] mem PCI: 00:10.5 10 * [0x40300 - 0x403ff] mem PCI: 00:12.0 14 * [0x40400 - 0x404ff] mem PCI_DOMAIN: 0000 compute_resources_mem: base: 40500 size: 40500 align: 17 gran:e avoid_fixed_resources: PCI_DOMAIN: 0000 avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI_DOMAIN: 0000 constrain_resources: PCI: 00:00.0 constrain_resources: PCI: 00:00.1 constrain_resources: PCI: 00:00.2 constrain_resources: PCI: 00:00.3 constrain_resources: PCI: 00:00.4 constrain_resources: PCI: 00:00.7 constrain_resources: PCI: 00:01.0 constrain_resources: PCI: 01:00.0 constrain_resources: PCI: 00:09.0 constrain_resources: PCI: 00:0b.0 constrain_resources: PCI: 00:0f.0 constrain_resources: PCI: 00:0f.1 constrain_resources: PCI: 00:10.0 constrain_resources: PCI: 00:10.1 constrain_resources: PCI: 00:10.2 constrain_resources: PCI: 00:10.3 constrain_resources: PCI: 00:10.4 constrain_resources: PCI: 00:10.5 constrain_resources: PCI: 00:11.0 constrain_resources: PNP: 002e.1 skipping PNP: 002e.1@74 fixed resource, size=0! constrain_resources: PNP: 002e.2 constrain_resources: PNP: 002e.3 constrain_resources: PNP: 002e.b skipping PNP: 002e.b@60 fixed resource, size=0! constrain_resources: PNP: 002e.4 constrain_resources: PNP: 002e.6 constrain_resources: PNP: 002e.a constrain_resources: PCI: 00:11.5 constrain_resources: PCI: 00:12.0 avoid_fixed_resources2: PCI_DOMAIN: 0000@10000000 limit 0000ffff lim->base 00001000 lim->limit 0000ffff avoid_fixed_resources2: PCI_DOMAIN: 0000@10000100 limit ffffffff lim->base 00000000 lim->limit febfffff Setting resources... PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:14b8 align:8 gran:0 limif Assigned: PCI: 00:09.0 10 * [0x1000 - 0x10ff] io Assigned: PCI: 00:0b.0 10 * [0x1400 - 0x14ff] io Assigned: PCI: 00:0f.0 24 * [0x1800 - 0x18ff] io Assigned: PCI: 00:11.5 10 * [0x1c00 - 0x1cff] io Assigned: PCI: 00:12.0 10 * [0x2000 - 0x20ff] io Assigned: PCI: 00:10.0 20 * [0x2400 - 0x241f] io Assigned: PCI: 00:10.1 20 * [0x2420 - 0x243f] io Assigned: PCI: 00:10.2 20 * [0x2440 - 0x245f] io Assigned: PCI: 00:10.3 20 * [0x2460 - 0x247f] io Assigned: PCI: 00:0f.0 20 * [0x2480 - 0x248f] io Assigned: PCI: 00:0f.1 20 * [0x2490 - 0x249f] io Assigned: PCI: 00:0f.0 10 * [0x24a0 - 0x24a7] io Assigned: PCI: 00:0f.0 18 * [0x24a8 - 0x24af] io Assigned: PCI: 00:0f.0 14 * [0x24b0 - 0x24b3] io Assigned: PCI: 00:0f.0 1c * [0x24b4 - 0x24b7] io PCI_DOMAIN: 0000 allocate_resources_io: next_base: 24b8 size: 14b8 align: 8 grae PCI_DOMAIN: 0000 allocate_resources_mem: base:feba0000 size:40500 align:17 granf Assigned: PCI: 00:09.0 30 * [0xfeba0000 - 0xfebbffff] mem Assigned: PCI: 00:0b.0 30 * [0xfebc0000 - 0xfebdffff] mem Assigned: PCI: 00:09.0 14 * [0xfebe0000 - 0xfebe00ff] mem Assigned: PCI: 00:0b.0 14 * [0xfebe0100 - 0xfebe01ff] mem Assigned: PCI: 00:10.4 10 * [0xfebe0200 - 0xfebe02ff] mem Assigned: PCI: 00:10.5 10 * [0xfebe0300 - 0xfebe03ff] mem Assigned: PCI: 00:12.0 14 * [0xfebe0400 - 0xfebe04ff] mem PCI_DOMAIN: 0000 allocate_resources_mem: next_base: febe0500 size: 40500 align:e Root Device assign_resources, bus 0 link: 0 Entering cn700 pci_domain_set_resources. Entering find_pci_tolm Leaving find_pci_tolm tomk is 0x100000 tom: 40000000, high_tables_base: 3dff0000, high_tables_size: 10000 PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:09.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io PCI: 00:09.0 14 <- [0x00febe0000 - 0x00febe00ff] size 0x00000100 gran 0x08 mem PCI: 00:09.0 30 <- [0x00feba0000 - 0x00febbffff] size 0x00020000 gran 0x11 romem PCI: 00:0b.0 10 <- [0x0000001400 - 0x00000014ff] size 0x00000100 gran 0x08 io PCI: 00:0b.0 14 <- [0x00febe0100 - 0x00febe01ff] size 0x00000100 gran 0x08 mem PCI: 00:0b.0 30 <- [0x00febc0000 - 0x00febdffff] size 0x00020000 gran 0x11 romem PCI: 00:0f.0 10 <- [0x00000024a0 - 0x00000024a7] size 0x00000008 gran 0x03 io PCI: 00:0f.0 14 <- [0x00000024b0 - 0x00000024b3] size 0x00000004 gran 0x02 io PCI: 00:0f.0 18 <- [0x00000024a8 - 0x00000024af] size 0x00000008 gran 0x03 io PCI: 00:0f.0 1c <- [0x00000024b4 - 0x00000024b7] size 0x00000004 gran 0x02 io PCI: 00:0f.0 20 <- [0x0000002480 - 0x000000248f] size 0x00000010 gran 0x04 io PCI: 00:0f.0 24 <- [0x0000001800 - 0x00000018ff] size 0x00000100 gran 0x08 io PCI: 00:0f.1 20 <- [0x0000002490 - 0x000000249f] size 0x00000010 gran 0x04 io PCI: 00:10.0 20 <- [0x0000002400 - 0x000000241f] size 0x00000020 gran 0x05 io PCI: 00:10.1 20 <- [0x0000002420 - 0x000000243f] size 0x00000020 gran 0x05 io PCI: 00:10.2 20 <- [0x0000002440 - 0x000000245f] size 0x00000020 gran 0x05 io PCI: 00:10.3 20 <- [0x0000002460 - 0x000000247f] size 0x00000020 gran 0x05 io PCI: 00:10.4 10 <- [0x00febe0200 - 0x00febe02ff] size 0x00000100 gran 0x08 mem PCI: 00:10.5 10 <- [0x00febe0300 - 0x00febe03ff] size 0x00000100 gran 0x08 mem PCI: 00:11.0 assign_resources, bus 0 link: 0 PNP: 002e.1 60 <- [0x0000000378 - 0x000000037f] size 0x00000008 gran 0x03 io PNP: 002e.1 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq PNP: 002e.1 74 <- [0x0000000003 - 0x0000000002] size 0x00000000 gran 0x00 drq PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq PNP: 002e.3 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io PNP: 002e.3 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq ERROR: PNP: 002e.3 74 drq size: 0x0000000001 not assigned PNP: 002e.b missing set_resources ERROR: PNP: 002e.4 60 io size: 0x0000000008 not assigned ERROR: PNP: 002e.4 70 irq size: 0x0000000001 not assigned ERROR: PNP: 002e.6 70 irq size: 0x0000000001 not assigned PCI: 00:11.0 assign_resources, bus 0 link: 0 PCI: 00:11.5 10 <- [0x0000001c00 - 0x0000001cff] size 0x00000100 gran 0x08 io PCI: 00:12.0 10 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io PCI: 00:12.0 14 <- [0x00febe0400 - 0x00febe04ff] size 0x00000100 gran 0x08 mem PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 PCI_DOMAIN: 0000 PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0 PCI_DOMAIN: 0000 resource base 1000 size 14b8 align 8 gran 0 limit ffff flags0 PCI_DOMAIN: 0000 resource base feba0000 size 40500 align 17 gran 0 limit febf0 PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e000a PCI_DOMAIN: 0000 resource base c0000 size 3df40000 align 0 gran 0 limit 0 flab PCI: 00:00.0 PCI: 00:00.1 PCI: 00:00.2 PCI: 00:00.3 PCI: 00:00.4 PCI: 00:00.7 PCI: 00:01.0 child on link 0 PCI: 01:00.0 PCI: 01:00.0 PCI: 01:00.0 resource base 0 size 4000000 align 26 gran 26 limit ffffffff f0 PCI: 01:00.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffff f4 PCI: 01:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff fla0 PCI: 00:09.0 PCI: 00:09.0 resource base 1000 size 100 align 8 gran 8 limit ffff flags 6000 PCI: 00:09.0 resource base febe0000 size 100 align 8 gran 8 limit febfffff f4 PCI: 00:09.0 resource base feba0000 size 20000 align 17 gran 17 limit febfff0 PCI: 00:0a.0 PCI: 00:0b.0 PCI: 00:0b.0 resource base 1400 size 100 align 8 gran 8 limit ffff flags 6000 PCI: 00:0b.0 resource base febe0100 size 100 align 8 gran 8 limit febfffff f4 PCI: 00:0b.0 resource base febc0000 size 20000 align 17 gran 17 limit febfff0 PCI: 00:0f.0 PCI: 00:0f.0 resource base 24a0 size 8 align 3 gran 3 limit ffff flags 600000 PCI: 00:0f.0 resource base 24b0 size 4 align 2 gran 2 limit ffff flags 600004 PCI: 00:0f.0 resource base 24a8 size 8 align 3 gran 3 limit ffff flags 600008 PCI: 00:0f.0 resource base 24b4 size 4 align 2 gran 2 limit ffff flags 60000c PCI: 00:0f.0 resource base 2480 size 10 align 4 gran 4 limit ffff flags 60000 PCI: 00:0f.0 resource base 1800 size 100 align 8 gran 8 limit ffff flags 6004 PCI: 00:0f.1 PCI: 00:0f.1 resource base 2490 size 10 align 4 gran 4 limit ffff flags 60000 PCI: 00:10.0 PCI: 00:10.0 resource base 2400 size 20 align 5 gran 5 limit ffff flags 60000 PCI: 00:10.1 PCI: 00:10.1 resource base 2420 size 20 align 5 gran 5 limit ffff flags 60000 PCI: 00:10.2 PCI: 00:10.2 resource base 2440 size 20 align 5 gran 5 limit ffff flags 60000 PCI: 00:10.3 PCI: 00:10.3 resource base 2460 size 20 align 5 gran 5 limit ffff flags 60000 PCI: 00:10.4 PCI: 00:10.4 resource base febe0200 size 100 align 8 gran 8 limit febfffff f0 PCI: 00:10.5 PCI: 00:10.5 resource base febe0300 size 100 align 8 gran 8 limit febfffff f0 PCI: 00:11.0 child on link 0 PNP: 002e.0 PCI: 00:11.0 resource base 500 size 80 align 0 gran 0 limit ffff flags e00008 PCI: 00:11.0 resource base 4d0 size 2 align 0 gran 0 limit ffff flags e000013 PCI: 00:11.0 resource base 400 size 10 align 0 gran 0 limit ffff flags e00000 PCI: 00:11.0 resource base fec00000 size 100 align 8 gran 8 limit ffffffff f4 PCI: 00:11.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c00001 PNP: 002e.0 PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c0000100 PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 in0 PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 in4 PNP: 002e.1 PNP: 002e.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags e0000100 PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags e0000400 in0 PNP: 002e.1 resource base 3 size 0 align 0 gran 0 limit 0 flags e0000800 in4 PNP: 002e.2 PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 in0 PNP: 002e.3 PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags e0000100 PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags e0000400 in0 PNP: 002e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 002e.b PNP: 002e.b resource base ec00 size 0 align 0 gran 0 limit 0 flags c00001000 PNP: 002e.4 PNP: 002e.4 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index0 PNP: 002e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.6 PNP: 002e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.a PCI: 00:11.5 PCI: 00:11.5 resource base 1c00 size 100 align 8 gran 8 limit ffff flags 6000 PCI: 00:12.0 PCI: 00:12.0 resource base 2000 size 100 align 8 gran 8 limit ffff flags 6000 PCI: 00:12.0 resource base febe0400 size 100 align 8 gran 8 limit febfffff f4 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 Done allocating resources. POST: 0x88 Enabling resources... PCI: 00:00.0 cmd <- 06 PCI: 00:00.1 subsystem <- 00/00 PCI: 00:00.1 cmd <- 06 PCI: 00:00.2 subsystem <- 00/00 PCI: 00:00.2 cmd <- 06 PCI: 00:00.4 subsystem <- 00/00 PCI: 00:00.4 cmd <- 06 PCI: 00:00.7 subsystem <- 00/00 PCI: 00:00.7 cmd <- 06 PCI: 00:01.0 bridge ctrl <- 000b PCI: 00:01.0 cmd <- 07 PCI: 00:09.0 cmd <- 03 PCI: 00:0b.0 cmd <- 03 PCI: 00:0f.0 cmd <- 01 PCI: 00:0f.1 cmd <- 81 PCI: 00:10.0 cmd <- 01 PCI: 00:10.1 cmd <- 01 PCI: 00:10.2 cmd <- 01 PCI: 00:10.3 cmd <- 01 PCI: 00:10.4 cmd <- 02 PCI: 00:10.5 cmd <- 02 PCI: 00:11.0 cmd <- 07 PCI: 00:11.5 subsystem <- 00/00 PCI: 00:11.5 cmd <- 01 PCI: 00:12.0 cmd <- 83 PCI: 01:00.0 cmd <- 03 done. Initializing devices... APIC_CLUSTER: 0 init Initializing CPU #0 CPU: vendor Centaur device 6d0 CPU: family 06, model 0d, stepping 00 Detected VIA Model D C7 Enabling improved C7 clock and voltage. Voltage: 956mV (min 956mV; max 1004mV) CPU multiplier: 8x (min 8x; max 15x) msr.lo = 8000810 new msr.lo = 810 Current voltage: 956mV Current CPU multiplier: 8x POST: 0x60 Enabling cache Setting fixed MTRRs(0-88) Type: UC Setting fixed MTRRs(0-16) Type: WB Setting fixed MTRRs(24-88) Type: WB DONE fixed MTRRs call enable_fixed_mtrr() Setting variable MTRR 0, base: 0MB, range: 512MB, type WB ADDRESS_MASK_HIGH=0xf Setting variable MTRR 1, base: 512MB, range: 256MB, type WB ADDRESS_MASK_HIGH=0xf Setting variable MTRR 2, base: 768MB, range: 128MB, type WB ADDRESS_MASK_HIGH=0xf Setting variable MTRR 3, base: 896MB, range: 64MB, type WB ADDRESS_MASK_HIGH=0xf Setting variable MTRR 4, base: 960MB, range: 32MB, type WB ADDRESS_MASK_HIGH=0xf Zero-sized MTRR range @0KB DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs POST: 0x6a MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Setting up local apic... apic_id: 0x00 done. POST: 0x9b CPU #0 initialized PCI: 00:00.0 init Enabling AGP. PCI: 00:00.1 init Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram CBFS: follow chain: fff80000 + 38 + 8370 + align -> fff883c0 Check fallback/payload CBFS: follow chain: fff883c0 + 38 + 4265 + align -> fff8c680 Check pci1106,3344.rom CBFS: follow chain: fff8c680 + 38 + 10000 + align -> fff9c6c0 Check CBFS: follow chain: fff9c6c0 + 28 + 538f8 + align -> ffff0000 CBFS: Could not find file pci1106,1314.rom PCI: 00:00.2 init Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram CBFS: follow chain: fff80000 + 38 + 8370 + align -> fff883c0 Check fallback/payload CBFS: follow chain: fff883c0 + 38 + 4265 + align -> fff8c680 Check pci1106,3344.rom CBFS: follow chain: fff8c680 + 38 + 10000 + align -> fff9c6c0 Check CBFS: follow chain: fff9c6c0 + 28 + 538f8 + align -> ffff0000 CBFS: Could not find file pci1106,2314.rom PCI: 00:00.3 init PCI: 00:00.4 init Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram CBFS: follow chain: fff80000 + 38 + 8370 + align -> fff883c0 Check fallback/payload CBFS: follow chain: fff883c0 + 38 + 4265 + align -> fff8c680 Check pci1106,3344.rom CBFS: follow chain: fff8c680 + 38 + 10000 + align -> fff9c6c0 Check CBFS: follow chain: fff9c6c0 + 28 + 538f8 + align -> ffff0000 CBFS: Could not find file pci1106,4314.rom PCI: 00:00.7 init Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram CBFS: follow chain: fff80000 + 38 + 8370 + align -> fff883c0 Check fallback/payload CBFS: follow chain: fff883c0 + 38 + 4265 + align -> fff8c680 Check pci1106,3344.rom CBFS: follow chain: fff8c680 + 38 + 10000 + align -> fff9c6c0 Check CBFS: follow chain: fff9c6c0 + 28 + 538f8 + align -> ffff0000 CBFS: Could not find file pci1106,7314.rom PCI: 00:01.0 init Setting up AGP bridge device PCI: 00:09.0 init Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram CBFS: follow chain: fff80000 + 38 + 8370 + align -> fff883c0 Check fallback/payload CBFS: follow chain: fff883c0 + 38 + 4265 + align -> fff8c680 Check pci1106,3344.rom CBFS: follow chain: fff8c680 + 38 + 10000 + align -> fff9c6c0 Check CBFS: follow chain: fff9c6c0 + 28 + 538f8 + align -> ffff0000 CBFS: Could not find file pci10ec,8167.rom On card, rom address for PCI: 00:09.0 = feba0000 PCI Expansion ROM, signature 0xfefe, INIT size 0x1fc00, data ptr 0xfefe Incorrect Expansion ROM Header Signature fefe PCI: 00:0b.0 init Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram CBFS: follow chain: fff80000 + 38 + 8370 + align -> fff883c0 Check fallback/payload CBFS: follow chain: fff883c0 + 38 + 4265 + align -> fff8c680 Check pci1106,3344.rom CBFS: follow chain: fff8c680 + 38 + 10000 + align -> fff9c6c0 Check CBFS: follow chain: fff9c6c0 + 28 + 538f8 + align -> ffff0000 CBFS: Could not find file pci10ec,8167.rom On card, rom address for PCI: 00:0b.0 = febc0000 PCI Expansion ROM, signature 0xfefe, INIT size 0x1fc00, data ptr 0xfefe Incorrect Expansion ROM Header Signature fefe PCI: 00:0f.0 init Configuring VIA SATA controller PCI: 00:0f.1 init Primary IDE interface enabled Secondary IDE interface enabled Enables in reg 0x40 read back as 0x4f Enables in reg 0x42 read back as 0x9 PCI: 00:10.0 init PCI: 00:10.1 init PCI: 00:10.2 init PCI: 00:10.3 init PCI: 00:10.4 init PCI: 00:10.5 init Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram CBFS: follow chain: fff80000 + 38 + 8370 + align -> fff883c0 Check fallback/payload CBFS: follow chain: fff883c0 + 38 + 4265 + align -> fff8c680 Check pci1106,3344.rom CBFS: follow chain: fff8c680 + 38 + 10000 + align -> fff9c6c0 Check CBFS: follow chain: fff9c6c0 + 28 + 538f8 + align -> ffff0000 CBFS: Could not find file pci1106,d104.rom PCI: 00:11.0 init Entering vt8237r_init. RTC Init IOAPIC: Initializing IOAPIC at 0xfec00000 IOAPIC: Bootstrap Processor Local APIC = 00 IOAPIC: ID = 0x02 IOAPIC: 23 interrupts IOAPIC: Enabling interrupts on FSB IOAPIC: reg 0x00000000 value 0x00000000 0x00000700 IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 Keyboard init... No PS/2 keyboard detected. Leaving vt8237r_init. PCI: 00:11.5 init Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram CBFS: follow chain: fff80000 + 38 + 8370 + align -> fff883c0 Check fallback/payload CBFS: follow chain: fff883c0 + 38 + 4265 + align -> fff8c680 Check pci1106,3344.rom CBFS: follow chain: fff8c680 + 38 + 10000 + align -> fff9c6c0 Check CBFS: follow chain: fff9c6c0 + 28 + 538f8 + align -> ffff0000 CBFS: Could not find file pci1106,3059.rom PCI: 01:00.0 init Initializing VGA... Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram CBFS: follow chain: fff80000 + 38 + 8370 + align -> fff883c0 Check fallback/payload CBFS: follow chain: fff883c0 + 38 + 4265 + align -> fff8c680 Check pci1106,3344.rom In cbfs, rom address for PCI: 01:00.0 = fff8c6b8 PCI Expansion ROM, signature 0xaa55, INIT size 0x10000, data ptr 0x0044 PCI ROM Image, Vendor 1106, Device 3344, PCI ROM Image, Class Code 030000, Code Type 00 copying VGA ROM Image from fff8c6b8 to 0xc0000, 0x10000 bytes Real mode stub @00000600: 606 bytes Calling Option ROM... oprom: INT# 0x15 oprom: eax: 00005f0b ebx: 00010100 ecx: 00000044 edx: 00000110 oprom: ebp: 0001feb0 esp: 00000fc4 edi: 00000044 esi: 0000b32b oprom: ip: d14c cs: c000 flags: 00000006 via_cn700_int15_handler Unknown INT15 function 5f0b! int15 call returned error. oprom: INT# 0x15 oprom: eax: 00005f01 ebx: 00010100 ecx: 00000044 edx: 00000110 oprom: ebp: 0001feb0 esp: 00000faa edi: 00000044 esi: 0000b32b oprom: ip: d07c cs: c000 flags: 00000002 via_cn700_int15_handler oprom: INT# 0x15 oprom: eax: 00005f02 ebx: 00010001 ecx: 00000000 edx: 000003c2 oprom: ebp: 0001feb0 esp: 00000fd8 edi: 00000044 esi: 00000001 oprom: ip: d0af cs: c000 flags: 00000002 via_cn700_int15_handler oprom: INT# 0x15 oprom: eax: 00005f18 ebx: 00010200 ecx: 00000044 edx: 000003c2 oprom: ebp: 0001feb0 esp: 00000fde edi: 00000044 esi: 00000000 oprom: ip: d23f cs: c000 flags: 00000006 via_cn700_int15_handler ... Option ROM returned. PNP: 002e.1 init PNP: 002e.2 init PNP: 002e.3 init PNP: 002e.4 init PNP: 002e.6 init PNP: 002e.a init Devices initialized Show all devs...After init. Root Device: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.1: enabled 1 PCI: 00:00.2: enabled 1 PCI: 00:00.3: enabled 1 PCI: 00:00.4: enabled 1 PCI: 00:00.7: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:0a.0: enabled 0 PCI: 00:0f.0: enabled 1 PCI: 00:0f.1: enabled 1 PCI: 00:10.0: enabled 1 PCI: 00:10.1: enabled 1 PCI: 00:10.2: enabled 1 PCI: 00:10.3: enabled 1 PCI: 00:10.4: enabled 1 PCI: 00:11.0: enabled 1 PNP: 002e.0: enabled 0 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 1 PNP: 002e.b: enabled 1 PCI: 00:11.5: enabled 1 PCI: 00:12.0: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI: 00:09.0: enabled 1 PCI: 00:0b.0: enabled 1 PCI: 00:10.5: enabled 1 PCI: 01:00.0: enabled 1 PNP: 002e.4: enabled 1 PNP: 002e.6: enabled 1 PNP: 002e.a: enabled 1 POST: 0x89 Initializing CBMEM area to 0x3dff0000 (65536 bytes) Adding CBMEM entry as no. 1 Moving GDT to 3dff0200...ok High Tables Base is 3dff0000. POST: 0x9a Copying Interrupt Routing Table to 0x000f0000... done. Adding CBMEM entry as no. 2 Copying Interrupt Routing Table to 0x3dff0400... done. PIRQ table: 192 bytes. POST: 0x9d Multiboot Information structure has been written. POST: 0x9d Adding CBMEM entry as no. 3 Writing high table forward entry at 0x00000500 Wrote coreboot table at: 00000500 - 00000518 checksum addf New low_table_end: 0x00000518 Now going to write high coreboot table at 0x3dff1400 rom_table_end = 0x3dff1400 Adjust low_table_end from 0x00000518 to 0x00001000 Adjust rom_table_end from 0x3dff1400 to 0x3e000000 Adding high table area coreboot memory table: 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000c0000-000000003dfeffff: RAM 3. 000000003dff0000-000000003dffffff: CONFIGURATION TABLES Wrote coreboot table at: 3dff1400 - 3dff15a8 checksum dd80 coreboot table: 424 bytes. POST: 0x9e 0. FREE SPACE 3dff3400 0000cc00 1. GDT 3dff0200 00000200 2. IRQ TABLE 3dff0400 00001000 3. COREBOOT 3dff1400 00002000 Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram CBFS: follow chain: fff80000 + 38 + 8370 + align -> fff883c0 Check fallback/payload Got a payload Loading segment from rom address 0xfff883f8 parameter section (skipped) Loading segment from rom address 0xfff88414 data (compression=0) malloc Enter, size 36, free_mem_ptr 00020bf4 malloc 00020bf4 New segment dstaddr 0x0 memsize 0x24 srcaddr 0xfff884be filesize 0x24 (cleaned up) New segment addr 0x0 size 0x24 offset 0xfff884be filesize 0x24 Loading segment from rom address 0xfff88430 data (compression=1) malloc Enter, size 36, free_mem_ptr 00020c18 malloc 00020c18 New segment dstaddr 0x100000 memsize 0x36d10 srcaddr 0xfff884e2 filesize 0x41b (cleaned up) New segment addr 0x100000 size 0x36d10 offset 0xfff884e2 filesizb Loading segment from rom address 0xfff8844c Entry Point 0x00100000 Payload is overwriting Coreboot tables. coreinfo 0.1 CPU Information qqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqq Vendor: IDT Processor: VIA C7 Processor 1500MHz Family: 6 Model: D Stepping: 0 CPU Speed: 800 Mhz Features: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge cmov pat clflsh acpi mmx fxsr sse sse2 tm pbe F1: System F2: Firmware 06/30/2010 - 23:04:52

2 1

good pci card for COM1?
by ron minnich 30 Jul '10

30 Jul '10

Anybody got a good line on a PCI card that would implement COM1? We have this Intel smackover DX58SO mainboard that has no serial :-) thanks ron

2 1

[PATCH][inteltool] Support for Atom D/N series and Q963/965
by Corey Osgood 30 Jul '10

30 Jul '10

Patch attached. -Corey

4 6

[commit] r5673 - trunk/util/inteltool
by repository service 29 Jul '10

29 Jul '10

Author: cozzie Date: Thu Jul 29 21:25:31 2010 New Revision: 5673 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5673 Log: Add support for the Intel Atom D400/500- and N400-series integrated northbridge. Also add support for the very similar Q963/965 northbridge. Tested: D510: confirmed working, with MCHBAR enable code Q965: writes to bit 0 to enable MCHBAR access are ignored, all other functions work Untested: D410/D525/N400: should be the same northbridge Signed-off-by: Corey Osgood <corey.osgood(a)gmail.com> Acked-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/util/inteltool/inteltool.c trunk/util/inteltool/inteltool.h trunk/util/inteltool/memory.c trunk/util/inteltool/pcie.c Modified: trunk/util/inteltool/inteltool.c ============================================================================== --- trunk/util/inteltool/inteltool.c Thu Jul 29 02:08:21 2010 (r5672) +++ trunk/util/inteltool/inteltool.c Thu Jul 29 21:25:31 2010 (r5673) @@ -41,12 +41,15 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945P, "i945P" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "i945GM" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PM965, "PM965" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q965, "Q963/965" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82975X, "i975X" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q35, "Q35" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82G33, "P35/G33/G31/P31" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q33, "Q33" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58, "X58" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GS45, "GS45ME" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ATOM_DXXX, "Atom D400/500 Series" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ATOM_NXXX, "Atom N400 Series" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_POULSBO, "SCH Poulsbo" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC, "SCH Poulsbo" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10R, "ICH10R" }, Modified: trunk/util/inteltool/inteltool.h ============================================================================== --- trunk/util/inteltool/inteltool.h Thu Jul 29 02:08:21 2010 (r5672) +++ trunk/util/inteltool/inteltool.h Thu Jul 29 21:25:31 2010 (r5673) @@ -62,6 +62,7 @@ #define PCI_DEVICE_ID_INTEL_82945P 0x2770 #define PCI_DEVICE_ID_INTEL_82945GM 0x27a0 #define PCI_DEVICE_ID_INTEL_PM965 0x2a00 +#define PCI_DEVICE_ID_INTEL_Q965 0x2990 #define PCI_DEVICE_ID_INTEL_82975X 0x277c #define PCI_DEVICE_ID_INTEL_82Q35 0x29b0 #define PCI_DEVICE_ID_INTEL_82G33 0x29c0 @@ -69,6 +70,10 @@ #define PCI_DEVICE_ID_INTEL_GS45 0x2a40 #define PCI_DEVICE_ID_INTEL_X58 0x3405 #define PCI_DEVICE_ID_INTEL_SCH_POULSBO 0x8100 +#define PCI_DEVICE_ID_INTEL_ATOM_DXXX 0xa000 + +/* untested, but almost identical to D-series */ +#define PCI_DEVICE_ID_INTEL_ATOM_NXXX 0xa010 #define PCI_DEVICE_ID_INTEL_82443LX 0x7180 /* 82443BX has a different device ID if AGP is disabled (hardware-wise). */ Modified: trunk/util/inteltool/memory.c ============================================================================== --- trunk/util/inteltool/memory.c Thu Jul 29 02:08:21 2010 (r5672) +++ trunk/util/inteltool/memory.c Thu Jul 29 21:25:31 2010 (r5673) @@ -47,6 +47,31 @@ mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe; mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; break; + case PCI_DEVICE_ID_INTEL_Q965: + case PCI_DEVICE_ID_INTEL_ATOM_DXXX: + case PCI_DEVICE_ID_INTEL_ATOM_NXXX: + mchbar_phys = pci_read_long(nb, 0x48); + + /* Test if bit 0 of the MCHBAR reg is 1 to enable memory reads. + * If it isn't, try to set it. This may fail, because there is + * some bit that locks that bit, and isn't in the public + * datasheets. + */ + + if(!(mchbar_phys & 1)) + { + printf("Access to the MCHBAR is currently disabled, "\ + "attempting to enable.\n"); + mchbar_phys |= 0x1; + pci_write_long(nb, 0x48, mchbar_phys); + if(pci_read_long(nb, 0x48) & 1) + printf("Enabled successfully.\n"); + else + printf("Enable FAILED!\n"); + } + mchbar_phys &= 0xfffffffe; + mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; + break; case PCI_DEVICE_ID_INTEL_82443LX: case PCI_DEVICE_ID_INTEL_82443BX: case PCI_DEVICE_ID_INTEL_82810: Modified: trunk/util/inteltool/pcie.c ============================================================================== --- trunk/util/inteltool/pcie.c Thu Jul 29 02:08:21 2010 (r5672) +++ trunk/util/inteltool/pcie.c Thu Jul 29 21:25:31 2010 (r5673) @@ -40,10 +40,13 @@ epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; break; case PCI_DEVICE_ID_INTEL_PM965: + case PCI_DEVICE_ID_INTEL_Q965: case PCI_DEVICE_ID_INTEL_82Q35: case PCI_DEVICE_ID_INTEL_82G33: case PCI_DEVICE_ID_INTEL_82Q33: case PCI_DEVICE_ID_INTEL_GS45: + case PCI_DEVICE_ID_INTEL_ATOM_DXXX: + case PCI_DEVICE_ID_INTEL_ATOM_NXXX: epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32; break; @@ -94,10 +97,13 @@ dmibar_phys = pci_read_long(nb, 0x4c) & 0xfffffffe; break; case PCI_DEVICE_ID_INTEL_PM965: + case PCI_DEVICE_ID_INTEL_Q965: case PCI_DEVICE_ID_INTEL_82Q35: case PCI_DEVICE_ID_INTEL_82G33: case PCI_DEVICE_ID_INTEL_82Q33: case PCI_DEVICE_ID_INTEL_GS45: + case PCI_DEVICE_ID_INTEL_ATOM_DXXX: + case PCI_DEVICE_ID_INTEL_ATOM_NXXX: dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe; dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32; break; @@ -149,10 +155,13 @@ pciexbar_reg = pci_read_long(nb, 0x48); break; case PCI_DEVICE_ID_INTEL_PM965: + case PCI_DEVICE_ID_INTEL_Q965: case PCI_DEVICE_ID_INTEL_82Q35: case PCI_DEVICE_ID_INTEL_82G33: case PCI_DEVICE_ID_INTEL_82Q33: case PCI_DEVICE_ID_INTEL_GS45: + case PCI_DEVICE_ID_INTEL_ATOM_DXXX: + case PCI_DEVICE_ID_INTEL_ATOM_NXXX: pciexbar_reg = pci_read_long(nb, 0x60); pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32; break;

1 0

[PATCH] fix potential smm security hole
by Stefan Reinauer 29 Jul '10

29 Jul '10

This patch resulted from a security review of coreboot's SMM handler. Feedback appreciated. Regards, Stefan

3 2

xcompile patch for libpayload
by baiyin cai 29 Jul '10

29 Jul '10

hi all, since the xcompile file is generated for different compiler, i think it should be included under the PHONY distclean, am i right? Signed-off-by Cai Bai Yin <caibaiyin.pku(a)gmail.com>

4 4

[commit] r5672 - trunk/payloads/libpayload
by repository service 29 Jul '10

29 Jul '10

Author: mjones Date: Thu Jul 29 02:08:21 2010 New Revision: 5672 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5672 Log: Resolved the bug of filo+libpayload building. The bug is if libpayload is installed before filo load "make -C ../libpayload/Makefile DEST=**", it would not install correctly. Also, distclean removes .xcompile now. Signed-off-by: Cai Bai Yin <caibaiyin.pku(a)gmail.com> Acked-by: Peter Stuge <peter(a)stuge.se> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/payloads/libpayload/Makefile Modified: trunk/payloads/libpayload/Makefile ============================================================================== --- trunk/payloads/libpayload/Makefile Wed Jul 28 02:27:09 2010 (r5671) +++ trunk/payloads/libpayload/Makefile Thu Jul 29 02:08:21 2010 (r5672) @@ -163,7 +163,7 @@ distclean: clean $(Q)rm -rf build # should be $(obj) ? - $(Q)rm -f .config .config.old ..config.tmp .kconfig.d .tmpconfig* + $(Q)rm -f .config .config.old .xcompile ..config.tmp .kconfig.d .tmpconfig* # This include must come _before_ the pattern rules below! # Order _does_ matter for pattern rules. @@ -182,5 +182,5 @@ endif -.PHONY: $(PHONY) prepare clean distclean doxygen doxy +.PHONY: $(PHONY) prepare install clean distclean doxygen doxy

1 0

Re: [coreboot] [PATCH] Geode GX2 post code patch
by Nils 28 Jul '10

28 Jul '10

Hi Peter, Peter wrote: >r5671 Thanks for committing the patch. Nils.

1 0

[PATCH] Geode GX2 post code patch
by Nils 28 Jul '10

28 Jul '10

This patch lets Geode GX2 use geode_post_code.h just like LX and cleans up gx2def.h and geode_post_code.h a little. It is abuild tested and boot tested on my Wyse S50. Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl> Acked-by: Nils Jacobs <njacobs8(a)hetnet.nl> (trivial) As this is a trivial patch and i didn`t wanted to put a burden on the already overloaded review team i acked it myself. Now i "just" need somebody with SVN access to commit it. ;) Thanks,Nils.

2 1

[commit] r5671 - in trunk/src: include/cpu/amd mainboard/amd/rumba mainboard/lippert/frontrunner mainboard/olpc/btest mainboard/olpc/rev_a mainboard/wyse/s50 southbridge/amd/cs5535
by repository service 28 Jul '10

28 Jul '10

Author: stuge Date: Wed Jul 28 02:27:09 2010 New Revision: 5671 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5671 Log: Let Geode GX2 use geode_post_code.h just like Geode LX Also clean up gx2def.h and geode_post_code.h a little. abuild tested and boot tested on a Wyse S50. Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl> Acked-by: Nils Jacobs <njacobs8(a)hetnet.nl> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/include/cpu/amd/geode_post_code.h trunk/src/include/cpu/amd/gx2def.h trunk/src/mainboard/amd/rumba/romstage.c trunk/src/mainboard/lippert/frontrunner/romstage.c trunk/src/mainboard/olpc/btest/romstage.c trunk/src/mainboard/olpc/rev_a/romstage.c trunk/src/mainboard/wyse/s50/romstage.c trunk/src/southbridge/amd/cs5535/chipsetinit.c Modified: trunk/src/include/cpu/amd/geode_post_code.h ============================================================================== --- trunk/src/include/cpu/amd/geode_post_code.h Tue Jul 27 02:30:42 2010 (r5670) +++ trunk/src/include/cpu/amd/geode_post_code.h Wed Jul 28 02:27:09 2010 (r5671) @@ -18,77 +18,70 @@ */ /* standard AMD post definitions -- might as well use them. */ -#define POST_Output_Port (0x080) /* port to write post codes to*/ +#define POST_Output_Port (0x080) /* port to write post codes to*/ -#define POST_preSioInit (0x000) -#define POST_clockInit (0x001) -#define POST_CPURegInit (0x002) -#define POST_UNREAL (0x003) -#define POST_CPUMemRegInit (0x004) -#define POST_CPUTest (0x005) -#define POST_memSetup (0x006) -#define POST_memSetUpStack (0x007) -#define POST_memTest (0x008) -#define POST_shadowRom (0x009) -#define POST_memRAMoptimize (0x00A) -#define POST_cacheInit (0x00B) +#define POST_preSioInit (0x000) +#define POST_clockInit (0x001) +#define POST_CPURegInit (0x002) +#define POST_UNREAL (0x003) +#define POST_CPUMemRegInit (0x004) +#define POST_CPUTest (0x005) +#define POST_memSetup (0x006) +#define POST_memSetUpStack (0x007) +#define POST_memTest (0x008) +#define POST_shadowRom (0x009) +#define POST_memRAMoptimize (0x00A) +#define POST_cacheInit (0x00B) #define POST_northBridgeInit (0x00C) -#define POST_chipsetInit (0x00D) -#define POST_sioTest (0x00E) -#define POST_pcATjunk (0x00F) - - -#define POST_intTable (0x010) -#define POST_memInfo (0x011) -#define POST_romCopy (0x012) -#define POST_PLLCheck (0x013) -#define POST_keyboardInit (0x014) -#define POST_cpuCacheOff (0x015) -#define POST_BDAInit (0x016) -#define POST_pciScan (0x017) -#define POST_optionRomInit (0x018) -#define POST_ResetLimits (0x019) -#define POST_summary_screen (0x01A) -#define POST_Boot (0x01B) -#define POST_SystemPreInit (0x01C) +#define POST_chipsetInit (0x00D) +#define POST_sioTest (0x00E) +#define POST_pcATjunk (0x00F) + +#define POST_intTable (0x010) +#define POST_memInfo (0x011) +#define POST_romCopy (0x012) +#define POST_PLLCheck (0x013) +#define POST_keyboardInit (0x014) +#define POST_cpuCacheOff (0x015) +#define POST_BDAInit (0x016) +#define POST_pciScan (0x017) +#define POST_optionRomInit (0x018) +#define POST_ResetLimits (0x019) +#define POST_summary_screen (0x01A) +#define POST_Boot (0x01B) +#define POST_SystemPreInit (0x01C) #define POST_ClearRebootFlag (0x01D) -#define POST_GLIUInit (0x01E) -#define POST_BootFailed (0x01F) +#define POST_GLIUInit (0x01E) +#define POST_BootFailed (0x01F) - -#define POST_CPU_ID (0x020) -#define POST_COUNTERBROKEN (0x021) -#define POST_DIFF_DIMMS (0x022) +#define POST_CPU_ID (0x020) +#define POST_COUNTERBROKEN (0x021) +#define POST_DIFF_DIMMS (0x022) #define POST_WIGGLE_MEM_LINES (0x023) -#define POST_NO_GLIU_DESC (0x024) -#define POST_CPU_LCD_CHECK (0x025) -#define POST_CPU_LCD_PASS (0x026) -#define POST_CPU_LCD_FAIL (0x027) -#define POST_CPU_STEPPING (0x028) +#define POST_NO_GLIU_DESC (0x024) +#define POST_CPU_LCD_CHECK (0x025) +#define POST_CPU_LCD_PASS (0x026) +#define POST_CPU_LCD_FAIL (0x027) +#define POST_CPU_STEPPING (0x028) #define POST_CPU_DM_BIST_FAILURE (0x029) -#define POST_CPU_FLAGS (0x02A) -#define POST_CHIPSET_ID (0x02b) -#define POST_CHIPSET_ID_PASS (0x02c) -#define POST_CHIPSET_ID_FAIL (0x02d) -#define POST_CPU_ID_GOOD (0x02E) -#define POST_CPU_ID_FAIL (0x02F) - - +#define POST_CPU_FLAGS (0x02A) +#define POST_CHIPSET_ID (0x02B) +#define POST_CHIPSET_ID_PASS (0x02C) +#define POST_CHIPSET_ID_FAIL (0x02D) +#define POST_CPU_ID_GOOD (0x02E) +#define POST_CPU_ID_FAIL (0x02F) /* PCI config*/ -#define P80_PCICFG (0x030) - +#define P80_PCICFG (0x030) /* PCI io*/ -#define P80_PCIIO (0x040) - +#define P80_PCIIO (0x040) /* PCI memory*/ -#define P80_PCIMEM (0x050) - +#define P80_PCIMEM (0x050) /* SIO*/ -#define P80_SIO (0x060) +#define P80_SIO (0x060) /* Memory Setp*/ #define P80_MEM_SETUP (0x070) @@ -102,32 +95,30 @@ #define ERROR_NO_DIMMS (0x077) #define ERROR_DIFF_DIMMS (0x078) #define ERROR_BAD_LATENCY (0x079) -#define ERROR_SET_PAGE (0x07a) -#define ERROR_DENSITY_DIMM (0x07b) -#define ERROR_UNSUPPORTED_DIMM (0x07c) -#define ERROR_BANK_SET (0x07d) +#define ERROR_SET_PAGE (0x07A) +#define ERROR_DENSITY_DIMM (0x07B) +#define ERROR_UNSUPPORTED_DIMM (0x07C) +#define ERROR_BANK_SET (0x07D) #define POST_MEM_SETUP_GOOD (0x07E) #define POST_MEM_SETUP_FAIL (0x07F) - -#define POST_UserPreInit (0x080) -#define POST_UserPostInit (0x081) +#define POST_UserPreInit (0x080) +#define POST_UserPostInit (0x081) #define POST_Equipment_check (0x082) -#define POST_InitNVRAMBX (0x083) -#define POST_NoPIRTable (0x084) +#define POST_InitNVRAMBX (0x083) +#define POST_NoPIRTable (0x084) #define POST_ChipsetFingerPrintPass (0x085) #define POST_ChipsetFingerPrintFail (0x086) -#define POST_CPU_IM_TAG_BIST_FAILURE (0x087) -#define POST_CPU_IM_DATA_BIST_FAILURE (0x088) +#define POST_CPU_IM_TAG_BIST_FAILURE (0x087) +#define POST_CPU_IM_DATA_BIST_FAILURE (0x088) #define POST_CPU_FPU_BIST_FAILURE (0x089) -#define POST_CPU_BTB_BIST_FAILURE (0x08a) -#define POST_CPU_EX_BIST_FAILURE (0x08b) -#define POST_Chipset_PI_Test_Fail (0x08c) -#define POST_Chipset_SMBus_SDA_Test_Fail (0x08d) -#define POST_BIT_CLK_Fail (0x08e) +#define POST_CPU_BTB_BIST_FAILURE (0x08A) +#define POST_CPU_EX_BIST_FAILURE (0x08B) +#define POST_Chipset_PI_Test_Fail (0x08C) +#define POST_Chipset_SMBus_SDA_Test_Fail (0x08D) +#define POST_BIT_CLK_Fail (0x08E) - -#define POST_STACK_SETUP (0x090) +#define POST_STACK_SETUP (0x090) #define POST_CPU_PF_BIST_FAILURE (0x091) #define POST_CPU_L2_BIST_FAILURE (0x092) #define POST_CPU_GLCP_BIST_FAILURE (0x093) @@ -137,61 +128,55 @@ #define POST_STACK_SETUP_PASS (0x09E) #define POST_STACK_SETUP_FAIL (0x09F) - -#define POST_PLL_INIT (0x0A0) -#define POST_PLL_MANUAL (0x0A1) -#define POST_PLL_STRAP (0x0A2) -#define POST_PLL_RESET_FAIL (0x0A3) -#define POST_PLL_PCI_FAIL (0x0A4) -#define POST_PLL_MEM_FAIL (0x0A5) +#define POST_PLL_INIT (0x0A0) +#define POST_PLL_MANUAL (0x0A1) +#define POST_PLL_STRAP (0x0A2) +#define POST_PLL_RESET_FAIL (0x0A3) +#define POST_PLL_PCI_FAIL (0x0A4) +#define POST_PLL_MEM_FAIL (0x0A5) #define POST_PLL_CPU_VER_FAIL (0x0A6) - #define POST_MEM_TESTMEM (0x0B0) #define POST_MEM_TESTMEM1 (0x0B1) #define POST_MEM_TESTMEM2 (0x0B2) #define POST_MEM_TESTMEM3 (0x0B3) #define POST_MEM_TESTMEM4 (0x0B4) -#define POST_MEM_TESTMEM_PASS (0x0BE) -#define POST_MEM_TESTMEM_FAIL (0x0BF) - +#define POST_MEM_TESTMEM_PASS (0x0BE) +#define POST_MEM_TESTMEM_FAIL (0x0BF) #define POST_SECUROM_SECBOOT_START (0x0C0) #define POST_SECUROM_BOOTSRCSETUP (0x0C1) #define POST_SECUROM_REMAP_FAIL (0x0C2) -#define POST_SECUROM_BOOTSRCSETUP_FAIL (0x0C3) +#define POST_SECUROM_BOOTSRCSETUP_FAIL (0x0C3) #define POST_SECUROM_DCACHESETUP (0x0C4) -#define POST_SECUROM_DCACHESETUP_FAIL (0x0C5) +#define POST_SECUROM_DCACHESETUP_FAIL (0x0C5) #define POST_SECUROM_ICACHESETUP (0x0C6) -#define POST_SECUROM_DESCRIPTORSETUP (0x0C7) -#define POST_SECUROM_DCACHESETUPBIOS (0x0C8) +#define POST_SECUROM_DESCRIPTORSETUP (0x0C7) +#define POST_SECUROM_DCACHESETUPBIOS (0x0C8) #define POST_SECUROM_PLATFORMSETUP (0x0C9) #define POST_SECUROM_SIGCHECKBIOS (0x0CA) -#define POST_SECUROM_ICACHESETUPBIOS (0x0CB) -#define POST_SECUROM_PASS (0x0CC) -#define POST_SECUROM_FAIL (0x0CD) - -#define POST_RCONFInitError (0x0CE) -#define POST_CacheInitError (0x0CF) +#define POST_SECUROM_ICACHESETUPBIOS (0x0CB) +#define POST_SECUROM_PASS (0x0CC) +#define POST_SECUROM_FAIL (0x0CD) +#define POST_RCONFInitError (0x0CE) +#define POST_CacheInitError (0x0CF) #define POST_ROM_PREUNCOMPRESS (0x0D0) -#define POST_ROM_UNCOMPRESS (0x0D1) -#define POST_ROM_SMM_INIT (0x0D2) -#define POST_ROM_VID_BIOS (0x0D3) -#define POST_ROM_LCDINIT (0x0D4) -#define POST_ROM_SPLASH (0x0D5) -#define POST_ROM_HDDINIT (0x0D6) -#define POST_ROM_SYS_INIT (0x0D7) -#define POST_ROM_DMM_INIT (0x0D8) -#define POST_ROM_TVINIT (0x0D9) +#define POST_ROM_UNCOMPRESS (0x0D1) +#define POST_ROM_SMM_INIT (0x0D2) +#define POST_ROM_VID_BIOS (0x0D3) +#define POST_ROM_LCDINIT (0x0D4) +#define POST_ROM_SPLASH (0x0D5) +#define POST_ROM_HDDINIT (0x0D6) +#define POST_ROM_SYS_INIT (0x0D7) +#define POST_ROM_DMM_INIT (0x0D8) +#define POST_ROM_TVINIT (0x0D9) #define POST_ROM_POSTUNCOMPRESS (0x0DE) - -#define P80_CHIPSET_INIT (0x0E0) -#define POST_PreChipsetInit (0x0E1) +#define P80_CHIPSET_INIT (0x0E0) +#define POST_PreChipsetInit (0x0E1) #define POST_LateChipsetInit (0x0E2) -#define POST_NORTHB_INIT (0x0E8) - +#define POST_NORTHB_INIT (0x0E8) -#define POST_INTR_SEG_JUMP (0x0F0) +#define POST_INTR_SEG_JUMP (0x0F0) Modified: trunk/src/include/cpu/amd/gx2def.h ============================================================================== --- trunk/src/include/cpu/amd/gx2def.h Tue Jul 27 02:30:42 2010 (r5670) +++ trunk/src/include/cpu/amd/gx2def.h Wed Jul 28 02:27:09 2010 (r5671) @@ -503,187 +503,6 @@ #define CHIPSET_DEV_NUM 15 #define IDSEL_BASE 11 // bit 11 = device 1 - -/* standard AMD post definitions -- might as well use them. */ -#define POST_Output_Port (0x080) /* port to write post codes to*/ - -#define POST_preSioInit (0x000) /* geode.asm*/ -#define POST_clockInit (0x001) /* geode.asm*/ -#define POST_CPURegInit (0x002) /* geode.asm*/ -#define POST_UNREAL (0x003) /* geode.asm*/ -#define POST_CPUMemRegInit (0x004) /* geode.asm*/ -#define POST_CPUTest (0x005) /* geode.asm*/ -#define POST_memSetup (0x006) /* geode.asm*/ -#define POST_memSetUpStack (0x007) /* geode.asm*/ -#define POST_memTest (0x008) /* geode.asm*/ -#define POST_shadowRom (0x009) /* geode.asm*/ -#define POST_memRAMoptimize (0x00A) /* geode.asm*/ -#define POST_cacheInit (0x00B) /* geode.asm*/ -#define POST_northBridgeInit (0x00C) /* geode.asm*/ -#define POST_chipsetInit (0x00D) /* geode.asm*/ -#define POST_sioTest (0x00E) /* geode.asm*/ -#define POST_pcATjunk (0x00F) /* geode.asm*/ - - -#define POST_intTable (0x010) /* geode.asm*/ -#define POST_memInfo (0x011) /* geode.asm*/ -#define POST_romCopy (0x012) /* geode.asm*/ -#define POST_PLLCheck (0x013) /* geode.asm*/ -#define POST_keyboardInit (0x014) /* geode.asm*/ -#define POST_cpuCacheOff (0x015) /* geode.asm*/ -#define POST_BDAInit (0x016) /* geode.asm*/ -#define POST_pciScan (0x017) /* geode.asm*/ -#define POST_optionRomInit (0x018) /* geode.asm*/ -#define POST_ResetLimits (0x019) /* geode.asm*/ -#define POST_summary_screen (0x01A) /* geode.asm*/ -#define POST_Boot (0x01B) /* geode.asm*/ -#define POST_SystemPreInit (0x01C) /* geode.asm*/ -#define POST_ClearRebootFlag (0x01D) /* geode.asm*/ -#define POST_GLIUInit (0x01E) /* geode.asm*/ -#define POST_BootFailed (0x01F) /* geode.asm*/ - - -#define POST_CPU_ID (0x020) /* cpucpuid.asm*/ -#define POST_COUNTERBROKEN (0x021) /* pllinit.asm*/ -#define POST_DIFF_DIMMS (0x022) /* pllinit.asm*/ -#define POST_WIGGLE_MEM_LINES (0x023) /* pllinit.asm*/ -#define POST_NO_GLIU_DESC (0x024) /* pllinit.asm*/ -#define POST_CPU_LCD_CHECK (0x025) /* pllinit.asm*/ -#define POST_CPU_LCD_PASS (0x026) /* pllinit.asm*/ -#define POST_CPU_LCD_FAIL (0x027) /* pllinit.asm*/ -#define POST_CPU_STEPPING (0x028) /* cpucpuid.asm*/ -#define POST_CPU_DM_BIST_FAILURE (0x029) /* gx2reg.asm*/ -#define POST_CPU_FLAGS (0x02A) /* cpucpuid.asm*/ -#define POST_CHIPSET_ID (0x02b) /* chipset.asm*/ -#define POST_CHIPSET_ID_PASS (0x02c) /* chipset.asm*/ -#define POST_CHIPSET_ID_FAIL (0x02d) /* chipset.asm*/ -#define POST_CPU_ID_GOOD (0x02E) /* cpucpuid.asm*/ -#define POST_CPU_ID_FAIL (0x02F) /* cpucpuid.asm*/ - - - -/* PCI config*/ -#define P80_PCICFG (0x030) /* pcispace.asm*/ - - -/* PCI io*/ -#define P80_PCIIO (0x040) /* pcispace.asm*/ - - -/* PCI memory*/ -#define P80_PCIMEM (0x050) /* pcispace.asm*/ - - -/* SIO*/ -#define P80_SIO (0x060) /* *sio.asm*/ - -/* Memory Setp*/ -#define P80_MEM_SETUP (0x070) /* docboot meminit*/ -#define POST_MEM_SETUP (0x070) /* memsize.asm*/ -#define ERROR_32BIT_DIMMS (0x071) /* memsize.asm*/ -#define POST_MEM_SETUP2 (0x072) /* memsize.asm*/ -#define POST_MEM_SETUP3 (0x073) /* memsize.asm*/ -#define POST_MEM_SETUP4 (0x074) /* memsize.asm*/ -#define POST_MEM_SETUP5 (0x075) /* memsize.asm*/ -#define POST_MEM_ENABLE (0x076) /* memsize.asm*/ -#define ERROR_NO_DIMMS (0x077) /* memsize.asm*/ -#define ERROR_DIFF_DIMMS (0x078) /* memsize.asm*/ -#define ERROR_BAD_LATENCY (0x079) /* memsize.asm*/ -#define ERROR_SET_PAGE (0x07a) /* memsize.asm*/ -#define ERROR_DENSITY_DIMM (0x07b) /* memsize.asm*/ -#define ERROR_UNSUPPORTED_DIMM (0x07c) /* memsize.asm*/ -#define ERROR_BANK_SET (0x07d) /* memsize.asm*/ -#define POST_MEM_SETUP_GOOD (0x07E) /* memsize.asm*/ -#define POST_MEM_SETUP_FAIL (0x07F) /* memsize.asm*/ - - -#define POST_UserPreInit (0x080) /* geode.asm*/ -#define POST_UserPostInit (0x081) /* geode.asm*/ -#define POST_Equipment_check (0x082) /* geode.asm*/ -#define POST_InitNVRAMBX (0x083) /* geode.asm*/ -#define POST_NoPIRTable (0x084) /* pci.asm*/ -#define POST_ChipsetFingerPrintPass (0x085) /* prechipsetinit*/ -#define POST_ChipsetFingerPrintFail (0x086) /* prechipsetinit*/ -#define POST_CPU_IM_TAG_BIST_FAILURE (0x087) /* gx2reg.asm*/ -#define POST_CPU_IM_DATA_BIST_FAILURE (0x088) /* gx2reg.asm*/ -#define POST_CPU_FPU_BIST_FAILURE (0x089) /* gx2reg.asm*/ -#define POST_CPU_BTB_BIST_FAILURE (0x08a) /* gx2reg.asm*/ -#define POST_CPU_EX_BIST_FAILURE (0x08b) /* gx2reg.asm*/ -#define POST_Chipset_PI_Test_Fail (0x08c) /* prechipsetinit*/ -#define POST_Chipset_SMBus_SDA_Test_Fail (0x08d) /* prechipsetinit*/ -#define POST_BIT_CLK_Fail (0x08e) /* Hawk geode.asm override*/ - - -#define POST_STACK_SETUP (0x090) /* memstack.asm*/ -#define POST_CPU_PF_BIST_FAILURE (0x091) /* gx2reg.asm*/ -#define POST_CPU_L2_BIST_FAILURE (0x092) /* gx2reg.asm*/ -#define POST_CPU_GLCP_BIST_FAILURE (0x093) /* gx2reg.asm*/ -#define POST_CPU_DF_BIST_FAILURE (0x094) /* gx2reg.asm*/ -#define POST_CPU_VG_BIST_FAILURE (0x095) /* gx2reg.asm*/ -#define POST_CPU_VIP_BIST_FAILURE (0x096) /* gx2reg.asm*/ -#define POST_STACK_SETUP_PASS (0x09E) /* memstack.asm*/ -#define POST_STACK_SETUP_FAIL (0x09F) /* memstack.asm*/ - - -#define POST_PLL_INIT (0x0A0) /* pllinit.asm*/ -#define POST_PLL_MANUAL (0x0A1) /* pllinit.asm*/ -#define POST_PLL_STRAP (0x0A2) /* pllinit.asm*/ -#define POST_PLL_RESET_FAIL (0x0A3) /* pllinit.asm*/ -#define POST_PLL_PCI_FAIL (0x0A4) /* pllinit.asm*/ -#define POST_PLL_MEM_FAIL (0x0A5) /* pllinit.asm*/ -#define POST_PLL_CPU_VER_FAIL (0x0A6) /* pllinit.asm*/ - - -#define POST_MEM_TESTMEM (0x0B0) /* memtest.asm*/ -#define POST_MEM_TESTMEM1 (0x0B1) /* memtest.asm*/ -#define POST_MEM_TESTMEM2 (0x0B2) /* memtest.asm*/ -#define POST_MEM_TESTMEM3 (0x0B3) /* memtest.asm*/ -#define POST_MEM_TESTMEM4 (0x0B4) /* memtest.asm*/ -#define POST_MEM_TESTMEM_PASS (0x0BE) /* memtest.asm*/ -#define POST_MEM_TESTMEM_FAIL (0x0BF) /* memtest.asm*/ - - -#define POST_SECUROM_SECBOOT_START (0x0C0) /* secstart.asm*/ -#define POST_SECUROM_BOOTSRCSETUP (0x0C1) /* secstart.asm*/ -#define POST_SECUROM_REMAP_FAIL (0x0C2) /* secstart.asm*/ -#define POST_SECUROM_BOOTSRCSETUP_FAIL (0x0C3) /* secstart.asm*/ -#define POST_SECUROM_DCACHESETUP (0x0C4) /* secstart.asm*/ -#define POST_SECUROM_DCACHESETUP_FAIL (0x0C5) /* secstart.asm*/ -#define POST_SECUROM_ICACHESETUP (0x0C6) /* secstart.asm*/ -#define POST_SECUROM_DESCRIPTORSETUP (0x0C7) /* secstart.asm*/ -#define POST_SECUROM_DCACHESETUPBIOS (0x0C8) /* secstart.asm*/ -#define POST_SECUROM_PLATFORMSETUP (0x0C9) /* secstart.asm*/ -#define POST_SECUROM_SIGCHECKBIOS (0x0CA) /* secstart.asm*/ -#define POST_SECUROM_ICACHESETUPBIOS (0x0CB) /* secstart.asm*/ -#define POST_SECUROM_PASS (0x0CC) /* secstart.asm*/ -#define POST_SECUROM_FAIL (0x0CD) /* secstart.asm*/ - -#define POST_RCONFInitError (0x0CE) /* cache.asm*/ -#define POST_CacheInitError (0x0CF) /* cache.asm*/ - - -#define POST_ROM_PREUNCOMPRESS (0x0D0) /* rominit.asm*/ -#define POST_ROM_UNCOMPRESS (0x0D1) /* rominit.asm*/ -#define POST_ROM_SMM_INIT (0x0D2) /* rominit.asm*/ -#define POST_ROM_VID_BIOS (0x0D3) /* rominit.asm*/ -#define POST_ROM_LCDINIT (0x0D4) /* rominit.asm*/ -#define POST_ROM_SPLASH (0x0D5) /* rominit.asm*/ -#define POST_ROM_HDDINIT (0x0D6) /* rominit.asm*/ -#define POST_ROM_SYS_INIT (0x0D7) /* rominit.asm*/ -#define POST_ROM_DMM_INIT (0x0D8) /* rominit.asm*/ -#define POST_ROM_TVINIT (0x0D9) /* rominit.asm*/ -#define POST_ROM_POSTUNCOMPRESS (0x0DE) - - -#define P80_CHIPSET_INIT (0x0E0) /* chipset.asm*/ -#define POST_PreChipsetInit (0x0E1) /* geode.asm*/ -#define POST_LateChipsetInit (0x0E2) /* geode.asm*/ -#define POST_NORTHB_INIT (0x0E8) /* northb.asm*/ - - -#define POST_INTR_SEG_JUMP (0x0F0) /* vector.asm*/ - - /* */ /* SB LBAR IO + MEMORY MAP*/ /* */ Modified: trunk/src/mainboard/amd/rumba/romstage.c ============================================================================== --- trunk/src/mainboard/amd/rumba/romstage.c Tue Jul 27 02:30:42 2010 (r5670) +++ trunk/src/mainboard/amd/rumba/romstage.c Wed Jul 28 02:27:09 2010 (r5671) @@ -9,6 +9,7 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/gx2def.h> +#include <cpu/amd/geode_post_code.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) Modified: trunk/src/mainboard/lippert/frontrunner/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/frontrunner/romstage.c Tue Jul 27 02:30:42 2010 (r5670) +++ trunk/src/mainboard/lippert/frontrunner/romstage.c Wed Jul 28 02:27:09 2010 (r5671) @@ -9,6 +9,7 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/gx2def.h> +#include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5535/cs5535.h" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) Modified: trunk/src/mainboard/olpc/btest/romstage.c ============================================================================== --- trunk/src/mainboard/olpc/btest/romstage.c Tue Jul 27 02:30:42 2010 (r5670) +++ trunk/src/mainboard/olpc/btest/romstage.c Wed Jul 28 02:27:09 2010 (r5671) @@ -9,6 +9,7 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/gx2def.h> +#include <cpu/amd/geode_post_code.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) Modified: trunk/src/mainboard/olpc/rev_a/romstage.c ============================================================================== --- trunk/src/mainboard/olpc/rev_a/romstage.c Tue Jul 27 02:30:42 2010 (r5670) +++ trunk/src/mainboard/olpc/rev_a/romstage.c Wed Jul 28 02:27:09 2010 (r5671) @@ -9,6 +9,7 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/gx2def.h> +#include <cpu/amd/geode_post_code.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) Modified: trunk/src/mainboard/wyse/s50/romstage.c ============================================================================== --- trunk/src/mainboard/wyse/s50/romstage.c Tue Jul 27 02:30:42 2010 (r5670) +++ trunk/src/mainboard/wyse/s50/romstage.c Wed Jul 28 02:27:09 2010 (r5671) @@ -29,6 +29,7 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/gx2def.h> +#include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536_early_smbus.c" #include "southbridge/amd/cs5536/cs5536_early_setup.c" Modified: trunk/src/southbridge/amd/cs5535/chipsetinit.c ============================================================================== --- trunk/src/southbridge/amd/cs5535/chipsetinit.c Tue Jul 27 02:30:42 2010 (r5670) +++ trunk/src/southbridge/amd/cs5535/chipsetinit.c Wed Jul 28 02:27:09 2010 (r5671) @@ -10,6 +10,7 @@ #include "chip.h" #include "northbridge/amd/gx2/northbridge.h" #include <cpu/amd/gx2def.h> +#include <cpu/amd/geode_post_code.h> #include <cpu/x86/msr.h> #include <cpu/x86/cache.h> #include "southbridge/amd/cs5535/cs5535.h"

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coreboot July 2010