coreboot May 2010

coreboot@coreboot.org

59 participants
300 discussions

[PATCH] Fix typo in r5543 "Change real mode API..."
by Michael Marineau 24 May '10

24 May '10

Greetings, I've just finished bisecting recent coreboot history to see what broke VGA on my EPIA-MII and traced it to commit 5543: Change real mode API to allow passing intXX number or entry point and some register values from C. This theoretically fixes non-vga option roms, but it also allows to use the same assembler code for option roms and vsm. ... After digging through the diff between the good and bad boot logs I noticed that all of the INT# 0x15 ... via_vt8623_int15_handler messages were missing after the "Enable VGA console" message. That call had somehow turned into a no-op. In the diff I observed the following assembly code: - /* Call VGA BIOS int10 function 0x4f14 to enable main console - * Epia-M does not always autosence the main console so forcing - * it on is good. - */ - /* Ask VGA option rom to enable main console */ - movw $0x4f14,%ax - movw $0x8003,%bx - movw $1, %cx - movw $0, %dx - movw $0, %di - int $0x10 Became 3 copies of this function: +static void vga_enable_console(void) +{ + /* Call VGA BIOS int10 function 0x4f14 to enable main console + * Epia-M does not always autosense the main console so forcing + * it on is good. + */ + + /* int#, EAX, EBX, ECX, EDX, ESI, EDI */ + realmode_interrupt(0x10, 0x4f1f, 0x8003, 0x0001, 0x0000, 0x0000, 0x0000); +} The value of AX magically transformed from 0x4f14 to 0x4f1f Doh! The attach patch fixes the three new C functions back to the original value, this fixes VGA for me. Cheers, -- Michael Marineau

3 3

[commit] r5583 - in trunk/src/northbridge/via: cx700 vt8623 vx800
by repository service 24 May '10

24 May '10

Author: stepan Date: Mon May 24 17:51:15 2010 New Revision: 5583 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5583 Log: Fix VGA after switching to realmode_interrupt() Signed-off-by: Michael Marineau <mike(a)marineau.org> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/northbridge/via/cx700/cx700_vga.c trunk/src/northbridge/via/vt8623/vga.c trunk/src/northbridge/via/vx800/vga.c Modified: trunk/src/northbridge/via/cx700/cx700_vga.c ============================================================================== --- trunk/src/northbridge/via/cx700/cx700_vga.c Sun May 23 13:08:37 2010 (r5582) +++ trunk/src/northbridge/via/cx700/cx700_vga.c Mon May 24 17:51:15 2010 (r5583) @@ -152,7 +152,7 @@ */ /* int#, EAX, EBX, ECX, EDX, ESI, EDI */ - realmode_interrupt(0x10, 0x4f1f, 0x8003, 0x0001, 0x0000, 0x0000, 0x0000); + realmode_interrupt(0x10, 0x4f14, 0x8003, 0x0001, 0x0000, 0x0000, 0x0000); } static void vga_init(device_t dev) Modified: trunk/src/northbridge/via/vt8623/vga.c ============================================================================== --- trunk/src/northbridge/via/vt8623/vga.c Sun May 23 13:08:37 2010 (r5582) +++ trunk/src/northbridge/via/vt8623/vga.c Mon May 24 17:51:15 2010 (r5583) @@ -106,7 +106,7 @@ */ /* int#, EAX, EBX, ECX, EDX, ESI, EDI */ - realmode_interrupt(0x10, 0x4f1f, 0x8003, 0x0001, 0x0000, 0x0000, 0x0000); + realmode_interrupt(0x10, 0x4f14, 0x8003, 0x0001, 0x0000, 0x0000, 0x0000); } static void vga_init(device_t dev) Modified: trunk/src/northbridge/via/vx800/vga.c ============================================================================== --- trunk/src/northbridge/via/vx800/vga.c Sun May 23 13:08:37 2010 (r5582) +++ trunk/src/northbridge/via/vx800/vga.c Mon May 24 17:51:15 2010 (r5583) @@ -152,7 +152,7 @@ */ /* int#, EAX, EBX, ECX, EDX, ESI, EDI */ - realmode_interrupt(0x10, 0x4f1f, 0x8003, 0x0001, 0x0000, 0x0000, 0x0000); + realmode_interrupt(0x10, 0x4f14, 0x8003, 0x0001, 0x0000, 0x0000, 0x0000); } extern u8 acpi_sleep_type;

1 0

Trac reminder: list of new ticket(s)
by coreboot tracker 24 May '10

24 May '10

1 0

[commit] r5581 - trunk/src/southbridge/amd/cs5536
by repository service 24 May '10

24 May '10

Author: stuge Date: Sun May 23 06:50:41 2010 New Revision: 5581 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5581 Log: Fix bug from r5476 re CS5536 device search during GeodeLX PCI domain enable cs5536.c:chipsetinit() is called during northbridge pci_domain_enable() which happens before scan_bus() so the device tree does not have PCI vendor/device ids yet. Let's use dev_find_slot() for now. This works only as long as the CS5536 has PCI device id 0xf in all mainboards, and a better solution is needed in case that ever changes! Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Nathan Williams <nathan(a)traverse.com.au> Modified: trunk/src/southbridge/amd/cs5536/cs5536.c Modified: trunk/src/southbridge/amd/cs5536/cs5536.c ============================================================================== --- trunk/src/southbridge/amd/cs5536/cs5536.c Sat May 22 17:07:15 2010 (r5580) +++ trunk/src/southbridge/amd/cs5536/cs5536.c Sun May 23 06:50:41 2010 (r5581) @@ -530,8 +530,7 @@ struct southbridge_amd_cs5536_config *sb; struct msrinit *csi; - dev = dev_find_device(PCI_VENDOR_ID_AMD, - PCI_DEVICE_ID_AMD_CS5536_ISA, 0); + dev = dev_find_slot(0, PCI_DEVFN(0xf, 0)); if (!dev) { printk(BIOS_ERR, "CS5536 not found.\n");

2 1

[PATCH] Add support for Traverse Technologies Geos mainboard
by Nathan Williams 23 May '10

23 May '10

This board is similar to the AMD Norwich mainboard. Signed-off-by: Nathan Williams <nathan(a)traverse.com.au>

3 8

[commit] r5582 - trunk/src/devices/oprom
by repository service 23 May '10

23 May '10

Author: stepan Date: Sun May 23 13:08:37 2010 New Revision: 5582 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5582 Log: consistently use decimal for the register offsets, and fix comment typos. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/devices/oprom/x86_asm.S Modified: trunk/src/devices/oprom/x86_asm.S ============================================================================== --- trunk/src/devices/oprom/x86_asm.S Sun May 23 06:50:41 2010 (r5581) +++ trunk/src/devices/oprom/x86_asm.S Sun May 23 13:08:37 2010 (r5582) @@ -59,12 +59,12 @@ /* Register store for realmode_call and realmode_interrupt */ __registers = RELOCATED(.) - .long 0 /* 0x00 - EAX */ - .long 0 /* 0x04 - EBX */ - .long 0 /* 0x08 - ECX */ - .long 0 /* 0x0c - EDX */ - .long 0 /* 0x10 - EDI */ - .long 0 /* 0x14 - ESI */ + .long 0 /* 0 - EAX */ + .long 0 /* 4 - EBX */ + .long 0 /* 8 - ECX */ + .long 0 /* 12 - EDX */ + .long 0 /* 16 - ESI */ + .long 0 /* 20 - EDI */ .code32 .globl __realmode_call @@ -89,17 +89,17 @@ /* initial register values */ movl 40(%ebp), %eax - movl %eax, __registers + 0x00 /* eax */ + movl %eax, __registers + 0 /* eax */ movl 44(%ebp), %eax - movl %eax, __registers + 0x04 /* ebx */ + movl %eax, __registers + 4 /* ebx */ movl 48(%ebp), %eax - movl %eax, __registers + 0x08 /* ecx */ + movl %eax, __registers + 8 /* ecx */ movl 52(%ebp), %eax - movl %eax, __registers + 0x0c /* edx */ + movl %eax, __registers + 12 /* edx */ movl 56(%ebp), %eax - movl %eax, __registers + 0x10 /* esi */ + movl %eax, __registers + 16 /* esi */ movl 60(%ebp), %eax - movl %eax, __registers + 0x14 /* esi */ + movl %eax, __registers + 20 /* edi */ /* Activate the right segment descriptor real mode. */ ljmp $0x28, $RELOCATED(1f) @@ -210,17 +210,17 @@ /* initial register values */ movl 40(%ebp), %eax - movl %eax, __registers + 0x00 /* eax */ + movl %eax, __registers + 0 /* eax */ movl 44(%ebp), %eax - movl %eax, __registers + 0x04 /* ebx */ + movl %eax, __registers + 4 /* ebx */ movl 48(%ebp), %eax - movl %eax, __registers + 0x08 /* ecx */ + movl %eax, __registers + 8 /* ecx */ movl 52(%ebp), %eax - movl %eax, __registers + 0x0c /* edx */ + movl %eax, __registers + 12 /* edx */ movl 56(%ebp), %eax - movl %eax, __registers + 0x10 /* esi */ + movl %eax, __registers + 16 /* esi */ movl 60(%ebp), %eax - movl %eax, __registers + 0x14 /* esi */ + movl %eax, __registers + 20 /* edi */ /* This configures CS properly for real mode. */ ljmp $0x28, $RELOCATED(1f)

1 0

(no subject)
by mbertens 23 May '10

23 May '10

hi all, I have a question about the PCI api and howto set registers on PCI devices. My system a Nokia IP530 has a BX440 northbridge and a 82371 southbrigde. The system has; - Dual IDE contoller (working) - Super I/O (Serial, keyb and flash-enable working) - 4 onboard NIC's 21143PD (1 NIC working) - PCMCIA controller dual slot PCI1225. I want to set the GPIOs of the SB to specific values to see if i can get the NICs and PCMCIA to work. All NICs get an IRQ assingment. So there must be some thing else that prevents them from working properly. Or if anyone has any good ideas for this problem let me known. Marc

4 8

Which machine is good for developing on coreboot?
by Jiang Wang 23 May '10

23 May '10

Hi all, I am a PhD student at a university and working on a research project which needs to modify the BIOS. Since most BIOS are close sourced, I choose the coreboot as the developing environment and thanks for providing such a good open source “BIOS”. Most of the existing computers in my lab are kind of new and Intel CPU based DELL desktop or servers. I guess they are not supported by coreboot. Therefore, I want to buy a new machine (my advisor will pay for that :) ) which is already well-supported by coreboot for developing, and I need your suggestions of which machine(x86 based desktop or workstation) is a good candidate. (Another reason I don’t like Intel based machine is that their documentation is poor compared to AMD. ) I have following requirements for the new machine. 1) Fully supported by coreboot. Especially, I want following support 2) Support Windows (XP) and Linux 3) Support ACPI S3 sleep (suspend to RAM) 4) Good documentation about how to detect and configure the memory (because I will modify this part for our project). I read coreboot Wiki and found out most supported parts are separated, such as CPU, motherboard, NB, SB, etc. Does that mean I need to buy all the parts and assemble the machine by myself? It is OK, but if there is some vendor providing a whole computer would be better. Or I guess I just need a good motherboard, any suggestions? Also, I prefer to buy an AMD K8 or K10 machine. Could someone recommend which main board should I use? I see “Pistachio” and “Tilapia” in the supported motherboard wiki, but I don’t know where I can buy those boards? Thanks. PS: I am new to BIOS development but have some experience in Linux and Window device driver. Regards, Jiang

2 1

Re: [coreboot] [PATCH] Promote heap sizing to first-class Kconfig citizenship.
by Joe Korty 22 May '10

22 May '10

I wrote: >> Unfortunately, the latest coreboot still gets an out-of-mem condition >> when the large pci-e chassis is attached. >> >> I've attached two coreboot logs, both are the latest svn but the second >> one has heap size at 0x10000 so that I can send you the log of what a >> good boot might look like. On Fri, May 21, 2010 at 04:33:12PM -0400, Myles Watson wrote: > That's a lot of devices. So maybe we need a Kconfig option called > ADDITIONAL_HEAP that's available on the EXPERT menu. It's possible that > making links into lists will make you fit, but I'd expect someone to shrink > the default heap when there's that much extra space for everyone else. I certainly think that that would be OK. It is impractical to come up with a default heap size to cover the largest possible IO configuration, since that would be very large indeed. Heck, even my failing large IO configuration is not really very large. I am putting only one expansion chassis on the system. I expect that we will eventually get customers that will want two or even three expansion chassis (each chassis holds 20 PCI-e cards). In one sense this is kinda exciting. Mainframes have always been about large IO. That's what distinguishes them from PCs. With these tweaks, PC-like machines can start to eat away at the bottom of that market. Regards, Joe Joe

4 5

[PATCH] Promote heap sizing to first-class Kconfig citizenship.
by Joe Korty 22 May '10

22 May '10

Promote heap sizing to first-class Kconfig citizenship. Changing the heap size is something that those, like me, with large PCI device trees need to do. Therefore heap size should appear as a normal, user-answerable question within the Kconfig build system. Also change the malloc debug message to more clearly indicate how much memory is left. Signed-off-by: Joe Korty <joe.korty(a)ccur.com> Index: trunk/src/Kconfig =================================================================== --- trunk.orig/src/Kconfig 2010-05-14 10:24:35.000000000 -0400 +++ trunk/src/Kconfig 2010-05-14 10:25:00.000000000 -0400 @@ -80,6 +80,17 @@ Enables the use of ccache for faster builds. Requires ccache in path. +config HEAP_SIZE + hex "Heap size (in bytes)" + default 0x4000 + help + The primary coreboot heap user is the PCI + bus walk. Therefore heap size may need to be + increased on systems that have exceptionally + large and/or deep PCI device trees. + + If unsure, use the default. + endmenu source src/mainboard/Kconfig @@ -124,10 +135,6 @@ bool default n -config HEAP_SIZE - hex - default 0x4000 - config DEBUG bool default n Index: trunk/src/lib/malloc.c =================================================================== --- trunk.orig/src/lib/malloc.c 2010-05-14 10:24:35.000000000 -0400 +++ trunk/src/lib/malloc.c 2010-05-14 10:25:00.000000000 -0400 @@ -14,7 +14,10 @@ { void *p; - MALLOCDBG("%s Enter, size %ld, free_mem_ptr %p\n", __func__, size, free_mem_ptr); + MALLOCDBG("%s Enter, size %ld, %d of %d bytes available.\n", + __func__, size, + (int)(free_mem_end_ptr - free_mem_ptr), + (int)(&_eheap - &_heap)); /* Checking arguments */ if (size < 0)

5 15

← Newer
1
...
7
8
9
10
11
12
13
...
30
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot May 2010