August 2009 - coreboot - mail.coreboot.org

[PATCH] Add amd/dbm690t comments to devicetree.cb
by Carl-Daniel Hailfinger Aug. 28, 2009

Aug. 28, 2009

r4534 introduced devicetree.cb in every mainboard directory, but didn't copy any comment lines before the start of the device tree. Sometimes, these comments refer to the device tree and need to be present on devicetree.cb if Config.lb is ever dropped. Fix the amd/dbm690t target. I went through the remaining 110 boards by hand and the following files are in need of attention: amd/pistachio/Config.lb missing comment msi/ms6178/Config.lb change via/epia-m700/Config.lb change lippert/spacerunner-lx/Config.lb missing setting lippert/roadrunner-lx/Config.lb misssing setting technexion/tim8690/Config.lb misssing comment gigabyte/m57sli/Config.lb change Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/devicetree.cb =================================================================== --- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/devicetree.cb (Revision 4605) +++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/devicetree.cb (Arbeitskopie) @@ -1,3 +1,14 @@ +#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) +#Define vga_rom_address = 0xfff0000 +#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) +#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, +# 1: the system allows a PCIE link to be established on Dev2 or Dev3. +#Define gfx_dual_slot, 0: single slot, 1: dual slot +#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable +#Define gfx_tmds, 0: didn't support TMDS, 1: support +#Define gfx_compliance, 0: didn't support compliance, 1: support +#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration +#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 chip northbridge/amd/amdk8/root_complex device apic_cluster 0 on chip cpu/amd/socket_S1G1 -- http://www.hailfinger.org/

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[v2] r4614 - trunk/coreboot-v2/src/mainboard/amd/dbm690t
by svn＠coreboot.org Aug. 28, 2009

Aug. 28, 2009

Author: hailfinger Date: 2009-08-28 21:00:59 +0200 (Fri, 28 Aug 2009) New Revision: 4614 Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/devicetree.cb Log: r4534 introduced devicetree.cb in every mainboard directory, but didn't copy any comment lines before the start of the device tree. Copy over the comments for amd/dbm690t. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/devicetree.cb 2009-08-28 16:38:42 UTC (rev 4613) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/devicetree.cb 2009-08-28 19:00:59 UTC (rev 4614) @@ -1,3 +1,14 @@ +#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) +#Define vga_rom_address = 0xfff0000 +#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) +#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, +# 1: the system allows a PCIE link to be established on Dev2 or Dev3. +#Define gfx_dual_slot, 0: single slot, 1: dual slot +#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable +#Define gfx_tmds, 0: didn't support TMDS, 1: support +#Define gfx_compliance, 0: didn't support compliance, 1: support +#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration +#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 chip northbridge/amd/amdk8/root_complex device apic_cluster 0 on chip cpu/amd/socket_S1G1

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[patch] AMD S1G1 socket in kconfig
by Cristi Magherusan Aug. 28, 2009

Aug. 28, 2009

Please see the attached patch. -- Signed-off-by: Cristi Magherusan <cristi.magherusan(a)net.utcluj.ro>

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Re: [coreboot] [v2] r4612 - trunk/coreboot-v2/src/mainboard
by Myles Watson Aug. 28, 2009

Aug. 28, 2009

On Fri, Aug 28, 2009 at 9:22 AM, <svn(a)coreboot.org> wrote: > Author: uwe > Date: 2009-08-28 17:22:31 +0200 (Fri, 28 Aug 2009) > New Revision: 4612 > - Use alphabetical order. I think they were alphabetized before in the same way that ls alphabetizes them. $ ls src/mainboard | grep ^a a-trend abit advantech amd arima artecgroup -Myles

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[PATCH] Add kconfig support for all Intel 82810 (i810) boards
by Uwe Hermann Aug. 28, 2009

Aug. 28, 2009

See patch. Will test on some hardware later, for now this is untested (but should work). Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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[v2] r4613 - in trunk/coreboot-v2/src: mainboard mainboard/asus mainboard/asus/mew-am mainboard/asus/mew-vm mainboard/mitac mainboard/mitac/6513wu mainboard/msi mainboard/msi/ms6178 mainboard/nec mainboard/nec/powermate2000 southbridge/intel/i82801xx
by svn＠coreboot.org Aug. 28, 2009

Aug. 28, 2009

Author: uwe Date: 2009-08-28 18:38:42 +0200 (Fri, 28 Aug 2009) New Revision: 4613 Added: trunk/coreboot-v2/src/mainboard/asus/mew-am/Kconfig trunk/coreboot-v2/src/mainboard/asus/mew-am/Makefile.inc trunk/coreboot-v2/src/mainboard/asus/mew-vm/Kconfig trunk/coreboot-v2/src/mainboard/asus/mew-vm/Makefile.inc trunk/coreboot-v2/src/mainboard/mitac/6513wu/Kconfig trunk/coreboot-v2/src/mainboard/mitac/6513wu/Makefile.inc trunk/coreboot-v2/src/mainboard/msi/ms6178/Kconfig trunk/coreboot-v2/src/mainboard/msi/ms6178/Makefile.inc trunk/coreboot-v2/src/mainboard/nec/powermate2000/Kconfig trunk/coreboot-v2/src/mainboard/nec/powermate2000/Makefile.inc Modified: trunk/coreboot-v2/src/mainboard/Makefile.romccboard.inc trunk/coreboot-v2/src/mainboard/asus/Kconfig trunk/coreboot-v2/src/mainboard/mitac/Kconfig trunk/coreboot-v2/src/mainboard/msi/Kconfig trunk/coreboot-v2/src/mainboard/msi/ms6178/devicetree.cb trunk/coreboot-v2/src/mainboard/nec/Kconfig trunk/coreboot-v2/src/southbridge/intel/i82801xx/Makefile.inc Log: Add kconfig support for all Intel 82810 (i810) boards. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: trunk/coreboot-v2/src/mainboard/Makefile.romccboard.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/Makefile.romccboard.inc 2009-08-28 15:22:31 UTC (rev 4612) +++ trunk/coreboot-v2/src/mainboard/Makefile.romccboard.inc 2009-08-28 16:38:42 UTC (rev 4613) @@ -47,8 +47,13 @@ $(obj)/mainboard/$(MAINBOARDDIR)/failover.inc: $(obj)/romcc $(src)/arch/i386/lib/failover.c $(obj)/romcc -mcpu=p2 -O2 --label-prefix=failover $(INCLUDES) $(src)/arch/i386/lib/failover.c -o $@ +ifeq ($(HAVE_OPTION_TABLE),y) +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(obj)/romcc $(src)/mainboard/$(MAINBOARDDIR)/auto.c $(obj)/option_table.h + $(obj)/romcc -mcpu=p2 -O2 $(INCLUDES) $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@ +else $(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(obj)/romcc $(src)/mainboard/$(MAINBOARDDIR)/auto.c $(obj)/romcc -mcpu=p2 -O2 $(INCLUDES) $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@ +endif endif Modified: trunk/coreboot-v2/src/mainboard/asus/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/Kconfig 2009-08-28 15:22:31 UTC (rev 4612) +++ trunk/coreboot-v2/src/mainboard/asus/Kconfig 2009-08-28 16:38:42 UTC (rev 4613) @@ -27,6 +27,8 @@ source "src/mainboard/asus/p2b-f/Kconfig" source "src/mainboard/asus/p3b-f/Kconfig" source "src/mainboard/asus/m2v-mx_se/Kconfig" +source "src/mainboard/asus/mew-am/Kconfig" +source "src/mainboard/asus/mew-vm/Kconfig" endchoice Added: trunk/coreboot-v2/src/mainboard/asus/mew-am/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/mew-am/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/asus/mew-am/Kconfig 2009-08-28 16:38:42 UTC (rev 4613) @@ -0,0 +1,59 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config BOARD_ASUS_MEW_AM + bool "MEW-AM" + select ARCH_X86 + select CPU_INTEL_SOCKET_PGA370 + select NORTHBRIDGE_INTEL_I82810 + select SOUTHBRIDGE_INTEL_I82801XX + select SUPERIO_SMSC_SMSCSUPERIO + select HAVE_PIRQ_TABLE + select UDELAY_IO + select PCI_ROM_RUN + select CONSOLE_VGA + help + ASUS MEW-AM mainboard. + +config MAINBOARD_DIR + string + default asus/mew-am + depends on BOARD_ASUS_MEW_AM + +config MAINBOARD_PART_NUMBER + string + default "MEW-AM" + depends on BOARD_ASUS_MEW_AM + +config HAVE_OPTION_TABLE + bool + default n + depends on BOARD_ASUS_MEW_AM + +config IRQ_SLOT_COUNT + int + default 8 + depends on BOARD_ASUS_MEW_AM + +config VIDEO_MB + int + default 1 + depends on BOARD_ASUS_MEW_AM + Added: trunk/coreboot-v2/src/mainboard/asus/mew-am/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/mew-am/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/asus/mew-am/Makefile.inc 2009-08-28 16:38:42 UTC (rev 4613) @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +include $(src)/mainboard/Makefile.romccboard.inc + Added: trunk/coreboot-v2/src/mainboard/asus/mew-vm/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/mew-vm/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/asus/mew-vm/Kconfig 2009-08-28 16:38:42 UTC (rev 4613) @@ -0,0 +1,54 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config BOARD_ASUS_MEW_VM + bool "MEW-VM" + select ARCH_X86 + select CPU_INTEL_SOCKET_PGA370 + select NORTHBRIDGE_INTEL_I82810 + select SOUTHBRIDGE_INTEL_I82801XX + select SUPERIO_SMSC_SMSCSUPERIO + select HAVE_PIRQ_TABLE + select UDELAY_IO + select PCI_ROM_RUN + select CONSOLE_VGA + help + ASUS MEW-VM mainboard. + +config MAINBOARD_DIR + string + default asus/mew-vm + depends on BOARD_ASUS_MEW_VM + +config MAINBOARD_PART_NUMBER + string + default "MEW-VM" + depends on BOARD_ASUS_MEW_VM + +config IRQ_SLOT_COUNT + int + default 11 + depends on BOARD_ASUS_MEW_VM + +config VIDEO_MB + int + default 1 + depends on BOARD_ASUS_MEW_VM + Added: trunk/coreboot-v2/src/mainboard/asus/mew-vm/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/mew-vm/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/asus/mew-vm/Makefile.inc 2009-08-28 16:38:42 UTC (rev 4613) @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +include $(src)/mainboard/Makefile.romccboard.inc + Added: trunk/coreboot-v2/src/mainboard/mitac/6513wu/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/mitac/6513wu/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/mitac/6513wu/Kconfig 2009-08-28 16:38:42 UTC (rev 4613) @@ -0,0 +1,59 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config BOARD_MITAC_6513WU + bool "6513WU" + select ARCH_X86 + select CPU_INTEL_SOCKET_PGA370 + select NORTHBRIDGE_INTEL_I82810 + select SOUTHBRIDGE_INTEL_I82801XX + select SUPERIO_SMSC_SMSCSUPERIO + select HAVE_PIRQ_TABLE + select UDELAY_IO + select PCI_ROM_RUN + select CONSOLE_VGA + help + Mitac 6513WU mainboard. + +config MAINBOARD_DIR + string + default mitac/6513wu + depends on BOARD_MITAC_6513WU + +config MAINBOARD_PART_NUMBER + string + default "6513WU" + depends on BOARD_MITAC_6513WU + +config HAVE_OPTION_TABLE + bool + default n + depends on BOARD_MITAC_6513WU + +config IRQ_SLOT_COUNT + int + default 8 + depends on BOARD_MITAC_6513WU + +config VIDEO_MB + int + default 1 + depends on BOARD_MITAC_6513WU + Added: trunk/coreboot-v2/src/mainboard/mitac/6513wu/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/mitac/6513wu/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/mitac/6513wu/Makefile.inc 2009-08-28 16:38:42 UTC (rev 4613) @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +include $(src)/mainboard/Makefile.romccboard.inc + Modified: trunk/coreboot-v2/src/mainboard/mitac/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/mitac/Kconfig 2009-08-28 15:22:31 UTC (rev 4612) +++ trunk/coreboot-v2/src/mainboard/mitac/Kconfig 2009-08-28 16:38:42 UTC (rev 4613) @@ -1 +1,28 @@ -# +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +choice + prompt "Mainboard model" + depends on VENDOR_MITAC + +source "src/mainboard/mitac/6513wu/Kconfig" + +endchoice + Modified: trunk/coreboot-v2/src/mainboard/msi/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/Kconfig 2009-08-28 15:22:31 UTC (rev 4612) +++ trunk/coreboot-v2/src/mainboard/msi/Kconfig 2009-08-28 16:38:42 UTC (rev 4613) @@ -24,6 +24,7 @@ source "src/mainboard/msi/ms6119/Kconfig" source "src/mainboard/msi/ms6147/Kconfig" +source "src/mainboard/msi/ms6178/Kconfig" endchoice Added: trunk/coreboot-v2/src/mainboard/msi/ms6178/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms6178/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/msi/ms6178/Kconfig 2009-08-28 16:38:42 UTC (rev 4613) @@ -0,0 +1,59 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config BOARD_MSI_MS_6178 + bool "MS-6178" + select ARCH_X86 + select CPU_INTEL_SOCKET_PGA370 + select NORTHBRIDGE_INTEL_I82810 + select SOUTHBRIDGE_INTEL_I82801XX + select SUPERIO_WINBOND_W83627HF + select HAVE_PIRQ_TABLE + select UDELAY_IO + select PCI_ROM_RUN + select CONSOLE_VGA + help + MSI MS-6178 mainboard. + +config MAINBOARD_DIR + string + default msi/ms6178 + depends on BOARD_MSI_MS_6178 + +config MAINBOARD_PART_NUMBER + string + default "MS-6178" + depends on BOARD_MSI_MS_6178 + +config HAVE_OPTION_TABLE + bool + default n + depends on BOARD_MSI_MS_6178 + +config IRQ_SLOT_COUNT + int + default 4 + depends on BOARD_MSI_MS_6178 + +config VIDEO_MB + int + default 1 + depends on BOARD_MSI_MS_6178 + Added: trunk/coreboot-v2/src/mainboard/msi/ms6178/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms6178/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/msi/ms6178/Makefile.inc 2009-08-28 16:38:42 UTC (rev 4613) @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +include $(src)/mainboard/Makefile.romccboard.inc + Modified: trunk/coreboot-v2/src/mainboard/msi/ms6178/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms6178/devicetree.cb 2009-08-28 15:22:31 UTC (rev 4612) +++ trunk/coreboot-v2/src/mainboard/msi/ms6178/devicetree.cb 2009-08-28 16:38:42 UTC (rev 4613) @@ -1,3 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + chip northbridge/intel/i82810 # Northbridge device apic_cluster 0 on # APIC cluster chip cpu/intel/socket_PGA370 # CPU @@ -6,11 +26,9 @@ end device pci_domain 0 on device pci 0.0 on end # Host bridge - device pci 1.0 off # Onboard video - # chip drivers/pci/onboard - # device pci 1.0 on end - # register "rom_address" = "0xfff80000" - # end + chip drivers/pci/onboard # Onboard VGA + device pci 1.0 on end + register "rom_address" = "0xfff80000" # 512 KB image end chip southbridge/intel/i82801xx # Southbridge register "ide0_enable" = "1" @@ -43,7 +61,7 @@ irq 0x70 = 1 # Keyboard interrupt irq 0x72 = 12 # Mouse interrupt end - device pnp 2e.6 on end # Consumer IR (TODO) + device pnp 2e.6 off end # Consumer IR (TODO) device pnp 2e.7 on # Game port / MIDI / GPIO 1 io 0x60 = 0x201 io 0x62 = 0x330 Modified: trunk/coreboot-v2/src/mainboard/nec/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/nec/Kconfig 2009-08-28 15:22:31 UTC (rev 4612) +++ trunk/coreboot-v2/src/mainboard/nec/Kconfig 2009-08-28 16:38:42 UTC (rev 4613) @@ -1 +1,28 @@ -# +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +choice + prompt "Mainboard model" + depends on VENDOR_NEC + +source "src/mainboard/nec/powermate2000/Kconfig" + +endchoice + Added: trunk/coreboot-v2/src/mainboard/nec/powermate2000/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/nec/powermate2000/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/nec/powermate2000/Kconfig 2009-08-28 16:38:42 UTC (rev 4613) @@ -0,0 +1,59 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config BOARD_NEC_POWERMATE_2000 + bool "PowerMate 2000" + select ARCH_X86 + select CPU_INTEL_SOCKET_PGA370 + select NORTHBRIDGE_INTEL_I82810 + select SOUTHBRIDGE_INTEL_I82801XX + select SUPERIO_SMSC_SMSCSUPERIO + select HAVE_PIRQ_TABLE + select UDELAY_IO + select PCI_ROM_RUN + select CONSOLE_VGA + help + NEC PowerMate 2000 mainboard. + +config MAINBOARD_DIR + string + default nec/powermate2000 + depends on BOARD_NEC_POWERMATE_2000 + +config MAINBOARD_PART_NUMBER + string + default "PowerMate 2000" + depends on BOARD_NEC_POWERMATE_2000 + +config HAVE_OPTION_TABLE + bool + default n + depends on BOARD_NEC_POWERMATE_2000 + +config IRQ_SLOT_COUNT + int + default 5 + depends on BOARD_NEC_POWERMATE_2000 + +config VIDEO_MB + int + default 1 + depends on BOARD_NEC_POWERMATE_2000 + Added: trunk/coreboot-v2/src/mainboard/nec/powermate2000/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/nec/powermate2000/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/nec/powermate2000/Makefile.inc 2009-08-28 16:38:42 UTC (rev 4613) @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +include $(src)/mainboard/Makefile.romccboard.inc + Modified: trunk/coreboot-v2/src/southbridge/intel/i82801xx/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801xx/Makefile.inc 2009-08-28 15:22:31 UTC (rev 4612) +++ trunk/coreboot-v2/src/southbridge/intel/i82801xx/Makefile.inc 2009-08-28 16:38:42 UTC (rev 4613) @@ -25,7 +25,7 @@ driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) += i82801xx_nic.o driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) += i82801xx_pci.o driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) += i82801xx_sata.o -driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) += i82801xx_smbus.o +# driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) += i82801xx_smbus.o driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) += i82801xx_usb.o driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) += i82801xx_usb_ehci.o @@ -34,3 +34,5 @@ # TODO: What about cmos_failover.c? +# TODO: Fix and enable i82801xx_smbus.o later. +

1 0

Re: [coreboot] [v2] r4611 - in trunk/coreboot-v2/src: cpu/amd/model_gx2 northbridge/amd/gx2 southbridge/amd/cs5536
by Stefan Reinauer Aug. 28, 2009

Aug. 28, 2009

On 8/28/09 4:47 PM, svn(a)coreboot.org wrote: > - case 0xBEA7: > - *eax=33; > - break; > - case 0xBEA4: > - *eax=333; > - break; > What about these int15 callbacks? I've seen from logs that the VSA code calls these interrupts. Are they not needed? Stefan -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

3 3

Kconfig for Tyan s2891, s2892, s2895
by Myles Watson Aug. 28, 2009

Aug. 28, 2009

They all build. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

2 4

[v2] r4612 - trunk/coreboot-v2/src/mainboard
by svn＠coreboot.org Aug. 28, 2009

Aug. 28, 2009

Author: uwe Date: 2009-08-28 17:22:31 +0200 (Fri, 28 Aug 2009) New Revision: 4612 Modified: trunk/coreboot-v2/src/mainboard/Kconfig Log: kconfig: Board name variable fixes and updates (trivial). - Use alphabetical order. - Drop non-exisiting vendors. - Add missing vendors (Mitac, Soyo, Technologic, TeleVideo). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/coreboot-v2/src/mainboard/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/Kconfig 2009-08-28 14:46:59 UTC (rev 4611) +++ trunk/coreboot-v2/src/mainboard/Kconfig 2009-08-28 15:22:31 UTC (rev 4612) @@ -4,14 +4,10 @@ prompt "Mainboard vendor" default VENDOR_EMULATION -config VENDOR_A_TREND - bool "A-Trend" config VENDOR_ABIT bool "Abit" config VENDOR_ADVANTECH bool "Advantech" -config VENDOR_AGAMI - bool "agami" config VENDOR_AMD bool "AMD" config VENDOR_ARIMA @@ -22,6 +18,8 @@ bool "ASI" config VENDOR_ASUS bool "ASUS" +config VENDOR_A_TREND + bool "A-Trend" config VENDOR_AXUS bool "AXUS" config VENDOR_AZZA @@ -62,6 +60,8 @@ bool "Kontron" config VENDOR_LIPPERT bool "Lippert" +config VENDOR_MITAC + bool "Mitac" config VENDOR_MOTOROLA bool "Motorola" config VENDOR_MSI @@ -78,12 +78,18 @@ bool "PC Engines" config VENDOR_RCA bool "RCA" +config VENDOR_SOYO + bool "Soyo" config VENDOR_SUNW bool "Sun" config VENDOR_SUPERMICRO bool "Supermicro" config VENDOR_TECHNEXION bool "Technexion" +config VENDOR_TECHNOLOGIC + bool "Technologic" +config VENDOR_TELEVIDEO + bool "TeleVideo" config VENDOR_THOMSON bool "Thomson" config VENDOR_TOTAL_IMPACT @@ -97,11 +103,6 @@ config MAINBOARD_VENDOR string - default "A-Trend" - depends on VENDOR_A_TREND - -config MAINBOARD_VENDOR - string default "Abit" depends on VENDOR_ABIT @@ -112,11 +113,6 @@ config MAINBOARD_VENDOR string - default "agami" - depends on VENDOR_AGAMI - -config MAINBOARD_VENDOR - string default "AMD" depends on VENDOR_AMD @@ -142,6 +138,11 @@ config MAINBOARD_VENDOR string + default "A-Trend" + depends on VENDOR_A_TREND + +config MAINBOARD_VENDOR + string default "AXUS" depends on VENDOR_AXUS @@ -242,6 +243,11 @@ config MAINBOARD_VENDOR string + default "Mitac" + depends on VENDOR_MITAC + +config MAINBOARD_VENDOR + string default "Motorola" depends on VENDOR_MOTOROLA @@ -282,6 +288,11 @@ config MAINBOARD_VENDOR string + default "Soyo" + depends on VENDOR_SOYO + +config MAINBOARD_VENDOR + string default "Sun" depends on VENDOR_SUNW @@ -297,6 +308,16 @@ config MAINBOARD_VENDOR string + default "Technologic" + depends on VENDOR_TECHNOLOGIC + +config MAINBOARD_VENDOR + string + default "TeleVideo" + depends on VENDOR_TELEVIDEO + +config MAINBOARD_VENDOR + string default "Thomson" depends on VENDOR_THOMSON

1 0

[v2] r4611 - in trunk/coreboot-v2/src: cpu/amd/model_gx2 northbridge/amd/gx2 southbridge/amd/cs5536
by svn＠coreboot.org Aug. 28, 2009

Aug. 28, 2009

Author: rminnich Date: 2009-08-28 16:46:59 +0200 (Fri, 28 Aug 2009) New Revision: 4611 Added: trunk/coreboot-v2/src/cpu/amd/model_gx2/Kconfig trunk/coreboot-v2/src/cpu/amd/model_gx2/Makefile.inc trunk/coreboot-v2/src/northbridge/amd/gx2/Kconfig trunk/coreboot-v2/src/northbridge/amd/gx2/Makefile.inc trunk/coreboot-v2/src/southbridge/amd/cs5536/Kconfig trunk/coreboot-v2/src/southbridge/amd/cs5536/Makefile.inc Modified: trunk/coreboot-v2/src/cpu/amd/model_gx2/vsmsetup.c trunk/coreboot-v2/src/northbridge/amd/gx2/northbridge.c Log: This is the beginning of support for Geode and Kconfig in v2. It also brings in the vsm from v3, which was a much cleaner cut. Over time, I hope to bring all the code back from v3. I have some rumbas at home and want to use them. I have a patch which comes in next that makes the rumba build. Note that I am holding the src/*/amd/Kconfig patch until these get merged. These have no impact on the current system. Note that this is not complete but I want to fill in the blanks bit by bit. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Added: trunk/coreboot-v2/src/cpu/amd/model_gx2/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_gx2/Kconfig (rev 0) +++ trunk/coreboot-v2/src/cpu/amd/model_gx2/Kconfig 2009-08-28 14:46:59 UTC (rev 4611) @@ -0,0 +1,3 @@ +config CPU_AMD_GX2 + bool + default false Added: trunk/coreboot-v2/src/cpu/amd/model_gx2/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_gx2/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/cpu/amd/model_gx2/Makefile.inc 2009-08-28 14:46:59 UTC (rev 4611) @@ -0,0 +1,9 @@ +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/fpu +subdirs-y += ../../x86/mmx +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/smm +driver-y += model_gx2_init.o +obj-y += cpubug.o +obj-y += vsmsetup.o Modified: trunk/coreboot-v2/src/cpu/amd/model_gx2/vsmsetup.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_gx2/vsmsetup.c 2009-08-28 14:40:04 UTC (rev 4610) +++ trunk/coreboot-v2/src/cpu/amd/model_gx2/vsmsetup.c 2009-08-28 14:46:59 UTC (rev 4611) @@ -1,771 +1,229 @@ -#include <console/console.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#undef __KERNEL__ -#include <arch/io.h> -#include <string.h> -#include <cpu/amd/gx2def.h> - -/* what a mess this uncompress thing is. I am not at all happy about how this - * was done, but can't fix it yet. RGM - */ -#warning "Fix the uncompress once coreboot knows how to do it" -#include "../lib/nrv2b.c" - -/* vsmsetup.c derived from vgabios.c. Derived from: */ - -/*------------------------------------------------------------ -*- C -*- - * 2 Kernel Monte a.k.a. Linux loading Linux on x86 +/* + * This file is part of the coreboot project. * - * Erik Arjan Hendriks <hendriks(a)lanl.gov> + * Copyright (C) 2000 Erik Arjan Hendriks + * Copyright (C) 2000 Scyld Computing Corporation + * Copyright (C) 2001 University of California. LA-CC Number 01-67. + * Copyright (C) 2005 Nick.Barker9(a)btinternet.com + * Copyright (C) 2007 coresystems GmbH * - * This version is a derivative of the original two kernel monte - * which is (C) 2000 Scyld. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. * - * Copyright (C) 2000 Scyld Computing Corporation + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - * - * Portions related to the alpha architecture are: - * - * Copyright(C) 2001 University of California. LA-CC Number 01-67. - * This software has been authored by an employee or employees of the - * University of California, operator of the Los Alamos National - * Laboratory under Contract No. W-7405-ENG-36 with the U.S. - * Department of Energy. The U.S. Government has rights to use, - * reproduce, and distribute this software. If the software is - * modified to produce derivative works, such modified software should - * be clearly marked, so as not to confuse it with the version - * available from LANL. - * - * This software may be used and distributed according to the terms - * of the GNU General Public License, incorporated herein by - * reference to http://www.gnu.org/licenses/gpl.html. - * - * This software is provided by the author(s) "as is" and any express - * or implied warranties, including, but not limited to, the implied - * warranties of merchantability and fitness for a particular purpose - * are disclaimed. In no event shall the author(s) be liable for any - * direct, indirect, incidental, special, exemplary, or consequential - * damages (including, but not limited to, procurement of substitute - * goods or services; loss of use, data, or profits; or business - * interruption) however caused and on any theory of liability, - * whether in contract, strict liability, or tort (including - * negligence or otherwise) arising in any way out of the use of this - * software, even if advised of the possibility of such damage. - * - * $Id: Exp $ - *--------------------------------------------------------------------*/ + * LA-CC is the Los Alamos Control and Compliance Number, see also: + * http://supply.lanl.gov/property/customs/eximguide/default.shtml + */ -/* Modified to be a self sufficient plug in so that it can be used - without reliance on other parts of core coreboot - (C) 2005 Nick.Barker9(a)btinternet.com +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <string.h> +#include <cpu/cpu.h> +#include <cpu/x86/lapic.h> +#include <cpu/x86/cache.h> +#include <arch/io.h> - Used initially for epia-m where there are problems getting the bios - emulator to successfully run this bios. -*/ +u32 VSA_vrRead(u16 classIndex); +void do_vsmbios(void); -/* Declare a temporary global descriptor table - necessary because the - Core part of the bios no longer sets up any 16 bit segments */ -__asm__ ( - /* pointer to original gdt */ - "gdtarg: \n" - " .word gdt_limit \n" - " .long gdt \n" - - /* compute the table limit */ - "__mygdt_limit = __mygdt_end - __mygdt - 1 \n" - - "__mygdtaddr: \n" - " .word __mygdt_limit \n" - " .long __mygdt \n" - - "__mygdt: \n" - /* selgdt 0, unused */ - " .word 0x0000, 0x0000 \n" - " .byte 0x00, 0x00, 0x00, 0x00 \n" - - /* selgdt 8, unused */ - " .word 0x0000, 0x0000 \n" - " .byte 0x00, 0x00, 0x00, 0x00 \n" - - /* selgdt 0x10, flat code segment */ - " .word 0xffff, 0x0000 \n" - " .byte 0x00, 0x9b, 0xcf, 0x00 \n" - - /* selgdt 0x18, flat data segment */ - " .word 0xffff, 0x0000 \n" - " .byte 0x00, 0x93, 0xcf, 0x00 \n" - - /* selgdt 0x20, unused */ - " .word 0x0000, 0x0000 \n" - " .byte 0x00, 0x00, 0x00, 0x00 \n" - - /* selgdt 0x28 16-bit 64k code at 0x00000000 */ - " .word 0xffff, 0x0000 \n" - " .byte 0, 0x9a, 0, 0 \n" - - /* selgdt 0x30 16-bit 64k data at 0x00000000 */ - " .word 0xffff, 0x0000 \n" - " .byte 0, 0x92, 0, 0 \n" - - "__mygdt_end: \n" -); - -/* Declare a pointer to where our idt is going to be i.e. at mem zero */ -__asm__ ("__myidt: \n" - /* 16-bit limit */ - " .word 1023 \n" - /* 24-bit base */ - " .long 0 \n" - " .word 0 \n" -); - -/* The address arguments to this function are PHYSICAL ADDRESSES */ +#define VSA2_BUFFER 0x60000 +#define VSA2_ENTRY_POINT 0x60020 +#define VSA2_SIGNATURE 0x56534132 // 'VSA2' returned in EAX +#define SIGNATURE 0x03 +/** + * TODO. + * + * The address arguments to this function are PHYSICAL ADDRESSES! + * + * @param smm TODO. + * @param sysm TODO. + */ static void real_mode_switch_call_vsm(unsigned long smm, unsigned long sysm) { - __asm__ __volatile__ ( - // paranoia -- does ecx get saved? not sure. This is - // the easiest safe thing to do. + u16 entryHi = (VSA2_ENTRY_POINT & 0xffff0000) >> 4; + u16 entryLo = (VSA2_ENTRY_POINT & 0xffff); + + __asm__ __volatile__( + /* Paranoia -- does ecx get saved? not sure. This is + * the easiest safe thing to do. + */ " pushal \n" - /* save the stack */ - " mov %esp, __stack \n" + /* Save the stack. */ + " mov %%esp, __stack \n" " jmp 1f \n" - "__stack: .long 0 \n" + "__stack: .long 0 \n" "1:\n" - /* get devfn into %ecx */ - " movl %esp, %ebp \n" -#if 0 - /* I'm not happy about that pushal followed by esp-relative references. - * just do hard-codes for now - */ - " movl 8(%ebp), %ecx \n" - " movl 12(%ebp), %edx \n" -#endif - " movl $0x10000026, %ecx \n" - " movl $0x10000028, %edx \n" - - /* load 'our' gdt */ - " lgdt %cs:__mygdtaddr \n" - - /* This configures CS properly for real mode. */ + /* Get devfn into %%ecx. */ + " movl %%esp, %%ebp \n" + /* Get the smm and sysm args into ecx and edx. */ + " movl %0, %%ecx \n" + " movl %1, %%edx \n" + /* Load 'our' gdt. */ + " lgdt %%cs:__mygdtaddr \n" + /* This configures CS properly for real mode. */ " ljmp $0x28, $__rms_16bit\n" "__rms_16bit: \n" " .code16 \n" /* 16 bit code from here on... */ - - /* Load the segment registers w/ properly configured segment - * descriptors. They will retain these configurations (limits, - * writability, etc.) once protected mode is turned off. */ - " mov $0x30, %ax \n" - " mov %ax, %ds \n" - " mov %ax, %es \n" - " mov %ax, %fs \n" - " mov %ax, %gs \n" - " mov %ax, %ss \n" - - /* Turn off protection (bit 0 in CR0) */ - " movl %cr0, %eax \n" - " andl $0xFFFFFFFE, %eax \n" - " movl %eax, %cr0 \n" - - /* Now really going into real mode */ + /* Load the segment registers with properly configured segment + * descriptors. They will retain these configurations (limits, + * writability, etc.) once protected mode is turned off. + */ + " mov $0x30, %%ax \n" + " mov %%ax, %%ds \n" + " mov %%ax, %%es \n" + " mov %%ax, %%fs \n" + " mov %%ax, %%gs \n" + " mov %%ax, %%ss \n" + /* Turn off protection (bit 0 in CR0). */ + " movl %%cr0, %%eax \n" + " andl $0xFFFFFFFE, %%eax \n" + " movl %%eax, %%cr0 \n" + /* Now really going into real mode. */ " ljmp $0, $__rms_real\n" "__rms_real: \n" - /* put the stack at the end of page zero. - * that way we can easily share it between real and protected, - * since the 16-bit ESP at segment 0 will work for any case. */ - /* Setup a stack */ - " mov $0x0, %ax \n" - " mov %ax, %ss \n" - " movl $0x1000, %eax \n" - " movl %eax, %esp \n" + /* Put the stack at the end of page zero. + * That way we can easily share it between real and protected, + * since the 16-bit ESP at segment 0 will work for any case. + */ - /* Load our 16 it idt */ - " xor %ax, %ax \n" - " mov %ax, %ds \n" - " lidt __myidt \n" - - /* Dump zeros in the other segregs */ - " mov %ax, %es \n" - /* FixMe: Big real mode for gs, fs? */ - " mov %ax, %fs \n" - " mov %ax, %gs \n" - " mov $0x40, %ax \n" - " mov %ax, %ds \n" - //" mov %cx, %ax \n" - " movl $0x10000026, %ecx \n" - " movl $0x10000028, %edx \n" - - /* run VGA BIOS at 0x6000:0020 */ - " lcall $0x6000, $0x0020\n" - - /* if we got here, just about done. - * Need to get back to protected mode */ - " movl %cr0, %eax \n" - " orl $0x0000001, %eax\n" /* PE = 1 */ - " movl %eax, %cr0 \n" - - /* Now that we are in protected mode jump to a 32 bit code segment. */ + /* Setup a stack. */ + " mov $0x0, %%ax \n" + " mov %%ax, %%ss \n" + " movl $0x1000, %%eax \n" + " movl %%eax, %%esp \n" + /* Dump zeros in the other segregs. */ + " mov %%ax, %%es \n" + /* FIXME: Big real mode for gs, fs? */ + " mov %%ax, %%fs \n" + " mov %%ax, %%gs \n" + " mov $0x40, %%ax \n" + " mov %%ax, %%ds \n" + /* " mov %%cx, %%ax \n" */ + " movl %0, %%ecx \n" + " movl %1, %%edx \n" + /* Call the VSA2 entry point address. */ + " lcall %2, %3\n" + /* If we got here, just about done. + * Need to get back to protected mode. + */ + " movl %%cr0, %%eax \n" + " orl $0x0000001, %%eax\n" /* PE = 1 */ + " movl %%eax, %%cr0 \n" + /* Now that we are in protected mode, + * jump to a 32 bit code segment. + */ " data32 ljmp $0x10, $vsmrestart\n" "vsmrestart:\n" " .code32\n" - " movw $0x18, %ax \n" - " mov %ax, %ds \n" - " mov %ax, %es \n" - " mov %ax, %fs \n" - " mov %ax, %gs \n" - " mov %ax, %ss \n" - - /* restore proper gdt and idt */ - " lgdt %cs:gdtarg \n" - " lidt idtarg \n" - + " movw $0x18, %%ax \n" + " mov %%ax, %%ds \n" + " mov %%ax, %%es \n" + " mov %%ax, %%fs \n" + " mov %%ax, %%gs \n" + " mov %%ax, %%ss \n" + /* Restore proper gdt. */ + " lgdt %%cs:gdtarg \n" ".globl vsm_exit \n" "vsm_exit: \n" - " mov __stack, %esp \n" - " popal \n" - ); + " mov __stack, %%esp \n" + " popal \n":: + "g" (smm), "g"(sysm), "g"(entryHi), "g"(entryLo) + ); } -__asm__ (".text\n""real_mode_switch_end:\n"); +__asm__(".text\n" "real_mode_switch_end:\n"); extern char real_mode_switch_end[]; +/* andrei: Some VSA virtual register helpers: raw read and MSR read. */ +u32 VSA_vrRead(u16 classIndex) +{ + unsigned eax, ebx, ecx, edx; + asm volatile ( + "movw $0x0AC1C, %%dx \n" + "orl $0x0FC530000, %%eax \n" + "outl %%eax, %%dx \n" + "addb $2, %%dl \n" + "inw %%dx, %%ax \n" + : "=a" (eax), "=b"(ebx), "=c"(ecx), "=d"(edx) + : "a"(classIndex) + ); + + return eax; +} + +u32 VSA_msrRead(u32 msrAddr) +{ + unsigned eax, ebx, ecx, edx; + asm volatile ( + "movw $0x0AC1C, %%dx \n" + "movl $0x0FC530007, %%eax \n" + "outl %%eax, %%dx \n" + "addb $2, %%dl \n" + "inw %%dx, %%ax \n" + : "=a" (eax), "=b"(ebx), "=c"(ecx), "=d"(edx) + : "c"(msrAddr) + ); + + return eax; +} + void do_vsmbios(void) { - device_t dev; - unsigned long busdevfn; - unsigned int rom = 0; unsigned char *buf; - unsigned int size = SMM_SIZE*1024; int i; - unsigned long ilen, olen; - - printk_err("do_vsmbios\n"); - /* clear vsm bios data area */ - for (i = 0x400; i < 0x500; i++) { - *(unsigned char *) i = 0; - } - /* declare rom address here - keep any config data out of the way - * of core LXB stuff */ + printk_err( "do_vsmbios\n"); + /* Clear VSM BIOS data area. */ + for (i = 0x400; i < 0x500; i++) + *(volatile unsigned char *)i = 0; + /* set up cbfs and find the vsa file -- later */ +/* + init_archive(&archive); - /* this is the base of rom on the GX2 at present. At some point, this has to be - * much better parameterized - */ - //rom = 0xfff80000; - //rom = 0xfffc0000; - /* the VSA starts at the base of rom - 64 */ - rom = ((unsigned long) 0) - (CONFIG_ROM_SIZE + 64*1024); + if (find_file(&archive, "blob/vsa", &file)) + die("FATAL: NO VSA found!\n"); - buf = (unsigned char *) 0x60000; - olen = unrv2b((uint8_t *)rom, buf, &ilen); - printk_debug("buf ilen %d olen%d\n", ilen, olen); - printk_debug("buf %p *buf %d buf[256k] %d\n", - buf, buf[0], buf[SMM_SIZE*1024]); + if (process_file(&file, (void *)VSA2_BUFFER)) + die("FATAL: Processing /blob/vsa failed\n"); + */ + + buf = (unsigned char *)VSA2_BUFFER; printk_debug("buf[0x20] signature is %x:%x:%x:%x\n", - buf[0x20] ,buf[0x21] ,buf[0x22],buf[0x23]); - /* check for post code at start of vsainit.bin. If you don't see it, - don't bother. */ + buf[0x20], buf[0x21], buf[0x22], buf[0x23]); + /* Check for POST code at start of vsainit.bin. If you don't see it, + * don't bother. + */ if ((buf[0x20] != 0xb0) || (buf[0x21] != 0x10) || (buf[0x22] != 0xe6) || (buf[0x23] != 0x80)) { - printk_err("do_vsmbios: no vsainit.bin signature, skipping!\n"); - return; + die("FATAL: no vsainit.bin signature, skipping!\n"); } - //memcpy((void *) 0x60000, buf, size); - - //for (i = 0; i < 0x800000; i++) - // outb(0xaa, 0x80); - - /* ecx gets smm, edx gets sysm */ + /* ecx gets smm, edx gets sysm. */ printk_err("Call real_mode_switch_call_vsm\n"); - real_mode_switch_call_vsm(0x10000026, 0x10000028); +// real_mode_switch_call_vsm(MSR_GLIU0_SMM, MSR_GLIU0_SYSMEM); - /* restart timer 1 */ + /* Restart Timer 1. */ outb(0x56, 0x43); outb(0x12, 0x41); -} - -// we had hoped to avoid this. -// this is a stub IDT only. It's main purpose is to ignore calls -// to the BIOS. -// no longer. Dammit. We have to respond to these. -struct realidt { - unsigned short offset, cs; -}; - -// from a handy writeup that andrey found. - -// handler. -// There are some assumptions we can make here. -// First, the Top Of Stack (TOS) is located on the top of page zero. -// we can share this stack between real and protected mode. -// that simplifies a lot of things ... -// we'll just push all the registers on the stack as longwords, -// and pop to protected mode. -// second, since this only ever runs as part of coreboot, -// we know all the segment register values -- so we don't save any. -// keep the handler that calls things small. It can do a call to -// more complex code in coreboot itself. This helps a lot as we don't -// have to do address fixup in this little stub, and calls are absolute -// so the handler is relocatable. -void handler(void) -{ - __asm__ __volatile__ ( - " .code16 \n" - "idthandle: \n" - " pushal \n" - " movb $0, %al \n" - " ljmp $0, $callbiosint16\n" - "end_idthandle: \n" - " .code32 \n" - ); -} - -void debughandler(void) -{ - __asm__ __volatile__ ( - " .code16 \n" - "debughandle: \n" - " pushw %cx \n" - " movw $250, %cx \n" - "dbh1: \n" - " loop dbh1 \n" - " popw %cx \n" - " iret \n" - "end_debughandle: \n" - ".code32 \n" - ); -} - -// Calling conventions. The first C function is called with this stuff -// on the stack. They look like value parameters, but note that if you -// modify them they will go back to the INTx function modified. -// the C function will call the biosint function with these as -// REFERENCE parameters. In this way, we can easily get -// returns back to the INTx caller (i.e. vgabios) -void callbiosint(void) -{ - __asm__ __volatile__ ( - " .code16 \n" - "callbiosint16: \n" - " push %ds \n" - " push %es \n" - " push %fs \n" - " push %gs \n" - // clean up the int #. To save space we put it in the lower - // byte. But the top 24 bits are junk. - " andl $0xff, %eax\n" - // this push does two things: - // - put the INT # on the stack as a parameter - // - provides us with a temp for the %cr0 mods. - " pushl %eax \n" - " movb $0xbb, %al\n" - " outb %al, $0x80\n" - " movl %cr0, %eax\n" - " orl $0x00000001, %eax\n" /* PE = 1 */ - " movl %eax, %cr0\n" - /* Now that we are in protected mode jump to a 32 bit code segment. */ - " data32 ljmp $0x10, $biosprotect\n" - "biosprotect: \n" - " .code32 \n" - " movw $0x18, %ax \n" - " mov %ax, %ds \n" - " mov %ax, %es \n" - " mov %ax, %fs \n" - " mov %ax, %gs \n" - " mov %ax, %ss \n" - " lidt idtarg \n" - " call biosint \n" - // back to real mode ... - " ljmp $0x28, $__rms_16bit2\n" - "__rms_16bit2: \n" - " .code16 \n" - /* 16 bit code from here on... */ - /* Load the segment registers w/ properly configured segment - * descriptors. They will retain these configurations (limits, - * writability, etc.) once protected mode is turned off. */ - " mov $0x30, %ax \n" - " mov %ax, %ds \n" - " mov %ax, %es \n" - " mov %ax, %fs \n" - " mov %ax, %gs \n" - " mov %ax, %ss \n" - - /* Turn off protection (bit 0 in CR0) */ - " movl %cr0, %eax \n" - " andl $0xFFFFFFFE, %eax \n" - " movl %eax, %cr0 \n" - - /* Now really going into real mode */ - " ljmp $0, $__rms_real2 \n" - "__rms_real2: \n" - - /* Setup a stack - * FixME: where is esp? */ - /* no need for a fix here. The esp is shared from 32-bit and 16-bit mode. - * you have to hack on the ss, but the esp remains the same across - * modes. - */ - " mov $0x0, %ax \n" - " mov %ax, %ss \n" - - /* debugging for RGM */ - " mov $0x11, %al \n" - " outb %al, $0x80 \n" - - /* Load our 16 bit idt */ - " xor %ax, %ax \n" - " mov %ax, %ds \n" - " lidt __myidt \n" - - /* Dump zeros in the other segregs */ - " mov %ax, %es \n" - " mov %ax, %fs \n" - " mov %ax, %gs \n" - " mov $0x40, %ax \n" - " mov %ax, %ds \n" - - /* pop the INT # that you pushed earlier */ - " popl %eax \n" - " pop %gs \n" - " pop %fs \n" - " pop %es \n" - " pop %ds \n" - " popal \n" - " iret \n" - " .code32 \n" - ); -} - -enum { - PCIBIOS = 0x1a, - MEMSIZE = 0x12 -}; - -int pcibios(unsigned long *pedi, unsigned long *pesi, unsigned long *pebp, - unsigned long *pesp, unsigned long *pebx, unsigned long *pedx, - unsigned long *pecx, unsigned long *peax, unsigned long *pflags); - -int handleint21(unsigned long *pedi, unsigned long *pesi, unsigned long *pebp, - unsigned long *pesp, unsigned long *pebx, unsigned long *pedx, - unsigned long *pecx, unsigned long *peax, unsigned long *pflags - ); - -int biosint(unsigned long intnumber, - unsigned long gsfs, unsigned long dses, - unsigned long edi, unsigned long esi, - unsigned long ebp, unsigned long esp, - unsigned long ebx, unsigned long edx, - unsigned long ecx, unsigned long eax, - unsigned long cs_ip, unsigned short stackflags) -{ - unsigned long ip; - unsigned long cs; - unsigned long flags; - int ret = -1; - - ip = cs_ip & 0xffff; - cs = cs_ip >> 16; - flags = stackflags; - - printk_debug("biosint: INT# 0x%lx\n", intnumber); - printk_debug("biosint: eax 0x%lx ebx 0x%lx ecx 0x%lx edx 0x%lx\n", - eax, ebx, ecx, edx); - printk_debug("biosint: ebp 0x%lx esp 0x%lx edi 0x%lx esi 0x%lx\n", - ebp, esp, edi, esi); - printk_debug("biosint: ip 0x%x cs 0x%x flags 0x%x\n", - ip, cs, flags); - printk_debug("biosint: gs 0x%x fs 0x%x ds 0x%x es 0x%x\n", - gsfs >> 16, gsfs & 0xffff, dses >> 16, dses & 0xffff); - - // cases in a good compiler are just as good as your own tables. - switch (intnumber) { - case 0 ... 15: - // These are not BIOS service, but the CPU-generated exceptions - printk_info("biosint: Oops, exception %u\n", intnumber); - if (esp < 0x1000) { - printk_debug("Stack contents: "); - while (esp < 0x1000) { - printk_debug("0x%04x ", *(unsigned short *) esp); - esp += 2; - } - printk_debug("\n"); - } - printk_debug("biosint: Bailing out ... not now\n"); - // "longjmp" - //vga_exit(); - break; - - case PCIBIOS: - ret = pcibios( &edi, &esi, &ebp, &esp, - &ebx, &edx, &ecx, &eax, &flags); - break; - case MEMSIZE: - // who cares. - eax = 64 * 1024; - ret = 0; - break; - case 0x15: - ret=handleint21( &edi, &esi, &ebp, &esp, - &ebx, &edx, &ecx, &eax, &flags); - break; - default: - printk_info("BIOSINT: Unsupport int #0x%x\n", - intnumber); - break; - } - if (ret) - flags |= 1; // carry flags + /* Check that VSA is running OK. */ + if (VSA_vrRead(SIGNATURE) == VSA2_SIGNATURE) + printk_debug("do_vsmbios: VSA2 VR signature verified\n"); else - flags &= ~1; - stackflags = flags; - return ret; -} - - -void setup_realmode_idt(void) -{ - extern unsigned char idthandle, end_idthandle; - extern unsigned char debughandle, end_debughandle; - - int i; - struct realidt *idts = (struct realidt *) 0; - int codesize = &end_idthandle - &idthandle; - unsigned char *intbyte, *codeptr; - - // for each int, we create a customized little handler - // that just pushes %ax, puts the int # in %al, - // then calls the common interrupt handler. - // this necessitated because intel didn't know much about - // architecture when they did the 8086 (it shows) - // (hmm do they know anymore even now :-) - // obviously you can see I don't really care about memory - // efficiency. If I did I would probe back through the stack - // and get it that way. But that's really disgusting. - for (i = 0; i < 256; i++) { - idts[i].cs = 0; - codeptr = (char*) 4096 + i * codesize; - idts[i].offset = (unsigned) codeptr; - memcpy(codeptr, &idthandle, codesize); - intbyte = codeptr + 3; - *intbyte = i; - } - - // fixed entry points - - // VGA BIOSes tend to hardcode f000:f065 as the previous handler of - // int10. - // calling convention here is the same as INTs, we can reuse - // the int entry code. - codeptr = (char*) 0xff065; - memcpy(codeptr, &idthandle, codesize); - intbyte = codeptr + 3; - *intbyte = 0x42; /* int42 is the relocated int10 */ - - /* debug handler - useful to set a programmable delay between instructions if the - TF bit is set upon call to real mode */ - idts[1].cs = 0; - idts[1].offset = 16384; - memcpy(16384, &debughandle, &end_debughandle - &debughandle); + die("FATAL: VSA2 VR signature not valid, install failed!\n"); } - - -enum { - CHECK = 0xb001, - FINDDEV = 0xb102, - READCONFBYTE = 0xb108, - READCONFWORD = 0xb109, - READCONFDWORD = 0xb10a, - WRITECONFBYTE = 0xb10b, - WRITECONFWORD = 0xb10c, - WRITECONFDWORD = 0xb10d -}; - -// errors go in AH. Just set these up so that word assigns -// will work. KISS. -enum { - PCIBIOS_NODEV = 0x8600, - PCIBIOS_BADREG = 0x8700 -}; - -int -pcibios(unsigned long *pedi, unsigned long *pesi, unsigned long *pebp, - unsigned long *pesp, unsigned long *pebx, unsigned long *pedx, - unsigned long *pecx, unsigned long *peax, unsigned long *pflags) -{ - unsigned long edi = *pedi; - unsigned long esi = *pesi; - unsigned long ebp = *pebp; - unsigned long esp = *pesp; - unsigned long ebx = *pebx; - unsigned long edx = *pedx; - unsigned long ecx = *pecx; - unsigned long eax = *peax; - unsigned long flags = *pflags; - unsigned short func = (unsigned short) eax; - int retval = 0; - unsigned short devid, vendorid, devfn; - short devindex; /* Use short to get rid of gabage in upper half of 32-bit register */ - unsigned char bus; - device_t dev; - - switch(func) { - case CHECK: - *pedx = 0x4350; - *pecx = 0x2049; - retval = 0; - break; - case FINDDEV: - { - devid = *pecx; - vendorid = *pedx; - devindex = *pesi; - dev = 0; - while ((dev = dev_find_device(vendorid, devid, dev))) { - if (devindex <= 0) - break; - devindex--; - } - if (dev) { - unsigned short busdevfn; - *peax = 0; - // busnum is an unsigned char; - // devfn is an int, so we mask it off. - busdevfn = (dev->bus->secondary << 8) - | (dev->path.pci.devfn & 0xff); - printk_debug("0x%x: return 0x%x\n", func, busdevfn); - *pebx = busdevfn; - retval = 0; - } else { - *peax = PCIBIOS_NODEV; - retval = -1; - } - } - break; - case READCONFDWORD: - case READCONFWORD: - case READCONFBYTE: - case WRITECONFDWORD: - case WRITECONFWORD: - case WRITECONFBYTE: - { - unsigned long dword; - unsigned short word; - unsigned char byte; - unsigned char reg; - - devfn = *pebx & 0xff; - bus = *pebx >> 8; - reg = *pedi; - dev = dev_find_slot(bus, devfn); - if (! dev) { - printk_debug("0x%x: BAD DEVICE bus %d devfn 0x%x\n", func, bus, devfn); - // idiots. the pcibios guys assumed you'd never pass a bad bus/devfn! - *peax = PCIBIOS_BADREG; - retval = -1; - } - switch(func) { - case READCONFBYTE: - byte = pci_read_config8(dev, reg); - *pecx = byte; - break; - case READCONFWORD: - word = pci_read_config16(dev, reg); - *pecx = word; - break; - case READCONFDWORD: - dword = pci_read_config32(dev, reg); - *pecx = dword; - break; - case WRITECONFBYTE: - byte = *pecx; - pci_write_config8(dev, reg, byte); - break; - case WRITECONFWORD: - word = *pecx; - pci_write_config16(dev, reg, word); - break; - case WRITECONFDWORD: - dword = *pecx; - pci_write_config32(dev, reg, dword); - break; - } - - if (retval) - retval = PCIBIOS_BADREG; - printk_debug("0x%x: bus %d devfn 0x%x reg 0x%x val 0x%lx\n", - func, bus, devfn, reg, *pecx); - *peax = 0; - retval = 0; - } - break; - default: - printk_err("UNSUPPORTED PCIBIOS FUNCTION 0x%x\n", func); - break; - } - - return retval; -} - -int handleint21(unsigned long *edi, unsigned long *esi, unsigned long *ebp, - unsigned long *esp, unsigned long *ebx, unsigned long *edx, - unsigned long *ecx, unsigned long *eax, unsigned long *flags) -{ - int res=-1; - printk_debug("handleint21, eax 0x%x\n", *eax); - switch(*eax&0xffff) - { - case 0x5f19: - break; - case 0x5f18: - *eax=0x5f; - *ebx=0x545; // MCLK = 133, 32M frame buffer, 256 M main memory - *ecx=0x060; - res=0; - break; - case 0x5f00: - *eax = 0x8600; - break; - case 0x5f01: - *eax = 0x5f; - *ecx = (*ecx & 0xffffff00 ) | 2; // panel type = 2 = 1024 * 768 - res = 0; - break; - case 0x5f02: - *eax=0x5f; - *ebx= (*ebx & 0xffff0000) | 2; - *ecx= (*ecx & 0xffff0000) | 0x401; // PAL + crt only - *edx= (*edx & 0xffff0000) | 0; // TV Layout - default - res=0; - break; - case 0x5f0f: - *eax=0x860f; - break; - case 0xBEA7: - *eax=33; - break; - case 0xBEA4: - *eax=333; - break; - } - return res; -} Added: trunk/coreboot-v2/src/northbridge/amd/gx2/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/gx2/Kconfig (rev 0) +++ trunk/coreboot-v2/src/northbridge/amd/gx2/Kconfig 2009-08-28 14:46:59 UTC (rev 4611) @@ -0,0 +1,27 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2007-2009 coresystems GmbH +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +config NORTHBRIDGE_AMD_GX2 + bool + default n + +config HAVE_HIGH_TABLES + bool + default y + Added: trunk/coreboot-v2/src/northbridge/amd/gx2/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/gx2/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/northbridge/amd/gx2/Makefile.inc 2009-08-28 14:46:59 UTC (rev 4611) @@ -0,0 +1,4 @@ +driver-y += northbridge.o +obj-y += northbridgeinit.o +obj-y += chipsetinit.o +obj-y += grphinit.o Modified: trunk/coreboot-v2/src/northbridge/amd/gx2/northbridge.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/gx2/northbridge.c 2009-08-28 14:40:04 UTC (rev 4610) +++ trunk/coreboot-v2/src/northbridge/amd/gx2/northbridge.c 2009-08-28 14:46:59 UTC (rev 4611) @@ -486,7 +486,6 @@ printk_debug("gx2 north: enable_dev\n"); void northbridgeinit(void); void chipsetinit(struct northbridge_amd_gx2_config *nb); - void setup_realmode_idt(void); void do_vsmbios(void); /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { @@ -499,8 +498,6 @@ cpubug(); chipsetinit(nb); setup_gx2(); - /* do this here for now -- this chip really breaks our device model */ - setup_realmode_idt(); do_vsmbios(); graphics_init(); dev->ops = &pci_domain_ops; Added: trunk/coreboot-v2/src/southbridge/amd/cs5536/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/cs5536/Kconfig (rev 0) +++ trunk/coreboot-v2/src/southbridge/amd/cs5536/Kconfig 2009-08-28 14:46:59 UTC (rev 4611) @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008-2009 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config SOUTHBRIDGE_AMD_CS5536 + bool + default n + Added: trunk/coreboot-v2/src/southbridge/amd/cs5536/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/cs5536/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/southbridge/amd/cs5536/Makefile.inc 2009-08-28 14:46:59 UTC (rev 4611) @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007 Advanced Micro Devices, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License version 2 as +## published by the Free Software Foundation. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +driver-y += cs5536.o +driver-y += cs5536_ide.o +driver-y += cs5536_pirq.o

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