coreboot August 2009

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[v2] r4620 - trunk/util/inteltool
by svn＠coreboot.org 29 Aug '09

29 Aug '09

Author: stepan Date: 2009-08-29 17:45:43 +0200 (Sat, 29 Aug 2009) New Revision: 4620 Modified: trunk/util/inteltool/inteltool.c trunk/util/inteltool/inteltool.h trunk/util/inteltool/memory.c trunk/util/inteltool/pcie.c trunk/util/inteltool/powermgt.c Log: add i810 and ich0 Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/util/inteltool/inteltool.c =================================================================== --- trunk/util/inteltool/inteltool.c 2009-08-29 03:00:51 UTC (rev 4619) +++ trunk/util/inteltool/inteltool.c 2009-08-29 15:45:43 UTC (rev 4620) @@ -29,6 +29,8 @@ uint16_t vendor_id, device_id; char *name; } supported_chips_list[] = { + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810, "i810" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810DC, "i810-DC100" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845, "i845" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945P, "i945P" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "i945GM" }, Modified: trunk/util/inteltool/inteltool.h =================================================================== --- trunk/util/inteltool/inteltool.h 2009-08-29 03:00:51 UTC (rev 4619) +++ trunk/util/inteltool/inteltool.h 2009-08-29 15:45:43 UTC (rev 4620) @@ -44,6 +44,8 @@ #define PCI_DEVICE_ID_INTEL_ICH8M 0x2815 #define PCI_DEVICE_ID_INTEL_ICH10R 0x3a16 +#define PCI_DEVICE_ID_INTEL_82810 0x7120 +#define PCI_DEVICE_ID_INTEL_82810DC 0x7122 #define PCI_DEVICE_ID_INTEL_82845 0x1a30 #define PCI_DEVICE_ID_INTEL_82945P 0x2770 #define PCI_DEVICE_ID_INTEL_82945GM 0x27a0 Modified: trunk/util/inteltool/memory.c =================================================================== --- trunk/util/inteltool/memory.c 2009-08-29 03:00:51 UTC (rev 4619) +++ trunk/util/inteltool/memory.c 2009-08-29 15:45:43 UTC (rev 4620) @@ -43,7 +43,8 @@ mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe; mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; break; - case 0x1234: // Dummy for non-existent functionality + case PCI_DEVICE_ID_INTEL_82810: + case PCI_DEVICE_ID_INTEL_82810DC: printf("This northbrigde does not have MCHBAR.\n"); return 1; default: Modified: trunk/util/inteltool/pcie.c =================================================================== --- trunk/util/inteltool/pcie.c 2009-08-29 03:00:51 UTC (rev 4619) +++ trunk/util/inteltool/pcie.c 2009-08-29 15:45:43 UTC (rev 4620) @@ -42,7 +42,8 @@ epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32; break; - case 0x1234: // Dummy for non-existent functionality + case PCI_DEVICE_ID_INTEL_82810: + case PCI_DEVICE_ID_INTEL_82810DC: printf("This northbrigde does not have EPBAR.\n"); return 1; default: @@ -88,7 +89,8 @@ dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe; dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32; break; - case 0x1234: // Dummy for non-existent functionality + case PCI_DEVICE_ID_INTEL_82810: + case PCI_DEVICE_ID_INTEL_82810DC: printf("This northbrigde does not have DMIBAR.\n"); return 1; default: @@ -136,7 +138,8 @@ pciexbar_reg = pci_read_long(nb, 0x60); pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32; break; - case 0x1234: // Dummy for non-existent functionality + case PCI_DEVICE_ID_INTEL_82810: + case PCI_DEVICE_ID_INTEL_82810DC: printf("Error: This northbrigde does not have PCIEXBAR.\n"); return 1; default: Modified: trunk/util/inteltool/powermgt.c =================================================================== --- trunk/util/inteltool/powermgt.c 2009-08-29 03:00:51 UTC (rev 4619) +++ trunk/util/inteltool/powermgt.c 2009-08-29 15:45:43 UTC (rev 4620) @@ -145,6 +145,64 @@ { 0x7c, 4, "RESERVED" }, }; +static const io_register_t ich0_pm_registers[] = { + { 0x00, 2, "PM1_STS" }, + { 0x02, 2, "PM1_EN" }, + { 0x04, 4, "PM1_CNT" }, + { 0x08, 4, "PM1_TMR" }, + { 0x0c, 4, "RESERVED" }, + { 0x10, 4, "PROC_CNT" }, +#if DANGEROUS_REGISTERS + /* This register returns 0 on read, but reading it may cause + * the system to enter C2 state, which might hang the system. + */ + { 0x14, 1, "LV2" }, + { 0x15, 1, "RESERVED" }, + { 0x16, 2, "RESERVED" }, +#endif + { 0x18, 4, "RESERVED" }, + { 0x1c, 4, "RESERVED" }, + { 0x20, 4, "RESERVED" }, + { 0x24, 4, "RESERVED" }, + { 0x28, 4, "GPE0_STS" }, + { 0x2C, 4, "GPE0_EN" }, + { 0x30, 2, "SMI_EN" }, + { 0x32, 2, "RESERVED" }, + { 0x34, 2, "SMI_STS" }, + { 0x36, 2, "RESERVED" }, + { 0x38, 4, "RESERVED" }, + { 0x3c, 4, "RESERVED" }, + { 0x40, 2, "IOMON_STS_EN" }, + { 0x42, 2, "RESERVED" }, + { 0x44, 2, "DEVACT_STS" }, + { 0x46, 2, "RESERVED" }, + { 0x48, 4, "RESERVED" }, + { 0x4c, 2, "BUS_ADDR_TRACK" }, + { 0x4e, 1, "BUS_CYC_TRACK" }, + { 0x4f, 1, "RESERVED" }, + { 0x50, 4, "RESERVED" }, + { 0x54, 4, "RESERVED" }, + { 0x58, 4, "RESERVED" }, + { 0x5c, 4, "RESERVED" }, + /* Here start the TCO registers */ + { 0x60, 1, "TCO_RLD" }, + { 0x61, 1, "TCO_TMR" }, + { 0x62, 1, "TCO_DAT_IN" }, + { 0x63, 1, "TCO_DAT_OUT" }, + { 0x64, 2, "TCO1_STS" }, + { 0x66, 2, "TCO2_STS" }, + { 0x68, 2, "TCO1_CNT" }, + { 0x6a, 2, "TCO2_CNT" }, + { 0x6c, 1, "TCO_MESSAGE1" }, + { 0x6d, 1, "TCO_MESSAGE2" }, + { 0x6e, 1, "TCO_WDSTATUS" }, + { 0x6f, 1, "RESERVED" }, + { 0x70, 4, "RESERVED" }, + { 0x74, 4, "RESERVED" }, + { 0x78, 4, "RESERVED" }, + { 0x7c, 4, "RESERVED" }, +}; + int print_pmbase(struct pci_dev *sb) { int i, size; @@ -167,6 +225,11 @@ pm_registers = ich8_pm_registers; size = ARRAY_SIZE(ich8_pm_registers); break; + case PCI_DEVICE_ID_INTEL_ICH0: + pmbase = pci_read_word(sb, 0x40) & 0xfffc; + pm_registers = ich0_pm_registers; + size = ARRAY_SIZE(ich0_pm_registers); + break; case 0x1234: // Dummy for non-existent functionality printf("This southbridge does not have PMBASE.\n"); return 1;

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[v2] r4619 - trunk/coreboot-v2/src/cpu/x86
by svn＠coreboot.org 29 Aug '09

29 Aug '09

Author: rminnich Date: 2009-08-29 05:00:51 +0200 (Sat, 29 Aug 2009) New Revision: 4619 Modified: trunk/coreboot-v2/src/cpu/x86/Kconfig Log: File I missed committing. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: trunk/coreboot-v2/src/cpu/x86/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/x86/Kconfig 2009-08-29 02:59:35 UTC (rev 4618) +++ trunk/coreboot-v2/src/cpu/x86/Kconfig 2009-08-29 03:00:51 UTC (rev 4619) @@ -2,6 +2,14 @@ bool default y +config UDELAY_TSC + bool + default n + +config TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 + bool + default n + config XIP_ROM_BASE hex default 0xfffe0000

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[v2] r4618 - in trunk/coreboot-v2/src: arch/i386 cpu/amd cpu/x86/tsc mainboard/amd/rumba northbridge/amd southbridge/amd
by svn＠coreboot.org 29 Aug '09

29 Aug '09

Author: rminnich Date: 2009-08-29 04:59:35 +0200 (Sat, 29 Aug 2009) New Revision: 4618 Modified: trunk/coreboot-v2/src/arch/i386/Kconfig trunk/coreboot-v2/src/cpu/amd/Kconfig trunk/coreboot-v2/src/cpu/amd/Makefile.inc trunk/coreboot-v2/src/cpu/x86/tsc/Makefile.inc trunk/coreboot-v2/src/mainboard/amd/rumba/Kconfig trunk/coreboot-v2/src/northbridge/amd/Kconfig trunk/coreboot-v2/src/southbridge/amd/Kconfig Log: This is the final set of changes to allow rumba to build. Rumba is not tested. I also addressed questions raised by Uwe: TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 UDELAY_TSC Are now defined as booleans in src/cpu/x86/Kconfig and can be selected in the mainboard Kconfig. The remaining question of Uwe's is a deeper problem: --- We'll have to check if this works. From a quick glance the Rumba does not have the mmx related lines (which _are_ in Makefile.romccboard.inc, though): crt0-y += ../../../../src/cpu/x86/fpu/enable_fpu.inc crt0-y += ../../../../src/cpu/x86/mmx/enable_mmx.inc crt0-y += auto.inc crt0-y += ../../../../src/cpu/x86/mmx/disable_mmx.inc --- We're going to need a whole variant of this standard mainboard OR we're going to have to make (some) of the unconditional includes above conditional. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/arch/i386/Kconfig =================================================================== --- trunk/coreboot-v2/src/arch/i386/Kconfig 2009-08-29 02:47:57 UTC (rev 4617) +++ trunk/coreboot-v2/src/arch/i386/Kconfig 2009-08-29 02:59:35 UTC (rev 4618) @@ -4,6 +4,14 @@ This option is used to set the architecture of a mainboard. It is usually set in mainboard/*/Kconfig. +config AP_IN_SIPI_WAIT + bool + default n + depends on ARCH_X86 + help + This is an SMP option. It relates to starting up APs. + It is usually set in mainboard/*/Kconfig. + config ARCH string default i386 Modified: trunk/coreboot-v2/src/cpu/amd/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/amd/Kconfig 2009-08-29 02:47:57 UTC (rev 4617) +++ trunk/coreboot-v2/src/cpu/amd/Kconfig 2009-08-29 02:59:35 UTC (rev 4618) @@ -8,3 +8,4 @@ source src/cpu/amd/socket_S1G1/Kconfig source src/cpu/amd/model_fxx/Kconfig +source src/cpu/amd/model_gx2/Kconfig Modified: trunk/coreboot-v2/src/cpu/amd/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/amd/Makefile.inc 2009-08-29 02:47:57 UTC (rev 4617) +++ trunk/coreboot-v2/src/cpu/amd/Makefile.inc 2009-08-29 02:59:35 UTC (rev 4618) @@ -1,4 +1,5 @@ subdirs-$(CONFIG_CPU_AMD_SOCKET_F) += socket_F subdirs-$(CONFIG_CPU_AMD_SOCKET_940) += socket_940 subdirs-$(CONFIG_CPU_AMD_SOCKET_AM2) += socket_AM2 +subdirs-$(CONFIG_CPU_AMD_GX2) += model_gx2 subdirs-$(CONFIG_CPU_AMD_SOCKET_S1G1) += socket_S1G1 Modified: trunk/coreboot-v2/src/cpu/x86/tsc/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/cpu/x86/tsc/Makefile.inc 2009-08-29 02:47:57 UTC (rev 4617) +++ trunk/coreboot-v2/src/cpu/x86/tsc/Makefile.inc 2009-08-29 02:59:35 UTC (rev 4618) @@ -1,7 +1,2 @@ obj-y += delay_tsc.o -# default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=0 -# if CONFIG_UDELAY_TSC -# default CONFIG_HAVE_INIT_TIMER=1 -# object delay_tsc.o -# end Modified: trunk/coreboot-v2/src/mainboard/amd/rumba/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/rumba/Kconfig 2009-08-29 02:47:57 UTC (rev 4617) +++ trunk/coreboot-v2/src/mainboard/amd/rumba/Kconfig 2009-08-29 02:59:35 UTC (rev 4618) @@ -26,6 +26,7 @@ select NORTHBRIDGE_AMD_GX2 select SOUTHBRIDGE_AMD_CS5536 select UDELAY_TSC + select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 select HAVE_PIRQ_TABLE help AMD Rumba mainboard. @@ -54,9 +55,3 @@ int default 0 depends on BOARD_AMD_RUMBA - - -config TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 - int - default 0 - depends on BOARD_AMD_RUMBA Modified: trunk/coreboot-v2/src/northbridge/amd/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/Kconfig 2009-08-29 02:47:57 UTC (rev 4617) +++ trunk/coreboot-v2/src/northbridge/amd/Kconfig 2009-08-29 02:59:35 UTC (rev 4618) @@ -1,7 +1,8 @@ +source src/northbridge/amd/amdk8/Kconfig +source src/northbridge/amd/gx2/Kconfig + #source src/northbridge/amd/amdfam10/Kconfig #source src/northbridge/amd/amdht/Kconfig -source src/northbridge/amd/amdk8/Kconfig #source src/northbridge/amd/amdmct/Kconfig #source src/northbridge/amd/gx1/Kconfig -#source src/northbridge/amd/gx2/Kconfig #source src/northbridge/amd/lx/Kconfig Modified: trunk/coreboot-v2/src/southbridge/amd/Kconfig =================================================================== --- trunk/coreboot-v2/src/southbridge/amd/Kconfig 2009-08-29 02:47:57 UTC (rev 4617) +++ trunk/coreboot-v2/src/southbridge/amd/Kconfig 2009-08-29 02:59:35 UTC (rev 4618) @@ -1,10 +1,10 @@ source src/southbridge/amd/amd8111/Kconfig source src/southbridge/amd/amd8131/Kconfig +source src/southbridge/amd/cs5536/Kconfig #source src/southbridge/amd/amd8131-disable/Kconfig #source src/southbridge/amd/amd8132/Kconfig #source src/southbridge/amd/amd8151/Kconfig #source src/southbridge/amd/cs5530/Kconfig #source src/southbridge/amd/cs5535/Kconfig -#source src/southbridge/amd/cs5536/Kconfig source src/southbridge/amd/rs690/Kconfig source src/southbridge/amd/sb600/Kconfig

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patch: amd mainboard Kconfig cleanup; add rumba support
by ron minnich 29 Aug '09

29 Aug '09

attached.requires my earlier gx2 patches to work. ron

4 5

[v2] r4617 - in trunk/coreboot-v2/src/mainboard/amd: . rumba serengeti_cheetah
by svn＠coreboot.org 29 Aug '09

29 Aug '09

Author: rminnich Date: 2009-08-29 04:47:57 +0200 (Sat, 29 Aug 2009) New Revision: 4617 Added: trunk/coreboot-v2/src/mainboard/amd/rumba/Kconfig trunk/coreboot-v2/src/mainboard/amd/rumba/Makefile.inc Modified: trunk/coreboot-v2/src/mainboard/amd/Kconfig trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Kconfig Log: Set the mainboard/amd directory up to support more than one. remove Config variables now defined elsewhere. add rumba Kconfig and Makefile.inc rumba won't build until my earlier patches are acked. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/mainboard/amd/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/Kconfig 2009-08-29 02:44:08 UTC (rev 4616) +++ trunk/coreboot-v2/src/mainboard/amd/Kconfig 2009-08-29 02:47:57 UTC (rev 4617) @@ -1 +1,9 @@ -source "src/mainboard/amd/serengeti_cheetah/Kconfig" \ No newline at end of file +choice + prompt "Mainboard model" + depends on VENDOR_AMD + +source "src/mainboard/amd/serengeti_cheetah/Kconfig" +source "src/mainboard/amd/rumba/Kconfig" + +endchoice + Added: trunk/coreboot-v2/src/mainboard/amd/rumba/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/rumba/Kconfig (rev 0) +++ trunk/coreboot-v2/src/mainboard/amd/rumba/Kconfig 2009-08-29 02:47:57 UTC (rev 4617) @@ -0,0 +1,62 @@ + + +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## +config BOARD_AMD_RUMBA + bool "Rumba" + select ARCH_X86 + select CPU_AMD_GX2 + select NORTHBRIDGE_AMD_GX2 + select SOUTHBRIDGE_AMD_CS5536 + select UDELAY_TSC + select HAVE_PIRQ_TABLE + help + AMD Rumba mainboard. + +config MAINBOARD_DIR + string + default amd/rumba + depends on BOARD_AMD_RUMBA + +config MAINBOARD_PART_NUMBER + string + default "Rumba" + depends on BOARD_AMD_RUMBA + +config HAVE_OPTION_TABLE + bool + default n + depends on BOARD_AMD_RUMBA + +config IRQ_SLOT_COUNT + int + default 2 + depends on BOARD_AMD_RUMBA + +config USE_INIT + int + default 0 + depends on BOARD_AMD_RUMBA + + +config TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 + int + default 0 + depends on BOARD_AMD_RUMBA Added: trunk/coreboot-v2/src/mainboard/amd/rumba/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/rumba/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/mainboard/amd/rumba/Makefile.inc 2009-08-29 02:47:57 UTC (rev 4617) @@ -0,0 +1 @@ +include $(src)/mainboard/Makefile.romccboard.inc Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Kconfig =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Kconfig 2009-08-29 02:44:08 UTC (rev 4616) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Kconfig 2009-08-29 02:47:57 UTC (rev 4617) @@ -1,7 +1,3 @@ -choice - prompt "Mainboard model" - depends on VENDOR_AMD - config BOARD_AMD_SERENGETI_CHEETAH bool "Serengeti Cheetah" select ARCH_X86 @@ -17,7 +13,6 @@ select USE_DCACHE_RAM help AMD Serengeti Cheetah mainboard. -endchoice config MAINBOARD_DIR string @@ -74,10 +69,6 @@ default "Serengeti-Cheetah" depends on BOARD_AMD_SERENGETI_CHEETAH -config PCI_64BIT_PREF_MEM - int - default 0 - depends on BOARD_AMD_SERENGETI_CHEETAH config USE_FAILOVER_IMAGE int

1 0

patch: beginnings of support for geode gx2, v2, and Kconfig
by ron minnich 29 Aug '09

29 Aug '09

attached. ron

3 4

[v2] r4616 - in trunk/coreboot-v2/src: cpu/amd/model_gx2 northbridge/amd/gx2
by svn＠coreboot.org 29 Aug '09

29 Aug '09

Author: rminnich Date: 2009-08-29 04:44:08 +0200 (Sat, 29 Aug 2009) New Revision: 4616 Modified: trunk/coreboot-v2/src/cpu/amd/model_gx2/Kconfig trunk/coreboot-v2/src/northbridge/amd/gx2/Kconfig Log: Fixes per Uwe's comments. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: trunk/coreboot-v2/src/cpu/amd/model_gx2/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_gx2/Kconfig 2009-08-28 20:42:21 UTC (rev 4615) +++ trunk/coreboot-v2/src/cpu/amd/model_gx2/Kconfig 2009-08-29 02:44:08 UTC (rev 4616) @@ -1,3 +1,3 @@ config CPU_AMD_GX2 bool - default false + default n Modified: trunk/coreboot-v2/src/northbridge/amd/gx2/Kconfig =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/gx2/Kconfig 2009-08-28 20:42:21 UTC (rev 4615) +++ trunk/coreboot-v2/src/northbridge/amd/gx2/Kconfig 2009-08-29 02:44:08 UTC (rev 4616) @@ -21,7 +21,3 @@ bool default n -config HAVE_HIGH_TABLES - bool - default y -

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[PATCH] VGA and external superIO support for Intel Trxuton (EP80579)
by Arnaud Maye 28 Aug '09

28 Aug '09

Hello Gents, This patch tries to improve the already existing Truxton board support package. The VGA card (Matrox G550e) shipped along with the Truxton board is supported as well as the external superIO controller chip ( SCH5027D ). A dedicated driver for the PCIe portA is included. See the patch below for more informations. Thank you, Arnaud * ** * This patch adds VGA and PS/2 Keyboard/mouse support to the already existing intel truxton (ep80579) dev board. This patch tries to improve the pcie portA configuration. The Matrox G550e PCIe gfx card shipped along with the dev board is supported. Patch details: The LPC interface has SERIRQ enabled (in order to receive legacy IRQ1/12 from the superIO controller. Added SCH5027D support to the generic smscsuperio driver. Modified config.lb to support the external SCH5027D superIO controller. Modified devicetree.cb to reflect actual device tree. Coreboot does not run at 0x4000 anymore but 0x00100000 instead. Use CONFIG_LB_MEM_TOPK to allow coreboot to run 0x00100000. CONFIG_CONSOLE_VGA is enabled. Added an ep80579 pcie_porta module (pciexp_porta_ep80579.c). The ep80579'smm interface is not in control of the VGA legacy memory range anymore. The default payload is seabios from now on. Signed-off-by: Arnaud Maye <arnaud.maye(a)4dsp.com> Index: src/southbridge/intel/i3100/i3100_early_lpc.c =================================================================== --- src/southbridge/intel/i3100/i3100_early_lpc.c (revision 4605) +++ src/southbridge/intel/i3100/i3100_early_lpc.c (working copy) @@ -25,6 +25,9 @@ /* Enable decoding of I/O locations for SuperIO devices */ pci_write_config16(dev, 0x80, 0x0010); pci_write_config16(dev, 0x82, 0x340f); + + /* Enable the SERIRQs (start pulse width is 8 clock cycles) */ + pci_write_config8(dev, 0x64, 0xD2); } static void i3100_halt_tco_timer(void) Index: src/superio/smsc/smscsuperio/superio.c =================================================================== --- src/superio/smsc/smscsuperio/superio.c (revision 4605) +++ src/superio/smsc/smscsuperio/superio.c (working copy) @@ -60,6 +60,7 @@ #define DME1737 0x78 #define SCH3112 0x7c #define SCH5307 0x81 /* Rebranded LPC47B397(?) */ +#define SCH5027D 0x89 /* Register defines */ #define DEVICE_ID_REG 0x20 /* Device ID register */ @@ -135,6 +136,7 @@ {DME1737, {0, 3, 4, 5, -1, 7, -1, -1, -1, -1, -1, -1, 10, -1, -1}}, {SCH3112, {0, 3, 4, 5, -1, 7, -1, -1, -1, -1, -1, -1, 10, -1, -1}}, {SCH5307, {0, 3, 4, 5, -1, 7, -1, -1, 8, -1, -1, -1, 10, -1, -1}}, + {SCH5027D, {0, 3, 4, 5, -1, 7, -1, -1, -1, -1, -1, -1, 10, -1, 11}}, }; /** Index: src/mainboard/intel/truxton/Config.lb =================================================================== --- src/mainboard/intel/truxton/Config.lb (revision 4605) +++ src/mainboard/intel/truxton/Config.lb (working copy) @@ -143,6 +143,19 @@ io 0x60 = 0x2f8 irq 0x70 = 3 end + end + chip superio/smsc/smscsuperio + device pnp 2e.0 off end + device pnp 2e.3 off end + device pnp 2e.4 off end + device pnp 2e.5 off end + device pnp 2e.7 on # PS/2 keyboard / mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 2e.a off end end end device pci 1f.2 on end # SATA Index: src/mainboard/intel/truxton/devicetree.cb =================================================================== --- src/mainboard/intel/truxton/devicetree.cb (revision 4605) +++ src/mainboard/intel/truxton/devicetree.cb (working copy) @@ -26,6 +26,19 @@ io 0x60 = 0x2f8 irq 0x70 = 3 end + end + chip superio/smsc/smscsuperio + device pnp 2e.0 off end + device pnp 2e.3 off end + device pnp 2e.4 off end + device pnp 2e.5 off end + device pnp 2e.7 on # PS/2 keyboard / mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 2e.a off end end end device pci 1f.2 on end # SATA Index: src/mainboard/intel/truxton/Options.lb =================================================================== --- src/mainboard/intel/truxton/Options.lb (revision 4605) +++ src/mainboard/intel/truxton/Options.lb (working copy) @@ -37,6 +37,7 @@ uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA +uses CONFIG_LB_MEM_TOPK uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE @@ -67,6 +68,7 @@ uses HOSTCC uses CONFIG_CROSS_COMPILE uses CONFIG_OBJCOPY +uses CONFIG_CONSOLE_VGA ### @@ -155,9 +157,14 @@ ## ## coreboot C code runs at this location in RAM ## -default CONFIG_RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00100000 ## +## in order to have coreboot running at 0x100000, TOPK has to be set +## +default CONFIG_LB_MEM_TOPK = 2*1024*1024 + +## ## Load the payload from the ROM ## default CONFIG_ROM_PAYLOAD=1 @@ -202,6 +209,9 @@ # This defaults to 8 data bits, 1 stop bit, and no parity default CONFIG_TTYS0_LCS=0x3 +# Enable the VGA console. +default CONFIG_CONSOLE_VGA=1 + ## ### Select the coreboot loglevel ## Index: src/northbridge/intel/i3100/pciexp_porta_ep80579.c =================================================================== --- src/northbridge/intel/i3100/pciexp_porta_ep80579.c (revision 0) +++ src/northbridge/intel/i3100/pciexp_porta_ep80579.c (revision 0) @@ -0,0 +1,112 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 4DSP Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* This code is based on src/northbridge/intel/i3100/pciexp_porta.c */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <device/pciexp.h> +#include <arch/io.h> +#include "chip.h" +#include <part/hard_reset.h> + +typedef struct northbridge_intel_i3100_config config_t; + +static void pcie_init(struct device *dev) +{ + config_t *config; + u16 val; + + /* Get the chip configuration */ + config = dev->chip_info; + + if(config->intrline) { + pci_write_config32(dev, 0x3c, config->intrline); + } + + printk_spew("configure PCIe port as \"Slot Implemented\"\n"); + val = pci_read_config16(dev, 0x66); + val &= ~(1<<8); + val |= 1<<8; + pci_write_config16(dev, 0x66, val); + + /* Todo configure the PCIe bootstrap mode (covered by Intel NDA) */ +} + + +static void pcie_bus_enable_resources(struct device *dev) +{ + u8 val8; + if (dev->link[0].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { + printk_spew("Enable VGA IO/MEM forwarding on PCIe port\n"); + pci_write_config8(dev, PCI_BRIDGE_CONTROL, 8); + + dev->command |= PCI_COMMAND_IO; + dev->command |= PCI_COMMAND_MEMORY; + } + pci_dev_enable_resources(dev); + enable_childrens_resources(dev); +} + + +static unsigned int pcie_scan_bridge(struct device *dev, unsigned int max) +{ + u16 val; + u16 ctl; + int flag = 0; + do { + val = pci_read_config16(dev, 0x76); + printk_debug("pcie porta 0x76: %02x\n", val); + if ((val & (1<<11)) && (!flag)) { /* training error */ + ctl = pci_read_config16(dev, 0x74); + pci_write_config16(dev, 0x74, (ctl | (1<<5))); + val = pci_read_config16(dev, 0x76); + printk_debug("pcie porta reset 0x76: %02x\n", val); + flag=1; + hard_reset(); + } + } while (val & (3<<10)); + return pciexp_scan_bridge(dev, max); +} + +static struct device_operations pcie_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pcie_bus_enable_resources, + .init = pcie_init, + .scan_bus = pcie_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = 0, +}; + +static struct pci_driver pci_driver_0 __pci_driver = { + .ops = &pcie_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_EP80579_PCIE_PA0, +}; + +static struct pci_driver pci_driver_1 __pci_driver = { + .ops = &pcie_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_EP80579_PCIE_PA1, +}; Index: src/northbridge/intel/i3100/Config.lb =================================================================== --- src/northbridge/intel/i3100/Config.lb (revision 4605) +++ src/northbridge/intel/i3100/Config.lb (working copy) @@ -23,5 +23,6 @@ driver northbridge.o driver pciexp_porta.o +driver pciexp_porta_ep80579.o default CONFIG_HAVE_HIGH_TABLES=1 Index: src/northbridge/intel/i3100/raminit_ep80579.c =================================================================== --- src/northbridge/intel/i3100/raminit_ep80579.c (revision 4605) +++ src/northbridge/intel/i3100/raminit_ep80579.c (working copy) @@ -31,7 +31,7 @@ { static const u32 register_values[] = { PCI_ADDR(0, 0x00, 0, CKDIS), 0xffff0000, 0x0000ffff, - PCI_ADDR(0, 0x00, 0, DEVPRES), 0x00000000, 0x07420801 | DEVPRES_CONFIG, + PCI_ADDR(0, 0x00, 0, DEVPRES), 0x00000000, 0x07420001 | DEVPRES_CONFIG, PCI_ADDR(0, 0x00, 0, PAM-1), 0xcccccc7f, 0x33333000, PCI_ADDR(0, 0x00, 0, PAM+3), 0xcccccccc, 0x33333333, PCI_ADDR(0, 0x00, 0, DEVPRES1), 0xffffffff, 0x0040003a, Index: targets/intel/truxton/Config.lb =================================================================== --- targets/intel/truxton/Config.lb (revision 4605) +++ targets/intel/truxton/Config.lb (working copy) @@ -34,7 +34,7 @@ romimage "fallback" option CONFIG_USE_FALLBACK_IMAGE=1 - payload /tmp/filo.elf + payload /tmp/seabios.elf end buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"

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[v2] r4615 - in trunk/coreboot-v2: src/mainboard/intel/truxton src/northbridge/intel/i3100 src/southbridge/intel/i3100 src/superio/smsc/smscsuperio targets/intel/truxton
by svn＠coreboot.org 28 Aug '09

28 Aug '09

Author: myles Date: 2009-08-28 22:42:21 +0200 (Fri, 28 Aug 2009) New Revision: 4615 Added: trunk/coreboot-v2/src/northbridge/intel/i3100/pciexp_porta_ep80579.c Modified: trunk/coreboot-v2/src/mainboard/intel/truxton/Config.lb trunk/coreboot-v2/src/mainboard/intel/truxton/Options.lb trunk/coreboot-v2/src/mainboard/intel/truxton/devicetree.cb trunk/coreboot-v2/src/northbridge/intel/i3100/Config.lb trunk/coreboot-v2/src/northbridge/intel/i3100/raminit_ep80579.c trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_early_lpc.c trunk/coreboot-v2/src/superio/smsc/smscsuperio/superio.c trunk/coreboot-v2/targets/intel/truxton/Config.lb Log: This patch adds VGA and PS/2 Keyboard/mouse support to the already existing intel truxton (ep80579) dev board. This patch tries to improve the pcie portA configuration. The Matrox G550e PCIe gfx card shipped along with the dev board is supported. Signed-off-by: Arnaud Maye <arnaud.maye(a)4dsp.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/mainboard/intel/truxton/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/truxton/Config.lb 2009-08-28 19:00:59 UTC (rev 4614) +++ trunk/coreboot-v2/src/mainboard/intel/truxton/Config.lb 2009-08-28 20:42:21 UTC (rev 4615) @@ -143,6 +143,19 @@ io 0x60 = 0x2f8 irq 0x70 = 3 end + end + chip superio/smsc/smscsuperio + device pnp 2e.0 off end + device pnp 2e.3 off end + device pnp 2e.4 off end + device pnp 2e.5 off end + device pnp 2e.7 on # PS/2 keyboard / mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 2e.a off end end end device pci 1f.2 on end # SATA Modified: trunk/coreboot-v2/src/mainboard/intel/truxton/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/truxton/Options.lb 2009-08-28 19:00:59 UTC (rev 4614) +++ trunk/coreboot-v2/src/mainboard/intel/truxton/Options.lb 2009-08-28 20:42:21 UTC (rev 4615) @@ -37,6 +37,7 @@ uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START uses CONFIG_COMPRESSED_PAYLOAD_LZMA +uses CONFIG_LB_MEM_TOPK uses CONFIG_PAYLOAD_SIZE uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE @@ -67,6 +68,7 @@ uses HOSTCC uses CONFIG_CROSS_COMPILE uses CONFIG_OBJCOPY +uses CONFIG_CONSOLE_VGA ### @@ -155,9 +157,14 @@ ## ## coreboot C code runs at this location in RAM ## -default CONFIG_RAMBASE=0x00004000 +default CONFIG_RAMBASE=0x00100000 ## +## in order to have coreboot running at 0x100000, TOPK has to be set +## +default CONFIG_LB_MEM_TOPK = 2*1024*1024 + +## ## Load the payload from the ROM ## default CONFIG_ROM_PAYLOAD=1 @@ -202,6 +209,9 @@ # This defaults to 8 data bits, 1 stop bit, and no parity default CONFIG_TTYS0_LCS=0x3 +# Enable the VGA console. +default CONFIG_CONSOLE_VGA=1 + ## ### Select the coreboot loglevel ## Modified: trunk/coreboot-v2/src/mainboard/intel/truxton/devicetree.cb =================================================================== --- trunk/coreboot-v2/src/mainboard/intel/truxton/devicetree.cb 2009-08-28 19:00:59 UTC (rev 4614) +++ trunk/coreboot-v2/src/mainboard/intel/truxton/devicetree.cb 2009-08-28 20:42:21 UTC (rev 4615) @@ -26,6 +26,19 @@ io 0x60 = 0x2f8 irq 0x70 = 3 end + end + chip superio/smsc/smscsuperio + device pnp 2e.0 off end + device pnp 2e.3 off end + device pnp 2e.4 off end + device pnp 2e.5 off end + device pnp 2e.7 on # PS/2 keyboard / mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 2e.a off end end end device pci 1f.2 on end # SATA Modified: trunk/coreboot-v2/src/northbridge/intel/i3100/Config.lb =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i3100/Config.lb 2009-08-28 19:00:59 UTC (rev 4614) +++ trunk/coreboot-v2/src/northbridge/intel/i3100/Config.lb 2009-08-28 20:42:21 UTC (rev 4615) @@ -23,5 +23,6 @@ driver northbridge.o driver pciexp_porta.o +driver pciexp_porta_ep80579.o default CONFIG_HAVE_HIGH_TABLES=1 Added: trunk/coreboot-v2/src/northbridge/intel/i3100/pciexp_porta_ep80579.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i3100/pciexp_porta_ep80579.c (rev 0) +++ trunk/coreboot-v2/src/northbridge/intel/i3100/pciexp_porta_ep80579.c 2009-08-28 20:42:21 UTC (rev 4615) @@ -0,0 +1,112 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 4DSP Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* This code is based on src/northbridge/intel/i3100/pciexp_porta.c */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <device/pciexp.h> +#include <arch/io.h> +#include "chip.h" +#include <part/hard_reset.h> + +typedef struct northbridge_intel_i3100_config config_t; + +static void pcie_init(struct device *dev) +{ + config_t *config; + u16 val; + + /* Get the chip configuration */ + config = dev->chip_info; + + if(config->intrline) { + pci_write_config32(dev, 0x3c, config->intrline); + } + + printk_spew("configure PCIe port as \"Slot Implemented\"\n"); + val = pci_read_config16(dev, 0x66); + val &= ~(1<<8); + val |= 1<<8; + pci_write_config16(dev, 0x66, val); + + /* Todo configure the PCIe bootstrap mode (covered by Intel NDA) */ +} + + +static void pcie_bus_enable_resources(struct device *dev) +{ + u8 val8; + if (dev->link[0].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { + printk_spew("Enable VGA IO/MEM forwarding on PCIe port\n"); + pci_write_config8(dev, PCI_BRIDGE_CONTROL, 8); + + dev->command |= PCI_COMMAND_IO; + dev->command |= PCI_COMMAND_MEMORY; + } + pci_dev_enable_resources(dev); + enable_childrens_resources(dev); +} + + +static unsigned int pcie_scan_bridge(struct device *dev, unsigned int max) +{ + u16 val; + u16 ctl; + int flag = 0; + do { + val = pci_read_config16(dev, 0x76); + printk_debug("pcie porta 0x76: %02x\n", val); + if ((val & (1<<11)) && (!flag)) { /* training error */ + ctl = pci_read_config16(dev, 0x74); + pci_write_config16(dev, 0x74, (ctl | (1<<5))); + val = pci_read_config16(dev, 0x76); + printk_debug("pcie porta reset 0x76: %02x\n", val); + flag=1; + hard_reset(); + } + } while (val & (3<<10)); + return pciexp_scan_bridge(dev, max); +} + +static struct device_operations pcie_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pcie_bus_enable_resources, + .init = pcie_init, + .scan_bus = pcie_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = 0, +}; + +static struct pci_driver pci_driver_0 __pci_driver = { + .ops = &pcie_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_EP80579_PCIE_PA0, +}; + +static struct pci_driver pci_driver_1 __pci_driver = { + .ops = &pcie_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_EP80579_PCIE_PA1, +}; Modified: trunk/coreboot-v2/src/northbridge/intel/i3100/raminit_ep80579.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i3100/raminit_ep80579.c 2009-08-28 19:00:59 UTC (rev 4614) +++ trunk/coreboot-v2/src/northbridge/intel/i3100/raminit_ep80579.c 2009-08-28 20:42:21 UTC (rev 4615) @@ -31,7 +31,7 @@ { static const u32 register_values[] = { PCI_ADDR(0, 0x00, 0, CKDIS), 0xffff0000, 0x0000ffff, - PCI_ADDR(0, 0x00, 0, DEVPRES), 0x00000000, 0x07420801 | DEVPRES_CONFIG, + PCI_ADDR(0, 0x00, 0, DEVPRES), 0x00000000, 0x07420001 | DEVPRES_CONFIG, PCI_ADDR(0, 0x00, 0, PAM-1), 0xcccccc7f, 0x33333000, PCI_ADDR(0, 0x00, 0, PAM+3), 0xcccccccc, 0x33333333, PCI_ADDR(0, 0x00, 0, DEVPRES1), 0xffffffff, 0x0040003a, Modified: trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_early_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_early_lpc.c 2009-08-28 19:00:59 UTC (rev 4614) +++ trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_early_lpc.c 2009-08-28 20:42:21 UTC (rev 4615) @@ -25,6 +25,9 @@ /* Enable decoding of I/O locations for SuperIO devices */ pci_write_config16(dev, 0x80, 0x0010); pci_write_config16(dev, 0x82, 0x340f); + + /* Enable the SERIRQs (start pulse width is 8 clock cycles) */ + pci_write_config8(dev, 0x64, 0xD2); } static void i3100_halt_tco_timer(void) Modified: trunk/coreboot-v2/src/superio/smsc/smscsuperio/superio.c =================================================================== --- trunk/coreboot-v2/src/superio/smsc/smscsuperio/superio.c 2009-08-28 19:00:59 UTC (rev 4614) +++ trunk/coreboot-v2/src/superio/smsc/smscsuperio/superio.c 2009-08-28 20:42:21 UTC (rev 4615) @@ -60,6 +60,7 @@ #define DME1737 0x78 #define SCH3112 0x7c #define SCH5307 0x81 /* Rebranded LPC47B397(?) */ +#define SCH5027D 0x89 /* Register defines */ #define DEVICE_ID_REG 0x20 /* Device ID register */ @@ -135,6 +136,7 @@ {DME1737, {0, 3, 4, 5, -1, 7, -1, -1, -1, -1, -1, -1, 10, -1, -1}}, {SCH3112, {0, 3, 4, 5, -1, 7, -1, -1, -1, -1, -1, -1, 10, -1, -1}}, {SCH5307, {0, 3, 4, 5, -1, 7, -1, -1, 8, -1, -1, -1, 10, -1, -1}}, + {SCH5027D, {0, 3, 4, 5, -1, 7, -1, -1, -1, -1, -1, -1, 10, -1, 11}}, }; /** Modified: trunk/coreboot-v2/targets/intel/truxton/Config.lb =================================================================== --- trunk/coreboot-v2/targets/intel/truxton/Config.lb 2009-08-28 19:00:59 UTC (rev 4614) +++ trunk/coreboot-v2/targets/intel/truxton/Config.lb 2009-08-28 20:42:21 UTC (rev 4615) @@ -34,7 +34,7 @@ romimage "fallback" option CONFIG_USE_FALLBACK_IMAGE=1 - payload /tmp/filo.elf + payload /tmp/seabios.elf end buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"

1 0

[patch] Kconfig support for M57SLI
by Harald Gutmann 28 Aug '09

28 Aug '09

Here is my new version of the Kconfig patch for M57SLI. It does build, but there are some warnings about CONFIG_* values not defined. Right now I have not tested the generated images, but I think I can do that tomorrow. When the images work, it will get the "Signed-off" tag. Thanks to Myles Watson and Christi Magherusan for helping out in various themes according this patch and the understanding of Kconfig. Kind regards, Harald

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coreboot August 2009