coreboot August 2009

coreboot@coreboot.org

61 participants
356 discussions

Kconfig socket try
by Myles Watson 28 Aug '09

28 Aug '09

If we set the cpu family from the socket, then use that to control things like DCACHE, does that work for everyone? Signed-off-by: Myles Watson<mylesgw(a)gmail.com> Thanks, Myles

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[v2] r4610 - in trunk/coreboot-v2/src/cpu/amd: model_fxx socket_940
by svn＠coreboot.org 28 Aug '09

28 Aug '09

Author: myles Date: 2009-08-28 16:40:04 +0200 (Fri, 28 Aug 2009) New Revision: 4610 Modified: trunk/coreboot-v2/src/cpu/amd/model_fxx/Kconfig trunk/coreboot-v2/src/cpu/amd/socket_940/Kconfig Log: Move DCACHE support into the cpu family for AMD model_fxx. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/src/cpu/amd/model_fxx/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_fxx/Kconfig 2009-08-28 14:36:12 UTC (rev 4609) +++ trunk/coreboot-v2/src/cpu/amd/model_fxx/Kconfig 2009-08-28 14:40:04 UTC (rev 4610) @@ -1,15 +1,40 @@ config HAVE_INIT_TIMER bool default y - depends on CPU_AMD_SOCKET_F + depends on CPU_AMD_MODEL_FXX config HAVE_MOVNTI bool default y - depends on CPU_AMD_SOCKET_F + depends on CPU_AMD_MODEL_FXX config CPU_ADDR_BITS int default 40 - depends on CPU_AMD_SOCKET_F + depends on CPU_AMD_MODEL_FXX +config USE_PRINTK_IN_CAR + bool + default y + depends on CPU_AMD_MODEL_FXX + +config USE_DCACHE_RAM + bool + default y + depends on CPU_AMD_MODEL_FXX + +config DCACHE_RAM_BASE + hex + default 0xc8000 + depends on CPU_AMD_MODEL_FXX + +config DCACHE_RAM_SIZE + hex + default 0x08000 + depends on CPU_AMD_MODEL_FXX + +config DCACHE_RAM_GLOBAL_VAR_SIZE + hex + default 0x01000 + depends on CPU_AMD_MODEL_FXX + Modified: trunk/coreboot-v2/src/cpu/amd/socket_940/Kconfig =================================================================== --- trunk/coreboot-v2/src/cpu/amd/socket_940/Kconfig 2009-08-28 14:36:12 UTC (rev 4609) +++ trunk/coreboot-v2/src/cpu/amd/socket_940/Kconfig 2009-08-28 14:40:04 UTC (rev 4610) @@ -12,3 +12,8 @@ hex default 1 depends on CPU_AMD_SOCKET_940 + +config CPU_AMD_MODEL_FXX + bool + default y + depends on CPU_AMD_SOCKET_940

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Kconfig PCI_ROM_RUN and friends
by Myles Watson 28 Aug '09

28 Aug '09

New patch since the include path changed for x86emu. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

2 2

[v2] r4609 - in trunk/coreboot-v2: . src/devices util/x86emu util/x86emu/yabel util/x86emu/yabel/compat
by svn＠coreboot.org 28 Aug '09

28 Aug '09

Author: myles Date: 2009-08-28 16:36:12 +0200 (Fri, 28 Aug 2009) New Revision: 4609 Added: trunk/coreboot-v2/util/x86emu/yabel/Makefile.inc trunk/coreboot-v2/util/x86emu/yabel/compat/Makefile.inc Modified: trunk/coreboot-v2/Makefile trunk/coreboot-v2/src/devices/Kconfig trunk/coreboot-v2/src/devices/Makefile.inc trunk/coreboot-v2/util/x86emu/Makefile.inc trunk/coreboot-v2/util/x86emu/yabel/biosemu.c Log: Add Kconfig support for PCI option ROMS. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/Makefile =================================================================== --- trunk/coreboot-v2/Makefile 2009-08-28 14:23:38 UTC (rev 4608) +++ trunk/coreboot-v2/Makefile 2009-08-28 14:36:12 UTC (rev 4609) @@ -215,6 +215,7 @@ OBJS := $(patsubst %,$(obj)/%,$(TARGETS-y)) INCLUDES := -I$(top)/src -I$(top)/src/include -I$(obj) -I$(top)/src/arch/$(ARCHDIR-y)/include INCLUDES += -I$(shell $(CC) -print-search-dirs | head -n 1 | cut -d' ' -f2)include +INCLUDES += -I$(top)/util/x86emu/include INCLUDES += -include $(obj)/build.h try-run= $(shell set -e; \ Modified: trunk/coreboot-v2/src/devices/Kconfig =================================================================== --- trunk/coreboot-v2/src/devices/Kconfig 2009-08-28 14:23:38 UTC (rev 4608) +++ trunk/coreboot-v2/src/devices/Kconfig 2009-08-28 14:36:12 UTC (rev 4609) @@ -21,35 +21,45 @@ menu "Devices" config VGA_ROM_RUN - bool + bool "Run VGA Option ROMs" help - Execute PCI/AGP option ROMs if available. This is required to - enable PCI/AGP VGA plugin cards. + Execute VGA option ROMs if found. This is required to enable PCI/AGP + VGA plugin cards. -choice - prompt "Execute PCI option ROMs" - default PCI_OPTION_ROM_RUN_REALMODE +config PCI_ROM_RUN + bool "Run non-VGA Option ROMs" help - Execute PCI/AGP option ROMs if available. You can choose to - execute PCI option ROMs natively (32bit x86 system required), - in an emulator (x86emu), or ignore option ROM execution. + Execute non-VGA PCI option ROMs if found. -config PCI_OPTION_ROM_RUN_REALMODE - prompt "Run VGA ROMs" - bool - select VGA_ROM_RUN - help - Execute PCI/AGP option ROMs if available. This is required to - enable PCI/AGP VGA plugin cards. +choice + prompt "Option ROM Execution" + default PCI_OPTION_ROM_RUN_REALMODE + depends on PCI_ROM_RUN || VGA_ROM_RUN + help + You can choose to execute PCI option ROMs natively (32bit x86 system + required) or in an emulator (x86emu or YABEL). -config NO_RUN - prompt "Do NOT run VGA ROMs" - bool - help - Do not execute PCI/AGP option ROMs. + config PCI_OPTION_ROM_RUN_REALMODE + prompt "Real mode" + bool + config PCI_OPTION_ROM_RUN_YABEL + prompt "YABEL" + bool + + config PCI_OPTION_ROM_RUN_X86EMU + prompt "X86EMU" + bool endchoice +config YABEL_DEBUG_FLAGS + prompt "Hex value for debug flags" + hex + default 0x0 + depends on PCI_OPTION_ROM_RUN_YABEL + help + See debug.h for values 0 is no debug output, 0x31ff is _verbose_. + endmenu config PCI_64BIT_PREF_MEM Modified: trunk/coreboot-v2/src/devices/Makefile.inc =================================================================== --- trunk/coreboot-v2/src/devices/Makefile.inc 2009-08-28 14:23:38 UTC (rev 4608) +++ trunk/coreboot-v2/src/devices/Makefile.inc 2009-08-28 14:36:12 UTC (rev 4609) @@ -12,8 +12,8 @@ obj-y += smbus_ops.o ifeq ($(CONFIG_PCI_ROM_RUN),y) -obj-$(CONFIG_PCI_ROM_RUN) += pci_rom.o -subdirs-$(CONFIG_PCI_ROM_RUN) += ../../util/x86emu +obj-y += pci_rom.o +subdirs-y += ../../util/x86emu else obj-$(CONFIG_VGA_ROM_RUN) += pci_rom.o subdirs-$(CONFIG_VGA_ROM_RUN) += ../../util/x86emu Modified: trunk/coreboot-v2/util/x86emu/Makefile.inc =================================================================== --- trunk/coreboot-v2/util/x86emu/Makefile.inc 2009-08-28 14:23:38 UTC (rev 4608) +++ trunk/coreboot-v2/util/x86emu/Makefile.inc 2009-08-28 14:36:12 UTC (rev 4609) @@ -19,9 +19,12 @@ ## subdirs-$(CONFIG_PCI_OPTION_ROM_RUN_X86EMU) += x86emu -obj-$(CONFIG_PCI_OPTION_ROM_RUN_X86EMU) += biosemu.c +obj-$(CONFIG_PCI_OPTION_ROM_RUN_X86EMU) += biosemu.o subdirs-$(CONFIG_PCI_OPTION_ROM_RUN_X86EMU) += pcbios obj-$(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) += x86.o obj-$(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) += x86_asm.o obj-$(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) += x86_interrupts.o + +subdirs-$(CONFIG_PCI_OPTION_ROM_RUN_YABEL) += x86emu +subdirs-$(CONFIG_PCI_OPTION_ROM_RUN_YABEL) += yabel Added: trunk/coreboot-v2/util/x86emu/yabel/Makefile.inc =================================================================== --- trunk/coreboot-v2/util/x86emu/yabel/Makefile.inc (rev 0) +++ trunk/coreboot-v2/util/x86emu/yabel/Makefile.inc 2009-08-28 14:36:12 UTC (rev 4609) @@ -0,0 +1,8 @@ +obj-y += biosemu.o +obj-y += debug.o +obj-y += device.o +obj-y += interrupt.o +obj-y += io.o +obj-y += mem.o +obj-y += pmm.o +subdirs-y += compat Modified: trunk/coreboot-v2/util/x86emu/yabel/biosemu.c =================================================================== --- trunk/coreboot-v2/util/x86emu/yabel/biosemu.c 2009-08-28 14:23:38 UTC (rev 4608) +++ trunk/coreboot-v2/util/x86emu/yabel/biosemu.c 2009-08-28 14:36:12 UTC (rev 4609) @@ -56,8 +56,6 @@ /* interrupt function override array (see biosemu.h) */ yabel_handleIntFunc yabel_intFuncArray[256]; -void dump(u8 * addr, u32 len); - /* main entry into YABEL biosemu, arguments are: * *biosmem = pointer to virtual memory * biosmem_size = size of the virtual memory Added: trunk/coreboot-v2/util/x86emu/yabel/compat/Makefile.inc =================================================================== --- trunk/coreboot-v2/util/x86emu/yabel/compat/Makefile.inc (rev 0) +++ trunk/coreboot-v2/util/x86emu/yabel/compat/Makefile.inc 2009-08-28 14:36:12 UTC (rev 4609) @@ -0,0 +1 @@ +obj-y += functions.o

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patch: starting to get some variables out of mainboard Kconfig that ought not be there.
by ron minnich 28 Aug '09

28 Aug '09

attached. I have mainboard patch for serengeti if this patch is ok. ron

2 2

[v2] r4608 - in trunk/coreboot-v2/src: console devices
by svn＠coreboot.org 28 Aug '09

28 Aug '09

Author: rminnich Date: 2009-08-28 16:23:38 +0200 (Fri, 28 Aug 2009) New Revision: 4608 Modified: trunk/coreboot-v2/src/console/Kconfig trunk/coreboot-v2/src/devices/Kconfig Log: Move some config variables that are in one or two mainboards to more rational places. The goal is to reduce the number of Config variables defined in mainboard Kconfig files to the absolute minimum. This has the side effect of making SERIAL_POST a menu item, which is nice. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/coreboot-v2/src/console/Kconfig =================================================================== --- trunk/coreboot-v2/src/console/Kconfig 2009-08-28 13:42:24 UTC (rev 4607) +++ trunk/coreboot-v2/src/console/Kconfig 2009-08-28 14:23:38 UTC (rev 4608) @@ -4,6 +4,10 @@ bool "See output on the serial port console" default y +config SERIAL_POST + bool "See POST output on the serial port console" + default n + config TTYS0_BASE hex "I/O base for the serial port" depends on SERIAL_CONSOLE Modified: trunk/coreboot-v2/src/devices/Kconfig =================================================================== --- trunk/coreboot-v2/src/devices/Kconfig 2009-08-28 13:42:24 UTC (rev 4607) +++ trunk/coreboot-v2/src/devices/Kconfig 2009-08-28 14:23:38 UTC (rev 4608) @@ -51,3 +51,30 @@ endchoice endmenu + +config PCI_64BIT_PREF_MEM + bool + default n + +config HYPERTRANSPORT_PLUGIN_SUPPORT + bool + default n + +config PCIX_PLUGIN_SUPPORT + bool + default n + +config PCIEXP_PLUGIN_SUPPORT + bool + default n + +config AGP_PLUGIN_SUPPORT + bool + default n + +config CARDBUS_PLUGIN_SUPPORT + bool + default n + + +

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code conflicting with Kconfig
by Carl-Daniel Hailfinger 28 Aug '09

28 Aug '09

v2 has some code which does not like the current state of Kconfig. The list below is a small sample only, it was taken for the Asus M2V-MX SE. src/northbridge/amd/amdk8/raminit_f.c:1069:5: warning: "CONFIG_HW_MEM_HOLE_SIZEK" is not defined src/northbridge/amd/amdk8/raminit_f_dqs.c:81:5: warning: "CONFIG_HW_MEM_HOLE_SIZEK" is not defined src/northbridge/amd/amdk8/raminit_f_dqs.c:94:5: warning: "CONFIG_HW_MEM_HOLE_SIZEK" is not defined src/northbridge/amd/amdk8/raminit_f_dqs.c:858:5: warning: "CONFIG_MEM_TRAIN_SEQ" is not defined src/northbridge/amd/amdk8/raminit_f_dqs.c:1705:5: warning: "CONFIG_MEM_TRAIN_SEQ" is not defined src/northbridge/amd/amdk8/raminit_f_dqs.c:1924:5: warning: "CONFIG_MEM_TRAIN_SEQ" is not defined src/northbridge/amd/amdk8/raminit_f_dqs.c:2010:5: warning: "CONFIG_MEM_TRAIN_SEQ" is not defined src/northbridge/amd/amdk8/raminit_f_dqs.c:2084:5: warning: "CONFIG_MEM_TRAIN_SEQ" is not defined src/northbridge/amd/amdk8/raminit_f.c:2883:5: warning: "CONFIG_HW_MEM_HOLE_SIZEK" is not defined src/northbridge/amd/amdk8/exit_from_self.c:159:5: warning: "CONFIG_HW_MEM_HOLE_SIZEK" is not defined src/northbridge/amd/amdk8/raminit_f.c:3146:5: warning: "CONFIG_HW_MEM_HOLE_SIZEK" is not defined src/northbridge/amd/amdk8/raminit_f.c:3178:5: warning: "CONFIG_MEM_TRAIN_SEQ" is not defined src/northbridge/amd/amdk8/raminit_f.c:3209:5: warning: "CONFIG_MEM_TRAIN_SEQ" is not defined src/sdram/generic_sdram.c:8:5: warning: "CONFIG_USE_INIT" is not defined src/cpu/amd/car/copy_and_run.c:18:5: warning: "CONFIG_AP_CODE_IN_CAR" is not defined src/northbridge/amd/amdk8/northbridge.c:140:5: warning: "CONFIG_SB_HT_CHAIN_ON_BUS0" is not defined src/northbridge/amd/amdk8/northbridge.c:242:5: warning: "CONFIG_SB_HT_CHAIN_ON_BUS0" is not defined src/northbridge/amd/amdk8/northbridge.c:251:5: warning: "CONFIG_SB_HT_CHAIN_ON_BUS0" is not defined src/northbridge/amd/amdk8/northbridge.c:478:5: warning: "CONFIG_CONSOLE_VGA_MULTI" is not defined src/northbridge/amd/amdk8/northbridge.c:491:5: warning: "CONFIG_CONSOLE_VGA_MULTI" is not defined src/northbridge/amd/amdk8/northbridge.c:639:5: warning: "CONFIG_PCI_64BIT_PREF_MEM" is not defined src/northbridge/amd/amdk8/northbridge.c:687:5: warning: "CONFIG_HW_MEM_HOLE_SIZEK" is not defined src/northbridge/amd/amdk8/northbridge.c:846:5: warning: "CONFIG_PCI_64BIT_PREF_MEM" is not defined src/northbridge/amd/amdk8/northbridge.c:853:5: warning: "CONFIG_HW_MEM_HOLE_SIZEK" is not defined src/northbridge/amd/amdk8/northbridge.c:863:5: warning: "CONFIG_PCI_64BIT_PREF_MEM" is not defined src/northbridge/amd/amdk8/northbridge.c:931:5: warning: "CONFIG_HW_MEM_HOLE_SIZEK" is not defined src/northbridge/amd/amdk8/northbridge.c:1027:9: warning: "CONFIG_HW_MEM_HOLE_SIZEK" is not defined src/cpu/amd/model_fxx/model_fxx_init.c:35:5: warning: "CONFIG_MEM_TRAIN_SEQ" is not defined src/cpu/amd/model_fxx/model_fxx_init.c:292:5: warning: "CONFIG_HW_MEM_HOLE_SIZEK" is not defined src/cpu/amd/model_fxx/model_fxx_init.c:325:5: warning: "CONFIG_HW_MEM_HOLE_SIZEK" is not defined src/include/part/watchdog.h:4:5: warning: "CONFIG_USE_WATCHDOG_ON_BOOT" is not defined src/console/console.c:78:5: warning: "CONFIG_SERIAL_POST" is not defined src/devices/device.c:533:5: warning: "CONFIG_PCI_64BIT_PREF_MEM" is not defined src/devices/pci_device.c:38:5: warning: "CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT" is not defined src/devices/pci_device.c:41:5: warning: "CONFIG_PCIX_PLUGIN_SUPPORT" is not defined src/devices/pci_device.c:44:5: warning: "CONFIG_PCIEXP_PLUGIN_SUPPORT" is not defined src/devices/pci_device.c:47:5: warning: "CONFIG_AGP_PLUGIN_SUPPORT" is not defined src/devices/pci_device.c:50:5: warning: "CONFIG_CARDBUS_PLUGIN_SUPPORT" is not defined src/devices/pci_device.c:747:5: warning: "CONFIG_PCIX_PLUGIN_SUPPORT" is not defined src/devices/pci_device.c:754:5: warning: "CONFIG_AGP_PLUGIN_SUPPORT" is not defined src/devices/pci_device.c:757:5: warning: "CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT" is not defined src/devices/pci_device.c:770:5: warning: "CONFIG_PCIEXP_PLUGIN_SUPPORT" is not defined src/devices/pci_device.c:834:5: warning: "CONFIG_CARDBUS_PLUGIN_SUPPORT" is not defined src/cpu/x86/tsc/delay_tsc.c:10:6: warning: "CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2" is not defined src/cpu/x86/mtrr/mtrr.c:421:6: warning: "CONFIG_GFXUMA" is not defined src/cpu/x86/lapic/lapic_cpu_init.c:451:5: warning: "CONFIG_WAIT_BEFORE_CPUS_INIT" is not defined Any fixes (which still work with the old config style) appreciated. We may have to change Kconfig for this. Regards, Carl-Daniel -- http://www.hailfinger.org/

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Winbond W83627 HG revision request
by Vladimir Alexeev 28 Aug '09

28 Aug '09

Greets! Can anyone make support for Winbond W83627-based microcontroller for HG revision this chip under AMD Geode LX generic motherboard. Or if can anyone make a patch for early blind initialization UART A port for debug output? wbr, Vladimir

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[v2] r4607 - trunk/coreboot-v2/src/southbridge/intel/i82801xx
by svn＠coreboot.org 28 Aug '09

28 Aug '09

Author: uwe Date: 2009-08-28 15:42:24 +0200 (Fri, 28 Aug 2009) New Revision: 4607 Modified: trunk/coreboot-v2/src/southbridge/intel/i82801xx/chip.h Log: Silence unneeded #warnings, change to code comments (tr?\209?\150vial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/coreboot-v2/src/southbridge/intel/i82801xx/chip.h =================================================================== --- trunk/coreboot-v2/src/southbridge/intel/i82801xx/chip.h 2009-08-28 12:48:02 UTC (rev 4606) +++ trunk/coreboot-v2/src/southbridge/intel/i82801xx/chip.h 2009-08-28 13:42:24 UTC (rev 4607) @@ -18,14 +18,19 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef IGNORE_I82801XX_DEVICE_LIST -#warning "The i82801xx code currently supports, on a testing/experimental" -#warning "basis, these devices:" -#warning "i82801aa, i82801ab, i82801ba, i82801ca, i82801db, i82801dbm," -#warning "i82801eb, and i82801er." -#warning "Using this without modification on any other i82801 version will" -#warning "probably work until RAM init, but will fail after that." -#endif +/* + * The i82801xx code currently supports: + * - 82801AA + * - 82801AB + * - 82801BA + * - 82801CA + * - 82801DB + * - 82801DBM + * - 82801EB + * - 82801ER + * + * This code should NOT be used for ICH6 and later versions. + */ #ifndef SOUTHBRIDGE_INTEL_I82801XX_CHIP_H #define SOUTHBRIDGE_INTEL_I82801XX_CHIP_H @@ -43,10 +48,11 @@ uint8_t pirqf_routing; uint8_t pirqg_routing; uint8_t pirqh_routing; + uint8_t ide0_enable; uint8_t ide1_enable; }; extern struct chip_operations southbridge_intel_i82801xx_ops; -#endif /* SOUTHBRIDGE_INTEL_I82801XX_CHIP_H */ +#endif

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[PATCH] Kill duplicated code in Config.lb
by Carl-Daniel Hailfinger 28 Aug '09

28 Aug '09

r4534 introduced devicetree.cb in every mainboard directory, and 100% of that content was extracted from Config.lb in the same directory without eliminating the original contents. This patch fixes the dupliaction by using include statements. So far, I only tackled amd/dbm690t because it's the only target I can run a build+boot test for. Someone needs to fix the other 110 boards in the tree. Boot tested. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/Config.lb =================================================================== --- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/Config.lb (Revision 4605) +++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/Config.lb (Arbeitskopie) @@ -134,132 +134,4 @@ config chip.h #The variables belong to mainboard are defined here. - -#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) -#Define vga_rom_address = 0xfff0000 -#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) -#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, -# 1: the system allows a PCIE link to be established on Dev2 or Dev3. -#Define gfx_dual_slot, 0: single slot, 1: dual slot -#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable -#Define gfx_tmds, 0: didn't support TMDS, 1: support -#Define gfx_compliance, 0: didn't support compliance, 1: support -#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration -#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 -chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on - chip cpu/amd/socket_S1G1 - device apic 0 on end - end - end - device pci_domain 0 on - chip northbridge/amd/amdk8 - device pci 18.0 on # southbridge - chip southbridge/amd/rs690 - device pci 0.0 on end # HT 0x7910 - device pci 1.0 on # Internal Graphics P2P bridge 0x7912 - chip drivers/pci/onboard - device pci 5.0 on end # Internal Graphics 0x791F - register "rom_address" = "0xfff00000" - end - end - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 - device pci 3.0 off end # PCIE P2P bridge 0x791b - device pci 4.0 on end # PCIE P2P bridge 0x7914 - device pci 5.0 on end # PCIE P2P bridge 0x7915 - device pci 6.0 on end # PCIE P2P bridge 0x7916 - device pci 7.0 on end # PCIE P2P bridge 0x7917 - device pci 8.0 off end # NB/SB Link P2P bridge - register "vga_rom_address" = "0xfff00000" - register "gpp_configuration" = "4" - register "port_enable" = "0xfc" - register "gfx_dev2_dev3" = "1" - register "gfx_dual_slot" = "0" - register "gfx_lane_reversal" = "0" - register "gfx_tmds" = "0" - register "gfx_compliance" = "0" - register "gfx_reconfiguration" = "1" - register "gfx_link_width" = "0" - end - chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus - device pci 12.0 on end # SATA 0x4380 - device pci 13.0 on end # USB 0x4387 - device pci 13.1 on end # USB 0x4388 - device pci 13.2 on end # USB 0x4389 - device pci 13.3 on end # USB 0x438a - device pci 13.4 on end # USB 0x438b - device pci 13.5 on end # USB 2 0x4386 - device pci 14.0 on # SM 0x4385 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - end # SM - device pci 14.1 on end # IDE 0x438c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x438d - chip superio/ite/it8712f - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 off end # EC - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 on # Mouse - irq 0x70 = 12 - end - device pnp 2e.7 off # GPIO, must be closed for unresolved reason. - end - device pnp 2e.8 off # MIDI - io 0x60 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.9 off # GAME - io 0x60 = 0x220 - end - device pnp 2e.a off end # CIR - end #superio/ite/it8712f - end #LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # ACI 0x4382 - device pci 14.6 on end # MCI 0x438e - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "hda_viddid" = "0x10ec0882" - end #southbridge/amd/sb600 - end # device pci 18.0 - - device pci 18.0 on end - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end #northbridge/amd/amdk8 - end #pci_domain -end #northbridge/amd/amdk8/root_complex - +include /mainboard/amd/dbm690t/devicetree.cb Index: LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/devicetree.cb =================================================================== --- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/devicetree.cb (Revision 4605) +++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/devicetree.cb (Arbeitskopie) @@ -1,3 +1,14 @@ +#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) +#Define vga_rom_address = 0xfff0000 +#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) +#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, +# 1: the system allows a PCIE link to be established on Dev2 or Dev3. +#Define gfx_dual_slot, 0: single slot, 1: dual slot +#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable +#Define gfx_tmds, 0: didn't support TMDS, 1: support +#Define gfx_compliance, 0: didn't support compliance, 1: support +#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration +#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 chip northbridge/amd/amdk8/root_complex device apic_cluster 0 on chip cpu/amd/socket_S1G1 -- http://www.hailfinger.org/

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coreboot August 2009