coreboot August 2009

coreboot@coreboot.org

61 participants
356 discussions

[PATCH] Fix AMD 690 HIGH_TABLES
by Carl-Daniel Hailfinger 15 Oct '09

15 Oct '09

Zheng, can you please test this with HIGH_TABLES enabled (and a new FILO)? A full log would be appreciated. Thanks. This hopefully will fix AMD 690 HIGH_TABLES or at least give me an insight into why HIGH_TABLES fails. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/northbridge.c =================================================================== --- LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/northbridge.c (Revision 4339) +++ LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/northbridge.c (Arbeitskopie) @@ -896,6 +896,7 @@ #if HAVE_HIGH_TABLES==1 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB extern uint64_t high_tables_base, high_tables_size; +extern uint64_t uma_memory_base, uma_memory_size; #endif static void pci_domain_set_resources(device_t dev) @@ -1066,7 +1067,9 @@ } -// printk_debug("node %d : mmio_basek=%08x, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); //yhlu + printk_debug("node %d : uma_memory_base/1024=0x%08x, mmio_basek=0x%08x, basek=0x%08x, limitk=0x%08x\n", i, uma_memory_base >> 10, mmio_basek, basek, limitk); + if ((uma_memory_base >> 10) < mmio_basek) + printk_alert("node %d: UMA memory starts below mmio_basek\n", i); /* See if I need to split the region to accomodate pci memory space */ if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) { @@ -1080,7 +1083,7 @@ #if HAVE_HIGH_TABLES==1 if (i==0 && high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024; + high_tables_base = ((uma_memory_base >> 10) - HIGH_TABLES_SIZE) * 1024; high_tables_size = HIGH_TABLES_SIZE * 1024; printk_debug("(split)%xK table at =%08llx\n", HIGH_TABLES_SIZE, high_tables_base); @@ -1105,6 +1108,9 @@ sizek -= (4*1024*1024 - mmio_basek); } } + + printk_debug("node %d : uma_memory_base/1024=0x%08x, mmio_basek=0x%08x, basek=0x%08x, limitk=0x%08x\n", i, uma_memory_base >> 10, mmio_basek, basek, limitk); + /* If sizek == 0, it was split at mmio_basek without a hole. * Don't create an empty ram_resource. */ @@ -1116,7 +1122,7 @@ i, mmio_basek, basek, limitk); if (i==0 && high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024; + high_tables_base = ((uma_memory_base >> 10) - HIGH_TABLES_SIZE) * 1024; high_tables_size = HIGH_TABLES_SIZE * 1024; } #endif -- http://www.hailfinger.org/ Index: LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/northbridge.c =================================================================== --- LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/northbridge.c (Revision 4339) +++ LinuxBIOSv2-asus_m2a-vm/src/northbridge/amd/amdk8/northbridge.c (Arbeitskopie) @@ -896,6 +896,7 @@ #if HAVE_HIGH_TABLES==1 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB extern uint64_t high_tables_base, high_tables_size; +extern uint64_t uma_memory_base, uma_memory_size; #endif static void pci_domain_set_resources(device_t dev) @@ -1066,7 +1067,9 @@ } -// printk_debug("node %d : mmio_basek=%08x, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); //yhlu + printk_debug("node %d : uma_memory_base/1024=0x%08x, mmio_basek=0x%08x, basek=0x%08x, limitk=0x%08x\n", i, uma_memory_base >> 10, mmio_basek, basek, limitk); + if ((uma_memory_base >> 10) < mmio_basek) + printk_alert("node %d: UMA memory starts below mmio_basek\n", i); /* See if I need to split the region to accomodate pci memory space */ if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) { @@ -1080,7 +1083,7 @@ #if HAVE_HIGH_TABLES==1 if (i==0 && high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024; + high_tables_base = ((uma_memory_base >> 10) - HIGH_TABLES_SIZE) * 1024; high_tables_size = HIGH_TABLES_SIZE * 1024; printk_debug("(split)%xK table at =%08llx\n", HIGH_TABLES_SIZE, high_tables_base); @@ -1105,6 +1108,9 @@ sizek -= (4*1024*1024 - mmio_basek); } } + + printk_debug("node %d : uma_memory_base/1024=0x%08x, mmio_basek=0x%08x, basek=0x%08x, limitk=0x%08x\n", i, uma_memory_base >> 10, mmio_basek, basek, limitk); + /* If sizek == 0, it was split at mmio_basek without a hole. * Don't create an empty ram_resource. */ @@ -1116,7 +1122,7 @@ i, mmio_basek, basek, limitk); if (i==0 && high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024; + high_tables_base = ((uma_memory_base >> 10) - HIGH_TABLES_SIZE) * 1024; high_tables_size = HIGH_TABLES_SIZE * 1024; } #endif

3 6

[PATCH] Die properly if CBFS can't find a stage
by Carl-Daniel Hailfinger 15 Oct '09

15 Oct '09

cbfs_and_run_core() did not check the return code of cbfs_load_stage() and jumped to (void*)-1 on error. Die properly instead. I didn't use die() because that caused a linker error. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: LinuxBIOSv2-asus_m2a-vm/src/arch/i386/lib/cbfs_and_run.c =================================================================== --- LinuxBIOSv2-asus_m2a-vm/src/arch/i386/lib/cbfs_and_run.c (Revision 4589) +++ LinuxBIOSv2-asus_m2a-vm/src/arch/i386/lib/cbfs_and_run.c (Arbeitskopie) @@ -11,6 +11,11 @@ u8 *dst; print_debug("Jumping to image.\r\n"); dst = cbfs_load_stage(filename); + if (dst == (void *) -1) { + /* We should use die() here. */ + print_emerg("Loading stage failed!\n"); + for (;;); + } print_debug("Jumping to image.\r\n"); __asm__ volatile ( -- http://www.hailfinger.org/

6 8

flashrom on MCP73
by Fabrício Ceolin 08 Oct '09

08 Oct '09

Hi guys, We are trying to make flashrom work on http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=858&… Chipset MCP73 / SIP chipset Macronix MX25L8005. We made modifications using a enable_flash_mcp55 function, but does't work. ./flashrom -V -c MX25L8005 -r -f rom Calibrating delay loop... 627M loops per second, 100 myus = 199 us. OK. No coreboot table found. Found chipset "NVIDIA MCP73", enabling flash write... OK. Probing for Macronix MX25L8005, 1024 KB: spi_command called, but no SPI chipset/strapping detected No EEPROM/flash device found. Force read (-f -r -c) requested, forcing chip probe success: Probing for Macronix MX25L8005, 1024 KB: Found chip "Macronix MX25L8005" (1024 KB) at physical address 0xfff00000. Force reading flash... spi_chip_read called, but no SPI chipset/strapping detected 0 done. How can I do works? Are there any hints? Thanks! -- Fabrício Ceolin

3 4

AMD 690/SB600 ACPI bug?
by Carl-Daniel Hailfinger 04 Oct '09

04 Oct '09

Hi, I read through the AMD 690/SB600 ACPI code and saw that src/mainboard/amd/pistachio/acpi/dsdt.asl src/mainboard/amd/dbm690t/acpi/dsdt.asl src/mainboard/technexion/tim8690/acpi/dsdt.asl all read STB5 from PCIe config space and then use the result as address of the SATA BAR5 without any proper bitmasking. For non-prefetchable 32-bit memory BARs this is OK, but if the BAR is either 64-bit or prefetchable or not memory, accesses to BAR5 will be screwed up. Comments are appreciated. I think that SATA BAR5 is 32-bit no-prefetch memory, but since SATA does not work if I boot with 4 GB RAM, I'm pretty paranoid about everything related to 32/64 bit issues. Regards, Carl-Daniel -- http://www.hailfinger.org/

2 1

[PATCH] Kill dead code in Intel E7520 raminit_test
by Carl-Daniel Hailfinger 04 Oct '09

04 Oct '09

/src/northbridge/intel/e7520/raminit_test.c is _the_ file which caused the stongest WTF!?! reaction ever when I read it. If redefines pci_read_config*() and pci_write_config*() as simple memory accesses to a local array without _any_ side effects. Same for pci_locate_device() which essentially operates on the fake pci_read_config*(). Its rdmsr() function is hardcoded to return zero and wrmsr() is empty. It has fake SPD arrays which are ignored. spd_read_byte() accesses the fake SPD arrays, then the result of spd_read_byte is discarded. It messes with setjmp() and longjmp(), but basically only uses them to hlt() upon invalid parameters to log2(). It calls raminit_main() at least 1 times and at most 73 times. It uses AMD Athlon dualcore PCI BDF in sdram_initialize() although it is an Intel chipset. It writes to stdout and stderr. (Yes, really.) Looking at this file is like watching a mass freeway pile-up. It's horrible, but you can't stop looking. Fix the majority of WTFs. Can we just rip this file out? Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: LinuxBIOSv2-raminit_test_cleanup/src/northbridge/intel/e7520/raminit_test.c =================================================================== --- LinuxBIOSv2-raminit_test_cleanup/src/northbridge/intel/e7520/raminit_test.c (Revision 4591) +++ LinuxBIOSv2-raminit_test_cleanup/src/northbridge/intel/e7520/raminit_test.c (Arbeitskopie) @@ -14,112 +14,18 @@ return 0; } -#define PCI_ADDR(BUS, DEV, FN, WHERE) ( \ - (((BUS) & 0xFF) << 16) | \ - (((DEV) & 0x1f) << 11) | \ - (((FN) & 0x07) << 8) | \ - ((WHERE) & 0xFF)) - #define PCI_DEV(BUS, DEV, FN) ( \ (((BUS) & 0xFF) << 16) | \ (((DEV) & 0x1f) << 11) | \ (((FN) & 0x7) << 8)) -#define PCI_ID(VENDOR_ID, DEVICE_ID) \ - ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) - typedef unsigned device_t; -unsigned char pci_register[256*5*3*256]; - -static uint8_t pci_read_config8(device_t dev, unsigned where) -{ - unsigned addr; - addr = dev | where; - return pci_register[addr]; -} - -static uint16_t pci_read_config16(device_t dev, unsigned where) -{ - unsigned addr; - addr = dev | where; - return pci_register[addr] | (pci_register[addr + 1] << 8); -} - -static uint32_t pci_read_config32(device_t dev, unsigned where) -{ - unsigned addr; - uint32_t value; - addr = dev | where; - value = pci_register[addr] | - (pci_register[addr + 1] << 8) | - (pci_register[addr + 2] << 16) | - (pci_register[addr + 3] << 24); - -#if 0 - print_debug("pcir32("); - print_debug_hex32(addr); - print_debug("):"); - print_debug_hex32(value); - print_debug("\n"); -#endif - return value; - -} - -static void pci_write_config8(device_t dev, unsigned where, uint8_t value) -{ - unsigned addr; - addr = dev | where; - pci_register[addr] = value; -} - -static void pci_write_config16(device_t dev, unsigned where, uint16_t value) -{ - unsigned addr; - addr = dev | where; - pci_register[addr] = value & 0xff; - pci_register[addr + 1] = (value >> 8) & 0xff; -} - -static void pci_write_config32(device_t dev, unsigned where, uint32_t value) -{ - unsigned addr; - addr = dev | where; - pci_register[addr] = value & 0xff; - pci_register[addr + 1] = (value >> 8) & 0xff; - pci_register[addr + 2] = (value >> 16) & 0xff; - pci_register[addr + 3] = (value >> 24) & 0xff; - -#if 0 - print_debug("pciw32("); - print_debug_hex32(addr); - print_debug(", "); - print_debug_hex32(value); - print_debug(")\n"); -#endif -} - -#define PCI_DEV_INVALID (0xffffffffU) -static device_t pci_locate_device(unsigned pci_id, device_t dev) -{ - for(; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0,0,1)) { - unsigned int id; - id = pci_read_config32(dev, 0); - if (id == pci_id) { - return dev; - } - } - return PCI_DEV_INVALID; -} - - - - static void uart_tx_byte(unsigned char data) { write(STDOUT_FILENO, &data, 1); } + static void hlt(void) { longjmp(end_buf, 2); @@ -144,161 +50,10 @@ return pow; } -typedef struct msr_struct -{ - unsigned lo; - unsigned hi; -} msr_t; - -static inline msr_t rdmsr(unsigned index) -{ - msr_t result; - result.lo = 0; - result.hi = 0; - return result; -} - -static inline void wrmsr(unsigned index, msr_t msr) -{ -} - #include "raminit.h" #define SIO_BASE 0x2e -static void hard_reset(void) -{ - /* FIXME implement the hard reset case... */ - longjmp(end_buf, 3); -} - -static void memreset_setup(void) -{ - /* Nothing to do */ -} - -static void memreset(int controllers, const struct mem_controller *ctrl) -{ - /* Nothing to do */ -} - -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* nothing to do */ -} - - -static uint8_t spd_mt4lsdt464a[256] = -{ - 0x80, 0x08, 0x04, 0x0C, 0x08, 0x01, 0x40, 0x00, 0x01, 0x70, - 0x54, 0x00, 0x80, 0x10, 0x00, 0x01, 0x8F, 0x04, 0x06, 0x01, - 0x01, 0x00, 0x0E, 0x75, 0x54, 0x00, 0x00, 0x0F, 0x0E, 0x0F, - - 0x25, 0x08, 0x15, 0x08, 0x15, 0x08, 0x00, 0x12, 0x01, 0x4E, - 0x9C, 0xE4, 0xB7, 0x46, 0x2C, 0xFF, 0x01, 0x02, 0x03, 0x04, - 0x05, 0x06, 0x07, 0x08, 0x09, 0x01, 0x02, 0x03, 0x04, 0x05, - 0x06, 0x07, 0x08, 0x09, 0x00, -}; - -static uint8_t spd_micron_512MB_DDR333[256] = -{ - 0x80, 0x08, 0x07, 0x0d, 0x0b, 0x02, 0x48, 0x00, 0x04, 0x60, - 0x70, 0x02, 0x82, 0x04, 0x04, 0x01, 0x0e, 0x04, 0x0c, 0x01, - 0x02, 0x26, 0xc0, 0x75, 0x70, 0x00, 0x00, 0x48, 0x30, 0x48, - 0x2a, 0x80, 0x80, 0x80, 0x45, 0x45, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x3c, 0x48, 0x30, 0x28, 0x50, 0x00, 0x01, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x10, 0x6f, 0x2c, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0x01, 0x33, 0x36, 0x56, 0x44, 0x44, 0x46, 0x31, - 0x32, 0x38, 0x37, 0x32, 0x47, 0x2d, 0x33, 0x33, 0x35, 0x43, - 0x33, 0x03, 0x00, 0x03, 0x23, 0x17, 0x07, 0x5a, 0xb2, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff -}; - -static uint8_t spd_micron_256MB_DDR333[256] = -{ - 0x80, 0x08, 0x07, 0x0d, 0x0b, 0x01, 0x48, 0x00, 0x04, 0x60, - 0x70, 0x02, 0x82, 0x04, 0x04, 0x01, 0x0e, 0x04, 0x0c, 0x01, - 0x02, 0x26, 0xc0, 0x75, 0x70, 0x00, 0x00, 0x48, 0x30, 0x48, - 0x2a, 0x80, 0x80, 0x80, 0x45, 0x45, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x3c, 0x48, 0x30, 0x23, 0x50, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x58, 0x2c, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0x01, 0x31, 0x38, 0x56, 0x44, 0x44, 0x46, 0x36, - 0x34, 0x37, 0x32, 0x47, 0x2d, 0x33, 0x33, 0x35, 0x43, 0x31, - 0x20, 0x01, 0x00, 0x03, 0x19, 0x17, 0x05, 0xb2, 0xf4, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -}; - -#define MAX_DIMMS 16 -static uint8_t spd_data[MAX_DIMMS*256]; - -static unsigned spd_count, spd_fail_count; -static int spd_read_byte(unsigned device, unsigned address) -{ - int result; - spd_count++; - if ((device < 0x50) || (device >= (0x50 +MAX_DIMMS))) { - result = -1; - } - else { - device -= 0x50; - - if (address > 256) { - result = -1; - } - else if (spd_data[(device << 8) | 2] != 7) { - result = -1; - } - else { - result = spd_data[(device << 8) | address]; - } - } -#if 0 - print_debug("spd_read_byte("); - print_debug_hex32(device); - print_debug(", "); - print_debug_hex32(address); - print_debug(") -> "); - print_debug_hex32(result); - print_debug("\n"); -#endif - if (spd_count >= spd_fail_count) { - result = -1; - } - return result; -} - /* no specific code here. this should go away completely */ static void coherent_ht_mainboard(unsigned cpus) { @@ -341,62 +96,13 @@ #endif }; console_init(); - memreset_setup(); sdram_initialize(ARRAY_SIZE(cpu), cpu); } -static void reset_tests(void) -{ - /* Clear the results of any previous tests */ - memset(pci_register, 0, sizeof(pci_register)); - memset(spd_data, 0, sizeof(spd_data)); - spd_count = 0; - spd_fail_count = UINT_MAX; - - pci_write_config32(PCI_DEV(0, 0x18, 3), NORTHBRIDGE_CAP, - NBCAP_128Bit | - NBCAP_MP| NBCAP_BIG_MP | - /* NBCAP_ECC | NBCAP_CHIPKILL_ECC | */ - (NBCAP_MEMCLK_200MHZ << NBCAP_MEMCLK_SHIFT) | - NBCAP_MEMCTRL); - - pci_write_config32(PCI_DEV(0, 0x19, 3), NORTHBRIDGE_CAP, - NBCAP_128Bit | - NBCAP_MP| NBCAP_BIG_MP | - /* NBCAP_ECC | NBCAP_CHIPKILL_ECC | */ - (NBCAP_MEMCLK_200MHZ << NBCAP_MEMCLK_SHIFT) | - NBCAP_MEMCTRL); - -#if 0 - pci_read_config32(PCI_DEV(0, 0x18, 3), NORTHBRIDGE_CAP); -#endif -} - static void test1(void) { - reset_tests(); - - memcpy(&spd_data[0*256], spd_micron_512MB_DDR333, 256); - memcpy(&spd_data[1*256], spd_micron_512MB_DDR333, 256); -#if 0 - memcpy(&spd_data[2*256], spd_micron_512MB_DDR333, 256); - memcpy(&spd_data[3*256], spd_micron_512MB_DDR333, 256); - - memcpy(&spd_data[8*256], spd_micron_512MB_DDR333, 256); - memcpy(&spd_data[9*256], spd_micron_512MB_DDR333, 256); - memcpy(&spd_data[10*256], spd_micron_512MB_DDR333, 256); - memcpy(&spd_data[11*256], spd_micron_512MB_DDR333, 256); -#endif - raminit_main(); - -#if 0 - print_debug("spd_count: "); - print_debug_hex32(spd_count); - print_debug("\r\n"); -#endif - } @@ -407,16 +113,7 @@ if (setjmp(end_buf) != 0) { goto done; } - reset_tests(); - spd_fail_count = i; - print_debug("\r\nSPD will fail after: "); - print_debug_hex32(spd_fail_count); - print_debug(" accesses.\r\n"); - - memcpy(&spd_data[0*256], spd_micron_512MB_DDR333, 256); - memcpy(&spd_data[1*256], spd_micron_512MB_DDR333, 256); - raminit_main(); done: -- http://www.hailfinger.org/

3 2

[v2][patch] Remover waits for keyboard controller keyboard enable status
by Marc Jones 29 Sep '09

29 Sep '09

The code was waiting for status that doesn't get returned. Stefan, This should be correct. Can you try it out on a few of your problem KBCs/keyboards? Signed-off-by: Marc Jones <marcj303(a)gmail.com> -Marc -- http://marcjonesconsulting.com

2 2

[flashrom] [PATCH] SST SST49LF003A/B should be marked as TEST_OK_PR
by Peter Lemenkov 25 Sep '09

25 Sep '09

Hello All! I reported earlier, that I successfully extracted BIOS image from SST49LF003A/B, but cannot verify it yet. Nowadays, using wonderful bios_extract utility, I can provide confirmation, that everything was extracted correctly. Here is the simple patch. Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- Here are logs of extraction of BIOS from chip, and extraction of various BLOBs from BIOS image: [petro@Workplace tmp]$ sudo ~/work/flashrom/flashrom -r bios.bin flashrom v0.9.0-runknown No coreboot table found. Found chipset "Intel ICH6/ICH6R", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. Found chip "SST SST49LF003A/B" (384 KB, FWH) at physical address 0xfffa0000. === This flash part has status UNTESTED for operations: READ ERASE WRITE Please email a report to flashrom(a)coreboot.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -rV, -wV, -EV), and mention which mainboard you tested. Thanks for your help! === Reading flash... done. [petro@Workplace tmp]$ ~/work/bios_extract/bios_extract bios.bin Using file "bios.bin" (384kB) Found Award BIOS. 0x00000 ( 79260 bytes) -> 8i9me.BIN (131072 bytes) 0x1359E ( 40539 bytes) -> awardext.rom ( 57600 bytes) 0x1D3FA ( 5375 bytes) -> ACPITBL.BIN ( 14956 bytes) 0x1E8FA ( 681 bytes) -> AwardBmp.bmp ( 5772 bytes) 0x1EBA4 ( 19354 bytes) -> awardeyt.rom ( 28336 bytes) 0x2373F ( 8997 bytes) -> _EN_CODE.BIN ( 22064 bytes) 0x25A65 ( 28551 bytes) -> GSDALE.VGA ( 65536 bytes) 0x2C9ED ( 747 bytes) -> GSDALE.VBT ( 1632 bytes) 0x2CCD9 ( 30268 bytes) -> RTGBROM.LOM ( 49152 bytes) 0x34316 ( 32167 bytes) -> rtk_pxe.211 ( 53248 bytes) 0x3C0BE ( 2774 bytes) -> PPMINIT.ROM ( 6365 bytes) 0x3CB95 ( 12899 bytes) -> FINER.BIN ( 28102 bytes) 0x3FDF9 ( 6020 bytes) -> SBF.BIN ( 7974 bytes) [petro@Workplace tmp]$ -- With best regards!

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[PATCH] amd/pistachio and technexion/tim8960 devicetree.cb comments
by Carl-Daniel Hailfinger 22 Sep '09

22 Sep '09

r4534 introduced devicetree.cb in every mainboard directory, but didn't copy any comment lines before the start of the device tree. Fix up amd/pistachio and technexion/tim8960. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: LinuxBIOSv2-printk_level_side_effects/src/mainboard/amd/pistachio/devicetree.cb =================================================================== --- LinuxBIOSv2-printk_level_side_effects/src/mainboard/amd/pistachio/devicetree.cb (Revision 4614) +++ LinuxBIOSv2-printk_level_side_effects/src/mainboard/amd/pistachio/devicetree.cb (Arbeitskopie) @@ -1,3 +1,14 @@ +#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) +#Define vga_rom_address = 0xfff0000 +#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) +#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, +# 1: the system allows a PCIE link to be established on Dev2 or Dev3. +#Define gfx_dual_slot, 0: single slot, 1: dual slot +#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable +#Define gfx_tmds, 0: didn't support TMDS, 1: support +#Define gfx_compliance, 0: didn't support compliance, 1: support +#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration +#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 chip northbridge/amd/amdk8/root_complex device apic_cluster 0 on chip cpu/amd/socket_AM2 Index: LinuxBIOSv2-printk_level_side_effects/src/mainboard/technexion/tim8690/devicetree.cb =================================================================== --- LinuxBIOSv2-printk_level_side_effects/src/mainboard/technexion/tim8690/devicetree.cb (Revision 4614) +++ LinuxBIOSv2-printk_level_side_effects/src/mainboard/technexion/tim8690/devicetree.cb (Arbeitskopie) @@ -1,3 +1,14 @@ +#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) +#Define vga_rom_address = 0xfff80000 +#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) +#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, +# 1: the system allows a PCIE link to be established on Dev2 or Dev3. +#Define gfx_dual_slot, 0: single slot, 1: dual slot +#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable +#Define gfx_tmds, 0: didn't support TMDS, 1: support +#Define gfx_compliance, 0: didn't support compliance, 1: support +#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration +#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 chip northbridge/amd/amdk8/root_complex device apic_cluster 0 on chip cpu/amd/socket_S1G1 -- http://www.hailfinger.org/

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[PATCH] Auto-pick working PCI ops if none are set
by Carl-Daniel Hailfinger 22 Sep '09

22 Sep '09

Until r4340, any usage of pci_{read,write}_config{8,16,32} in coreboot_ram before the device tree was set up resulted in either a silent hang or a NULL pointer dereference. I changed the code in r4340 to die() properly with a loud error message. That still was not perfect, but at least it allowed people to see why their new ports died. Still, die() is not something developers like to see, and thus a patch to automatically pick a sensible default instead of dying was created. Of course, handling PCI access method selection automatically for fallback purposes has certain limitations before the device tree is set up. We only check if conf1 works and use conf2 as fallback. No further tests are done. This patch enables cleanups and readability improvements in early coreboot_ram code: Without this patch: dword = pci_cf8_conf1.read32(&pbus, sm_dev->bus->secondary, sm_dev->path.pci.devfn, 0x64); With this patch: dword = pci_read_config32(sm_dev, 0x64); The advantage is obvious. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: LinuxBIOSv2-asus_m2a-vm/src/devices/pci_ops.c =================================================================== --- LinuxBIOSv2-asus_m2a-vm/src/devices/pci_ops.c (Revision 4604) +++ LinuxBIOSv2-asus_m2a-vm/src/devices/pci_ops.c (Arbeitskopie) @@ -25,6 +25,9 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> +/* The only consumer of the return value of get_pbus() is ops_pci_bus(). + * ops_pci_bus() can handle being passed NULL and auto-picks working ops. + */ static struct bus *get_pbus(device_t dev) { struct bus *pbus = NULL; @@ -44,8 +47,9 @@ pbus = pbus->dev->bus; } if (!pbus || !pbus->dev || !pbus->dev->ops || !pbus->dev->ops->ops_pci_bus) { - printk_emerg("%s: Cannot find pci bus operations.\n", dev_path(dev)); - die(""); + /* This can happen before the device tree is set up completely. */ + //printk_emerg("%s: Cannot find pci bus operations.\n", dev_path(dev)); + pbus = NULL; } return pbus; } Index: LinuxBIOSv2-asus_m2a-vm/src/include/device/pci_ops.h =================================================================== --- LinuxBIOSv2-asus_m2a-vm/src/include/device/pci_ops.h (Revision 4604) +++ LinuxBIOSv2-asus_m2a-vm/src/include/device/pci_ops.h (Arbeitskopie) @@ -21,4 +21,7 @@ void pci_mmio_write_config32(device_t dev, unsigned where, uint32_t val); #endif +/* This function lives in pci_ops_auto.c */ +const struct pci_bus_operations *pci_remember_direct(void); + #endif /* PCI_OPS_H */ Index: LinuxBIOSv2-asus_m2a-vm/src/include/device/pci.h =================================================================== --- LinuxBIOSv2-asus_m2a-vm/src/include/device/pci.h (Revision 4604) +++ LinuxBIOSv2-asus_m2a-vm/src/include/device/pci.h (Arbeitskopie) @@ -97,6 +97,8 @@ if (bus && bus->dev && bus->dev->ops) { bops = bus->dev->ops->ops_pci_bus; } + if (!bops) + bops = pci_remember_direct(); return bops; } Index: LinuxBIOSv2-asus_m2a-vm/src/arch/i386/lib/pci_ops_auto.c =================================================================== --- LinuxBIOSv2-asus_m2a-vm/src/arch/i386/lib/pci_ops_auto.c (Revision 4604) +++ LinuxBIOSv2-asus_m2a-vm/src/arch/i386/lib/pci_ops_auto.c (Arbeitskopie) @@ -41,6 +41,8 @@ return 0; } +struct pci_bus_operations *pci_bus_fallback_ops = NULL; + const struct pci_bus_operations *pci_check_direct(void) { unsigned int tmp; @@ -81,11 +83,18 @@ return NULL; } +const struct pci_bus_operations *pci_remember_direct(void) +{ + if (!pci_bus_fallback_ops) + pci_bus_fallback_ops = pci_check_direct(); + return pci_bus_fallback_ops; +} + /** Set the method to be used for PCI, type I or type II */ void pci_set_method(device_t dev) { printk_info("Finding PCI configuration type.\n"); - dev->ops->ops_pci_bus = pci_check_direct(); + dev->ops->ops_pci_bus = pci_remember_direct(); post_code(0x5f); } -- http://www.hailfinger.org/

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Kconfig VGA console
by Myles Watson 17 Sep '09

17 Sep '09

Separate CONFIG_CONSOLE_VGA from CONFIG_VGA_BRIDGE_SETUP. CONSOLE_VGA means use VGA for the boot console. VGA_BRIDGE_SETUP means set the bits so that VGA can be used. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

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coreboot August 2009