coreboot June 2009

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[v2] r4347 - trunk/coreboot-v2/src/mainboard/iwill/dk8_htx
by svn＠coreboot.org 06 Jun '09

06 Jun '09

Author: oxygene Date: 2009-06-06 14:19:59 +0200 (Sat, 06 Jun 2009) New Revision: 4347 Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb Log: Make failover larger and decrease fallback's size so the total stays the same. The errata need some extra room in failover. Trivial and abuild tested Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb 2009-06-06 11:33:58 UTC (rev 4346) +++ trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb 2009-06-06 12:19:59 UTC (rev 4347) @@ -108,10 +108,10 @@ #default FALLBACK_SIZE=131072 #default FALLBACK_SIZE=0x40000 -#FALLBACK: 256K-4K -default FALLBACK_SIZE=0x3f000 -#FAILOVER: 4K -default FAILOVER_SIZE=0x01000 +#FALLBACK: 256K-8K +default FALLBACK_SIZE=0x3e000 +#FAILOVER: 8K +default FAILOVER_SIZE=0x02000 #more 1M for pgtbl default CONFIG_LB_MEM_TOPK=2048

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build service results for r4346
by coreboot information 06 Jun '09

06 Jun '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "oxygene" checked in revision 4346 to the coreboot repository. This caused the following changes: Change Log: Fix for Erratum 350 for AMD Fam10h CPUs. Compared to posted patch, there are whitespace fixes (request by Uwe), and a guard to run the erratum only on AMD_RB_C2 (request by Marc). Signed-off-by: Marco Schmidt <mashpb(a)gmail.com> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of iwill:dk8_htx is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4346&device=dk8_htx&vendor… Configuration of via:epia-m700 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4346&device=epia-m700&vend… If something broke during this checkin please be a pain in oxygene's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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build service results for r4345
by coreboot information 06 Jun '09

06 Jun '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "oxygene" checked in revision 4345 to the coreboot repository. This caused the following changes: Change Log: Fix for Erratum 343 for AMD Fam10h CPUs. Signed-off-by: Marco Schmidt <mashpb(a)gmail.com> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of iwill:dk8_htx has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4345&device=dk8_htx&vendor… Configuration of via:epia-m700 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4345&device=epia-m700&vend… If something broke during this checkin please be a pain in oxygene's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[v2] r4346 - in trunk/coreboot-v2/src/northbridge/amd/amdmct: mct wrappers
by svn＠coreboot.org 06 Jun '09

06 Jun '09

Author: oxygene Date: 2009-06-06 13:33:58 +0200 (Sat, 06 Jun 2009) New Revision: 4346 Modified: trunk/coreboot-v2/src/northbridge/amd/amdmct/mct/mct_d.c trunk/coreboot-v2/src/northbridge/amd/amdmct/wrappers/mcti_d.c Log: Fix for Erratum 350 for AMD Fam10h CPUs. Compared to posted patch, there are whitespace fixes (request by Uwe), and a guard to run the erratum only on AMD_RB_C2 (request by Marc). Signed-off-by: Marco Schmidt <mashpb(a)gmail.com> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/src/northbridge/amd/amdmct/mct/mct_d.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdmct/mct/mct_d.c 2009-06-06 11:21:52 UTC (rev 4345) +++ trunk/coreboot-v2/src/northbridge/amd/amdmct/mct/mct_d.c 2009-06-06 11:33:58 UTC (rev 4346) @@ -356,7 +356,7 @@ phyAssistedMemFnceTraining(pMCTstat, pDCTstatA); if (nv_DQSTrainCTL) { - mctHookBeforeAnyTraining(); + mctHookBeforeAnyTraining(pMCTstat, pDCTstatA); print_t("DQSTiming_D: TrainReceiverEn_D FirstPass:\n"); TrainReceiverEn_D(pMCTstat, pDCTstatA, FirstPass); Modified: trunk/coreboot-v2/src/northbridge/amd/amdmct/wrappers/mcti_d.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdmct/wrappers/mcti_d.c 2009-06-06 11:21:52 UTC (rev 4345) +++ trunk/coreboot-v2/src/northbridge/amd/amdmct/wrappers/mcti_d.c 2009-06-06 11:33:58 UTC (rev 4346) @@ -18,7 +18,7 @@ */ /* Call-backs */ - +#include <delay.h> u16 mctGet_NVbits(u8 index) { u16 val = 0; @@ -326,11 +326,79 @@ { } +static void coreDelay (void); -void mctHookBeforeAnyTraining(void) + +/* Erratum 350 */ +void vErrata350(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat) { + u8 u8Channel; + u8 u8Receiver; + u32 u32Addr; + u8 u8Valid; + u32 u32DctDev; + + // 1. dummy read for each installed DIMM */ + for (u8Channel = 0; u8Channel < 2; u8Channel++) { + // This will be 0 for vaild DIMMS, eles 8 + u8Receiver = mct_InitReceiver_D(pDCTstat, u8Channel); + + for (; u8Receiver < 8; u8Receiver += 2) { + u32Addr = mct_GetRcvrSysAddr_D(pMCTstat, pDCTstat, u8Channel, u8Receiver, &u8Valid); + + if(!u8Valid) { /* Address not supported on current CS */ + print_t("vErrara350: Address not supported on current CS\n"); + continue; + } + print_t("vErrara350: dummy read \n"); + read32_fs(u32Addr); + } + } + + print_t("vErrara350: step 2a\n"); + + /* 2. Write 0000_8000h to register F2x[1, 0]9C_xD080F0C. */ + u32DctDev = pDCTstat->dev_dct; + Set_NB32_index_wait(u32DctDev, 0x098, 0x0c, 0x00008000); + /* ^--- value + ^---F2x[1, 0]9C_x0C DRAM Phy Miscellaneous Register + ^----F2x[1, 0]98 DRAM Controller Additional Data Offset Register */ + + if(!pDCTstat->GangedMode) { + print_t("vErrara350: step 2b\n"); + Set_NB32_index_wait(u32DctDev, 0x198, 0x0c, 0x00008000); + /* ^--- value + ^---F2x[1, 0]9C_x0C DRAM Phy Miscellaneous Register + ^----F2x[1, 0]98 DRAM Controller Additional Data Offset Register */ + } + + print_t("vErrara350: step 3\n"); + /* 3. Wait at least 300 nanoseconds. */ + coreDelay(); + + print_t("vErrara350: step 4\n"); + /* 4. Write 0000_0000h to register F2x[1, 0]9C_xD080F0C. */ + Set_NB32_index_wait(u32DctDev, 0x098, 0x0c, 0x00000000); + + if(!pDCTstat->GangedMode) { + print_t("vErrara350: step 4b\n"); + Set_NB32_index_wait(u32DctDev, 0x198, 0x0c, 0x00000000); + } + + print_t("vErrara350: step 5\n"); + /* 5. Wait at least 2 microseconds. */ + coreDelay(); + } + +void mctHookBeforeAnyTraining(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) +{ + if (pDCTstatA->LogicalCPUID & AMD_RB_C2) { + vErrata350(pMCTstat, pDCTstatA); + } +} + void mctHookAfterAnyTraining(void) { }

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[v2] r4345 - in trunk/coreboot-v2/src: cpu/amd/car include/cpu/amd
by svn＠coreboot.org 06 Jun '09

06 Jun '09

Author: oxygene Date: 2009-06-06 13:21:52 +0200 (Sat, 06 Jun 2009) New Revision: 4345 Modified: trunk/coreboot-v2/src/cpu/amd/car/cache_as_ram.inc trunk/coreboot-v2/src/cpu/amd/car/post_cache_as_ram.c trunk/coreboot-v2/src/include/cpu/amd/model_10xxx_msr.h Log: Fix for Erratum 343 for AMD Fam10h CPUs. Signed-off-by: Marco Schmidt <mashpb(a)gmail.com> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/src/cpu/amd/car/cache_as_ram.inc =================================================================== --- trunk/coreboot-v2/src/cpu/amd/car/cache_as_ram.inc 2009-06-06 07:19:53 UTC (rev 4344) +++ trunk/coreboot-v2/src/cpu/amd/car/cache_as_ram.inc 2009-06-06 11:21:52 UTC (rev 4345) @@ -27,6 +27,8 @@ /* for CAR_FAM10 */ #define CacheSizeAPStack 0x400 /* 1K */ +#define MSR_FAM10 0xC001102A + #define jmp_if_k8(x) comisd %xmm2, %xmm1; jb x #define CPUID_MASK 0x0ff00f00 @@ -122,6 +124,22 @@ bts $15, %eax wrmsr + /* Erratum 343, RevGuide for Fam10h, Pub#41322 Rev. 3.33 */ + + /* read-address has to be stored in the ecx register */ + movl $MSR_FAM10, %ecx + + /* execute special read command for msr-register. Result is then in the EDX:EAX-registers (MSBs in EDX) */ + rdmsr + + /* Set bit 35 to 1 in EAX */ + bts $35, %eax + + /* write back the modified register EDX:EAX to the MSR specified in ECX */ + wrmsr + + /* Erratum 343 end */ + CAR_FAM10_out_post_errata: /* Set MtrrFixDramModEn for clear fixed mtrr */ Modified: trunk/coreboot-v2/src/cpu/amd/car/post_cache_as_ram.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/car/post_cache_as_ram.c 2009-06-06 07:19:53 UTC (rev 4344) +++ trunk/coreboot-v2/src/cpu/amd/car/post_cache_as_ram.c 2009-06-06 11:21:52 UTC (rev 4345) @@ -23,8 +23,20 @@ : "S" (src), "D" (dest), "c" ((bytes)>>2) ); } +/* Disable Erratum 343 Workaround, see RevGuide for Fam10h, Pub#41322 Rev 3.33 */ +static void vErrata343(void) +{ + msr_t msr; + unsigned int uiMask = 0xFFFFFFF7; +#ifdef BU_CFG2_MSR + msr = rdmsr(BU_CFG2_MSR); + msr.hi &= uiMask; // set bit 35 to 0 + wrmsr(BU_CFG2_MSR, msr); +#endif +} + static void post_cache_as_ram(void) { @@ -56,6 +68,8 @@ print_debug("Copying data from cache to RAM -- switching to use RAM as stack... "); /* from here don't store more data in CAR */ + vErrata343(); + #if 0 __asm__ volatile ( "pushl %eax\n\t" Modified: trunk/coreboot-v2/src/include/cpu/amd/model_10xxx_msr.h =================================================================== --- trunk/coreboot-v2/src/include/cpu/amd/model_10xxx_msr.h 2009-06-06 07:19:53 UTC (rev 4344) +++ trunk/coreboot-v2/src/include/cpu/amd/model_10xxx_msr.h 2009-06-06 11:21:52 UTC (rev 4345) @@ -26,6 +26,7 @@ #define IC_CFG_MSR 0xC0011021 #define DC_CFG_MSR 0xC0011022 #define BU_CFG_MSR 0xC0011023 +#define BU_CFG2_MSR 0xC001102A #define CPU_ID_FEATURES_MSR 0xC0011004 #define CPU_ID_HYPER_EXT_FEATURES 0xC001100d

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build service results for r4344
by coreboot information 06 Jun '09

06 Jun '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "oxygene" checked in revision 4344 to the coreboot repository. This caused the following changes: Change Log: Change the CBFS build process to use coreboot.rom instead of coreboot.strip. That fixes the normal image because the calculations for its offset in the ROM match reality again. This requires changes in CBFS configurations to minimize the bootblock size. These are also done for CBFS boards. Other than this a couple of minor fixes are in this patch: - make asus/m2v-mx_se build with abuild with a crosscompiler - move CONFIG_CBFS for hp/dl145_g3 to Options.lb as it's done everywhere else - change the default config of abuild to not provide ROM_IMAGE_SIZE values for the images in a CBFS configuration - change abuild's crosscompile autodetection to not try to use "i386-elf-i386-elf-gcc" (which is bogus) Except for the latter two abuild changes (both in util/abuild/abuild), they're available as patch set on the mailing list in a mail from 2009-06-05 titled [PATCH]es to get normal image to work again with CBFS The changes in util/abuild/abuild are trivial and abuild tested. As discussed on the list, targets/hp/dl145_g3/Config-abuild.lb is deleted, now that Config.lb works again. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Configuration of via:epia-m700 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4344&device=epia-m700&vend… If something broke during this checkin please be a pain in oxygene's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[v2] r4344 - in trunk/coreboot-v2: src/config src/mainboard/emulation/qemu-x86 src/mainboard/hp/dl145_g3 src/mainboard/kontron/986lcd-m src/mainboard/via/vt8454c targets/asus/m2v-mx_se targets/emulation/qemu-x86 targets/hp/dl145_g3 targets/kontron/986lcd-m targets/via/vt8454c util/abuild util/newconfig
by svn＠coreboot.org 06 Jun '09

06 Jun '09

Author: oxygene Date: 2009-06-06 09:19:53 +0200 (Sat, 06 Jun 2009) New Revision: 4344 Removed: trunk/coreboot-v2/targets/hp/dl145_g3/Config-abuild.lb Modified: trunk/coreboot-v2/src/config/failovercalculation.lb trunk/coreboot-v2/src/config/nofailovercalculation.lb trunk/coreboot-v2/src/config/nofailovercalculation128.lb trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Config.lb trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Options.lb trunk/coreboot-v2/src/mainboard/hp/dl145_g3/Options.lb trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Options.lb trunk/coreboot-v2/src/mainboard/via/vt8454c/Options.lb trunk/coreboot-v2/targets/asus/m2v-mx_se/Config-abuild.lb trunk/coreboot-v2/targets/emulation/qemu-x86/Config-abuild.lb trunk/coreboot-v2/targets/emulation/qemu-x86/Config-lab.lb trunk/coreboot-v2/targets/emulation/qemu-x86/Config.OLPC.lb trunk/coreboot-v2/targets/emulation/qemu-x86/Config.lb trunk/coreboot-v2/targets/hp/dl145_g3/Config.lb trunk/coreboot-v2/targets/kontron/986lcd-m/Config-abuild.lb trunk/coreboot-v2/targets/kontron/986lcd-m/Config.lb trunk/coreboot-v2/targets/via/vt8454c/Config-abuild.lb trunk/coreboot-v2/targets/via/vt8454c/Config.lb trunk/coreboot-v2/util/abuild/abuild trunk/coreboot-v2/util/newconfig/config.g Log: Change the CBFS build process to use coreboot.rom instead of coreboot.strip. That fixes the normal image because the calculations for its offset in the ROM match reality again. This requires changes in CBFS configurations to minimize the bootblock size. These are also done for CBFS boards. Other than this a couple of minor fixes are in this patch: - make asus/m2v-mx_se build with abuild with a crosscompiler - move CONFIG_CBFS for hp/dl145_g3 to Options.lb as it's done everywhere else - change the default config of abuild to not provide ROM_IMAGE_SIZE values for the images in a CBFS configuration - change abuild's crosscompile autodetection to not try to use "i386-elf-i386-elf-gcc" (which is bogus) Except for the latter two abuild changes (both in util/abuild/abuild), they're available as patch set on the mailing list in a mail from 2009-06-05 titled [PATCH]es to get normal image to work again with CBFS The changes in util/abuild/abuild are trivial and abuild tested. As discussed on the list, targets/hp/dl145_g3/Config-abuild.lb is deleted, now that Config.lb works again. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/coreboot-v2/src/config/failovercalculation.lb =================================================================== --- trunk/coreboot-v2/src/config/failovercalculation.lb 2009-06-05 23:43:11 UTC (rev 4343) +++ trunk/coreboot-v2/src/config/failovercalculation.lb 2009-06-06 07:19:53 UTC (rev 4344) @@ -10,8 +10,13 @@ default ROM_SECTION_SIZE = FALLBACK_SIZE default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) - default ROM_SECTION_OFFSET = 0 + if CONFIG_CBFS + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) + else + default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE ) + default ROM_SECTION_OFFSET = 0 + end end end Modified: trunk/coreboot-v2/src/config/nofailovercalculation.lb =================================================================== --- trunk/coreboot-v2/src/config/nofailovercalculation.lb 2009-06-05 23:43:11 UTC (rev 4343) +++ trunk/coreboot-v2/src/config/nofailovercalculation.lb 2009-06-06 07:19:53 UTC (rev 4344) @@ -6,8 +6,13 @@ default ROM_SECTION_SIZE = FALLBACK_SIZE default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 + if CONFIG_CBFS + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FALLBACK_SIZE ) + else + default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) + default ROM_SECTION_OFFSET = 0 + end end ## Modified: trunk/coreboot-v2/src/config/nofailovercalculation128.lb =================================================================== --- trunk/coreboot-v2/src/config/nofailovercalculation128.lb 2009-06-05 23:43:11 UTC (rev 4343) +++ trunk/coreboot-v2/src/config/nofailovercalculation128.lb 2009-06-06 07:19:53 UTC (rev 4344) @@ -6,8 +6,13 @@ default ROM_SECTION_SIZE = FALLBACK_SIZE default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) else - default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) - default ROM_SECTION_OFFSET = 0 + if CONFIG_CBFS + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FALLBACK_SIZE ) + else + default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) + default ROM_SECTION_OFFSET = 0 + end end ## Modified: trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Config.lb 2009-06-05 23:43:11 UTC (rev 4343) +++ trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Config.lb 2009-06-06 07:19:53 UTC (rev 4344) @@ -3,14 +3,14 @@ ## (coreboot plus bootloader) will live in the boot rom chip. ## default ROM_SIZE = 256 * 1024 -default ROM_SECTION_SIZE = ROM_SIZE +default ROM_SECTION_SIZE = ROM_IMAGE_SIZE default ROM_SECTION_OFFSET = 0 ## ## Compute the start location and size size of ## The coreboot bootloader. ## -default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) +default PAYLOAD_SIZE = ( ROM_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) ## Modified: trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Options.lb 2009-06-05 23:43:11 UTC (rev 4343) +++ trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Options.lb 2009-06-06 07:19:53 UTC (rev 4344) @@ -100,7 +100,7 @@ ## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536 -default FALLBACK_SIZE = 131072 +default FALLBACK_SIZE = ROM_IMAGE_SIZE ## ## Use a small 8K stack Modified: trunk/coreboot-v2/src/mainboard/hp/dl145_g3/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/hp/dl145_g3/Options.lb 2009-06-05 23:43:11 UTC (rev 4343) +++ trunk/coreboot-v2/src/mainboard/hp/dl145_g3/Options.lb 2009-06-06 07:19:53 UTC (rev 4344) @@ -121,9 +121,7 @@ ## ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## -#default FALLBACK_SIZE=131072 -#256K -default FALLBACK_SIZE=0x40000 +default FALLBACK_SIZE=ROM_IMAGE_SIZE #more 1M for pgtbl default CONFIG_LB_MEM_TOPK=2048 @@ -329,5 +327,9 @@ ## Select power on after power fail setting default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" +## +## CBFS +default CONFIG_CBFS=1 + ### End Options.lb end Modified: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Options.lb 2009-06-05 23:43:11 UTC (rev 4343) +++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Options.lb 2009-06-06 07:19:53 UTC (rev 4344) @@ -249,7 +249,7 @@ ### Compute the location and size of where this firmware image ### (coreboot plus bootloader) will live in the boot rom chip. ### -default FALLBACK_SIZE=131072 +default FALLBACK_SIZE=ROM_IMAGE_SIZE ## ## coreboot C code runs at this location in RAM Modified: trunk/coreboot-v2/src/mainboard/via/vt8454c/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/vt8454c/Options.lb 2009-06-05 23:43:11 UTC (rev 4343) +++ trunk/coreboot-v2/src/mainboard/via/vt8454c/Options.lb 2009-06-06 07:19:53 UTC (rev 4344) @@ -158,7 +158,7 @@ ## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. default ROM_IMAGE_SIZE = 65536 -default FALLBACK_SIZE = 131072 +default FALLBACK_SIZE = ROM_IMAGE_SIZE ## ## Use a small 8K stack Modified: trunk/coreboot-v2/targets/asus/m2v-mx_se/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/asus/m2v-mx_se/Config-abuild.lb 2009-06-05 23:43:11 UTC (rev 4343) +++ trunk/coreboot-v2/targets/asus/m2v-mx_se/Config-abuild.lb 2009-06-06 07:19:53 UTC (rev 4344) @@ -20,6 +20,10 @@ target asus_m2v-mx_se mainboard asus/m2v-mx_se +option CC="CROSSCC" +option CROSS_COMPILE="CROSS_PREFIX" +option HOSTCC="CROSS_HOSTCC" + ## ROM_SIZE is the total number of bytes allocated for coreboot use ## (normal AND fallback images and payloads). Modified: trunk/coreboot-v2/targets/emulation/qemu-x86/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/emulation/qemu-x86/Config-abuild.lb 2009-06-05 23:43:11 UTC (rev 4343) +++ trunk/coreboot-v2/targets/emulation/qemu-x86/Config-abuild.lb 2009-06-06 07:19:53 UTC (rev 4344) @@ -8,11 +8,8 @@ __COMPRESSION__ __LOGLEVEL__ -option ROM_SIZE=256*1024 - romimage "fallback" option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x10000 option COREBOOT_EXTRA_VERSION=".0" payload __PAYLOAD__ end Modified: trunk/coreboot-v2/targets/emulation/qemu-x86/Config-lab.lb =================================================================== --- trunk/coreboot-v2/targets/emulation/qemu-x86/Config-lab.lb 2009-06-05 23:43:11 UTC (rev 4343) +++ trunk/coreboot-v2/targets/emulation/qemu-x86/Config-lab.lb 2009-06-06 07:19:53 UTC (rev 4344) @@ -13,7 +13,6 @@ option IRQ_SLOT_COUNT=6 romimage "image" - option ROM_IMAGE_SIZE=0x10000 option COREBOOT_EXTRA_VERSION="-LAB" payload ../payload.elf.lzma end Modified: trunk/coreboot-v2/targets/emulation/qemu-x86/Config.OLPC.lb =================================================================== --- trunk/coreboot-v2/targets/emulation/qemu-x86/Config.OLPC.lb 2009-06-05 23:43:11 UTC (rev 4343) +++ trunk/coreboot-v2/targets/emulation/qemu-x86/Config.OLPC.lb 2009-06-06 07:19:53 UTC (rev 4344) @@ -13,7 +13,6 @@ option IRQ_SLOT_COUNT=6 romimage "image" - option ROM_IMAGE_SIZE=0x10000 option COREBOOT_EXTRA_VERSION="-OpenBIOS" payload /tmp/olpcpayload.elf end Modified: trunk/coreboot-v2/targets/emulation/qemu-x86/Config.lb =================================================================== --- trunk/coreboot-v2/targets/emulation/qemu-x86/Config.lb 2009-06-05 23:43:11 UTC (rev 4343) +++ trunk/coreboot-v2/targets/emulation/qemu-x86/Config.lb 2009-06-06 07:19:53 UTC (rev 4344) @@ -11,7 +11,6 @@ option IRQ_SLOT_COUNT=6 romimage "normal" - option ROM_IMAGE_SIZE=0x10000 option COREBOOT_EXTRA_VERSION="-GRUB2" # payload /home/stepan/core.img payload ../payload.elf Deleted: trunk/coreboot-v2/targets/hp/dl145_g3/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/hp/dl145_g3/Config-abuild.lb 2009-06-05 23:43:11 UTC (rev 4343) +++ trunk/coreboot-v2/targets/hp/dl145_g3/Config-abuild.lb 2009-06-06 07:19:53 UTC (rev 4344) @@ -1,27 +0,0 @@ -# This will make a target directory of ./VENDOR_MAINBOARD - -target VENDOR_MAINBOARD -mainboard VENDOR/MAINBOARD - -option CC="CROSSCC" -option CROSS_COMPILE="CROSS_PREFIX" -option HOSTCC="CROSS_HOSTCC" - -__COMPRESSION__ -__LOGLEVEL__ - -option ROM_SIZE=1024*(1024-32) -option FALLBACK_SIZE=1024*512 - -option CONFIG_CBFS = 1 - -romimage "fallback" - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x20000 - option XIP_ROM_SIZE=0x20000 - option COREBOOT_EXTRA_VERSION=".0-fallback" - payload __PAYLOAD__ -end - -buildrom ./coreboot.rom ROM_SIZE "fallback" - Modified: trunk/coreboot-v2/targets/hp/dl145_g3/Config.lb =================================================================== --- trunk/coreboot-v2/targets/hp/dl145_g3/Config.lb 2009-06-05 23:43:11 UTC (rev 4343) +++ trunk/coreboot-v2/targets/hp/dl145_g3/Config.lb 2009-06-06 07:19:53 UTC (rev 4344) @@ -25,11 +25,9 @@ mainboard hp/dl145_g3 option ROM_SIZE= 1024*1024 -option CONFIG_CBFS = 1 romimage "fallback" option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x20000 option XIP_ROM_SIZE=0x20000 option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" payload ./bios.bin.elf Modified: trunk/coreboot-v2/targets/kontron/986lcd-m/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/kontron/986lcd-m/Config-abuild.lb 2009-06-05 23:43:11 UTC (rev 4343) +++ trunk/coreboot-v2/targets/kontron/986lcd-m/Config-abuild.lb 2009-06-06 07:19:53 UTC (rev 4344) @@ -11,18 +11,15 @@ __LOGLEVEL__ option ROM_SIZE=1024*1024 -option FALLBACK_SIZE=1024*64 romimage "normal" option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x10000 option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end romimage "fallback" option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x10000 option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end Modified: trunk/coreboot-v2/targets/kontron/986lcd-m/Config.lb =================================================================== --- trunk/coreboot-v2/targets/kontron/986lcd-m/Config.lb 2009-06-05 23:43:11 UTC (rev 4343) +++ trunk/coreboot-v2/targets/kontron/986lcd-m/Config.lb 2009-06-06 07:19:53 UTC (rev 4344) @@ -5,20 +5,8 @@ ## (normal AND fallback images and payloads). option ROM_SIZE = 1024 * 1024 -# Use this line instead if you want to use onboard VGA: -# option ROM_SIZE = (1024 * 1024) - (64 * 1024) - -## ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image, -## not including any payload. -option ROM_IMAGE_SIZE = 128 * 1024 - -## FALLBACK_SIZE is the amount of the ROM the complete fallback image -## (including payload) will use. -option FALLBACK_SIZE = ROM_SIZE - romimage "fallback" option USE_FALLBACK_IMAGE = 1 - option ROM_IMAGE_SIZE = 144 * 1024 payload ../payload.elf end Modified: trunk/coreboot-v2/targets/via/vt8454c/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/via/vt8454c/Config-abuild.lb 2009-06-05 23:43:11 UTC (rev 4343) +++ trunk/coreboot-v2/targets/via/vt8454c/Config-abuild.lb 2009-06-06 07:19:53 UTC (rev 4344) @@ -29,14 +29,12 @@ option HOSTCC="CROSS_HOSTCC" option ROM_SIZE=512*1024 -option FALLBACK_SIZE=512*1024 __COMPRESSION__ __LOGLEVEL__ romimage "fallback" option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x15000 option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end Modified: trunk/coreboot-v2/targets/via/vt8454c/Config.lb =================================================================== --- trunk/coreboot-v2/targets/via/vt8454c/Config.lb 2009-06-05 23:43:11 UTC (rev 4343) +++ trunk/coreboot-v2/targets/via/vt8454c/Config.lb 2009-06-06 07:19:53 UTC (rev 4344) @@ -30,14 +30,12 @@ romimage "normal" option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x14000 option COREBOOT_EXTRA_VERSION=".0-normal" payload $(HOME)/payload.elf end romimage "fallback" option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x14000 option COREBOOT_EXTRA_VERSION=".0-fallback" payload $(HOME)/payload.elf end Modified: trunk/coreboot-v2/util/abuild/abuild =================================================================== --- trunk/coreboot-v2/util/abuild/abuild 2009-06-05 23:43:11 UTC (rev 4343) +++ trunk/coreboot-v2/util/abuild/abuild 2009-06-06 07:19:53 UTC (rev 4344) @@ -176,14 +176,20 @@ cat <<EOF romimage "normal" option USE_FALLBACK_IMAGE=0 +if CONFIG_CBFS +else option ROM_IMAGE_SIZE=0x17000 +end option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end romimage "fallback" option USE_FALLBACK_IMAGE=1 +if CONFIG_CBFS +else option ROM_IMAGE_SIZE=0x17000 +end option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end @@ -375,6 +381,7 @@ CC="$CC -Wa,--divide" fi CROSS_COMPILE="$TARCH-elf-" + CC=gcc echo using $CROSS_COMPILE$CC found_crosscompiler=true fi Modified: trunk/coreboot-v2/util/newconfig/config.g =================================================================== --- trunk/coreboot-v2/util/newconfig/config.g 2009-06-05 23:43:11 UTC (rev 4343) +++ trunk/coreboot-v2/util/newconfig/config.g 2009-06-06 07:19:53 UTC (rev 4344) @@ -2293,7 +2293,7 @@ # build the bootblock here. file.write("\n\tcat") for j in i.roms: - file.write(" %s/coreboot.strip " % j) + file.write(" %s/coreboot.rom " % j) file.write("> %s.bootblock\n\n" %i.name) file.write("\t./cbfstool %s create %s %s %s.bootblock\n" %(i.name, romsize, bootblocksize, i.name))

1 0

Looking for pci-e memory
by ron minnich 06 Jun '09

06 Jun '09

for a project. I need a pci-e card that has memory -- nothing else. Not having a lot of luck finding it but then I'm not even sure where to look. thanks ron

7 12

build service results for r4343
by coreboot information 06 Jun '09

06 Jun '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "hailfinger" checked in revision 4343 to the coreboot repository. This caused the following changes: Change Log: Fix non-revF K8 ram init compilation which was broken in r4341. Change all printk_raminit to printk_spew. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Myles Watson <mylesgw(a)gmail.com> Build Log: Compilation of arima:hdama has been fixed Compilation of asus:a8n_e has been fixed Compilation of asus:a8v-e_se has been fixed Compilation of broadcom:blast has been fixed Compilation of ibm:e325 has been fixed Compilation of ibm:e326 has been fixed Compilation of iwill:dk8_htx has been fixed Compilation of iwill:dk8s2 has been fixed Compilation of iwill:dk8x has been fixed Compilation of msi:ms7135 has been fixed Compilation of newisys:khepri has been fixed Compilation of sunw:ultra40 has been fixed Compilation of tyan:s2850 has been fixed Compilation of tyan:s2875 has been fixed Compilation of tyan:s2880 has been fixed Compilation of tyan:s2881 has been fixed Compilation of tyan:s2882 has been fixed Compilation of tyan:s2885 has been fixed Compilation of tyan:s2891 has been fixed Compilation of tyan:s2892 has been fixed Compilation of tyan:s2895 has been fixed Compilation of tyan:s4880 has been fixed Compilation of tyan:s4882 has been fixed Configuration of via:epia-m700 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4343&device=epia-m700&vend… If something broke during this checkin please be a pain in hailfinger's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

build service results for r4341
by coreboot information 06 Jun '09

06 Jun '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "hailfinger" checked in revision 4341 to the coreboot repository. This caused the following changes: Change Log: K8 RAM init debug messages are pretty short and sometimes cryptic. Make them a bit more verbose and hopefully more understandable. Old messages for my machine with 5 GB: RAM: 0x00400000 kB Ram3 [...] Initializing memory: done RAM: 0x00500000 kB New messages: RAM end at 0x00400000 kB Adjusting lower RAM end Lower RAM end at 0x003f0000 kB Ram3 [...] Initializing memory: done Handling memory hole at 0x00300000 (default) RAM end at 0x00500000 kB Handling memory mapped above 4 GB Upper RAM end at 0x00500000 kB Correcting memory amount mapped below 4 GB Adjusting lower RAM end Lower RAM end at 0x00300000 kB Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Myles Watson <mylesgw(a)gmail.com> Build Log: Compilation of arima:hdama has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4341&device=hdama&vendor=a… Compilation of asus:a8n_e has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4341&device=a8n_e&vendor=a… Compilation of asus:a8v-e_se has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4341&device=a8v-e_se&vendo… Compilation of broadcom:blast has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4341&device=blast&vendor=b… Compilation of ibm:e325 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4341&device=e325&vendor=ib… Compilation of ibm:e326 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4341&device=e326&vendor=ib… Compilation of iwill:dk8_htx has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4341&device=dk8_htx&vendor… Compilation of iwill:dk8s2 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4341&device=dk8s2&vendor=i… Compilation of iwill:dk8x has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4341&device=dk8x&vendor=iw… Compilation of msi:ms7135 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4341&device=ms7135&vendor=… Compilation of newisys:khepri has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4341&device=khepri&vendor=… Compilation of sunw:ultra40 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4341&device=ultra40&vendor… Compilation of tyan:s2850 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4341&device=s2850&vendor=t… Compilation of tyan:s2875 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4341&device=s2875&vendor=t… Compilation of tyan:s2880 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4341&device=s2880&vendor=t… Compilation of tyan:s2881 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4341&device=s2881&vendor=t… Compilation of tyan:s2882 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4341&device=s2882&vendor=t… Compilation of tyan:s2885 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4341&device=s2885&vendor=t… Compilation of tyan:s2891 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4341&device=s2891&vendor=t… Compilation of tyan:s2892 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4341&device=s2892&vendor=t… Compilation of tyan:s2895 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4341&device=s2895&vendor=t… Compilation of tyan:s4880 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4341&device=s4880&vendor=t… Compilation of tyan:s4882 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4341&device=s4882&vendor=t… If something broke during this checkin please be a pain in hailfinger's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

3 6

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coreboot June 2009