coreboot June 2009

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[FILO] #19: FILO don't compile with an SSP enabled gcc
by FILO 08 Jun '09

08 Jun '09

#19: FILO don't compile with an SSP enabled gcc ----------------------------------+----------------------------------------- Reporter: montjoie | Owner: somebody Type: defect | Status: new Priority: major | Milestone: Component: FILO | Version: Keywords: FILO SSP | Dependencies: Patchstatus: patch needs review | ----------------------------------+----------------------------------------- On a SSP enabled gcc ( like on gentoo-hardened) FILO won't compile with lots of: printf.c:(.text+0xdfd): undefined reference to `__guard' printf.c:(.text+0x115e): undefined reference to `__guard' printf.c:(.text+0x1177): undefined reference to `__stack_smash_handler' main/builtin.o: In function `elf_load': (.text+0x275b): undefined reference to `__guard' main/builtin.o: In function `elf_load': (.text+0x2a4a): undefined reference to `__guard' main/builtin.o: In function `elf_load': (.text+0x2a63): undefined reference to `__stack_smash_handler' main/builtin.o: In function `grub_menulst': (.text+0x3558): undefined reference to `__guard' -- Ticket URL: <http://tracker.coreboot.org/trac/filo/ticket/19> FILO <http://www.coreboot.org/FILO>

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Re: [coreboot] [v3] r1171 - in coreboot-v3: device mainboard/amd/serengeti mainboard/emulation/qemu-x86 mainboard/pcengines/alix1c mainboard/pcengines/alix2c3
by Joseph Smith 08 Jun '09

08 Jun '09

On Sun, 7 Jun 2009 19:36:43 +0200, svn(a)coreboot.org wrote: > Author: stepan > Date: 2009-06-07 19:36:43 +0200 (Sun, 07 Jun 2009) > New Revision: 1171 > > Modified: > coreboot-v3/device/Kconfig > coreboot-v3/mainboard/amd/serengeti/defconfig > coreboot-v3/mainboard/emulation/qemu-x86/defconfig > coreboot-v3/mainboard/pcengines/alix1c/defconfig > coreboot-v3/mainboard/pcengines/alix2c3/defconfig > Log: > rename VM86 to REALMODE in v3, too, as that is what it really is. > (trivial) > > Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> > Acked-by: Stefan Reinauer <stepan(a)coresystems.de> > Oops sorry about that, I forgot about the v3 boards, thanks Stefan. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

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[RFC] [flashrom] "accelerated" high-level external programmer functions and serial external programmer protocol
by Urja Rannikko 08 Jun '09

08 Jun '09

Hi all, I have a device that i would like to make a flashrom supported external programmer, an atmega168 with 3 shift registers as address bus and a DIL32 socket connected via RS232. Currently it runs it's own special software and i have special software on the PC to use it - but this combination supports (at the moment) only AT29C020 and W29C020C, so using flashrom's great database of flash chips would be great. Ok, so i would just implement a protocol for passing read and write cycles though the serial bus, sounds easy but there's a caveeat: eg. for the W29C020C there's a timeout between the bytes in the page load algo, 200us. For serial only i might be able to do that, but as my device isnt really attached to my computer's serial port (it's transmitter is busted..) but instead an serial<->ethernet adapter, there's no way one can do a "ping" in 200us, same problem applies for the USB FTDI chips i think. Even if it would work, the performance would be way too low. So, i suggest a way for external programmers to provide alternatives to the normal flash chip functions like probe_jedec, read_memmapped, write_jedec, etc. In the external programmer init function the code could/would "attach" a table to a global pointer that defines re-mappings of chip functions, and before calling a chip function flashrom would check if the pointer is non-null and then check if there's an alternative to the function that is to be used, and would call the alternative instead. The alternative function would then use it's special protocol to actually cause the function to be "executed" on the programmer device, requiring much less bandwidth and making those timing requirements easy to meet. In case there's no re-mapping of some flash chip function (i wouldnt want to implement all the flash chip functions on my external programmer at once), the external programmer would ofcourse also implement the basic read and write cycles and the original flash chip access function would try to operate using those - whether that works is a different issue. That's the first part of this "RFC" ... comments please. Then i suggest that we would try to make some kind of a "standard" for an external serial programmer protocol - it could run over the normal serial port, an USB<->serial converter chip or over an TCP socket. This would allow use to reuse a simple "serialprog" external programmer module for any serial programming devices which some of us might make. That would allow eg. to support my device, but because that is propably an one-off device (it's cheap only because the base board was free for me) make the protocol usable with other possible devices too. My suggestion would be a simple protocol in wich "calls" are the sending of a lenght word + function byte + parameters. The device would return with support byte + optional return value. eg in theory a read cycle: PC: 0x04 0x00 0x00 0xAA 0xBB 0xCC ---- 16-bit little endian lenght (of bytes after it) + function number 0 (read byte) + 24-bit address then device would return eg: DEV: 0xAA 0xBB 0xAA = I support this function, 0xBB = data returned or DEV: 0x55 = I dont support this function. The values i picked are pretty much arbitary, but the idea is that different devices could support different sets of functions and could skip over not-supported functions in the data stream, just reporting that they dont support it. The scheme would allow upto 256 different functions with arbitary parameters (per-function). I chose 24-bit addresses as i havent heard of a bios flash chip that's even near 16MiB, and because we are tight on space in the protocol. I might be into implementing this all, but it will take some time, and i would like to get it right so that it's of best possible use for all. Any input is appreciated. -- urjaman

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build service results for r4351
by coreboot information 08 Jun '09

08 Jun '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "rminnich" checked in revision 4351 to the coreboot repository. This caused the following changes: Change Log: This is transition code for cbfs to implement cbfs files at fixed addresses. I call this transitional as the approach I am taking is to add capability to cbfstool but not change code in a way that will break existing usages. Later, once we're sure nothing has broken, we can start to smooth the edges. Right now, fixed address file are only supported via the add command. There is one additional command syntax, so, example: cbfstool add rom romstrap optionrom 0xffffd000 Will add the file to that fix location for a romstrap. The assumption is that the ROM is based at the end of a 32-bit address space. As you can see from the code, that assumption can easily be over-ridden, if we ever need to, with a command option. Here is one example output result. rminnich@xcpu2:~/src/bios/coreboot-v2/util/cbfstool$ ./cbfstool x.cbf print x.cbf: 1024 kB, bootblocksize 32768, romsize 1048576, offset 0x0 Alignment: 16 bytes Name Offset Type Size h 0x0 optionrom 251 0x130 free 917120 h3 0xdffe0 optionrom 251 0xe0110 free 97960 The way this is implemented is pretty simple. I introduce a new operator, split, that splits an unallocated area into two unallocated areas. Then, allocation merely becomes a matter of 0, 1, or 2 splits: 0 split -- the free area is the exact fit 1 splits -- need to split some off the front or back 2 splits -- need to split off BOTH the front and back I think you'll be able to see what I've done. I call this transitional because, in the end state, we only need one allocate function; for now I've left two in, to make sure I don't break compatibilty. Why I like this better than ldscript approach: I like having the ROMSTRAP located by cbfs, not linker scripts. For one thing, it makes romstrap visible as a first class object. I think I would have latched onto a problem I was having much more quickly had I remembered the ROMSTRAP. It gets lost in the linker scripts. At this point, we should be able to start removing special ROMSTRAP location code from linker scripts. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Build Log: Configuration of via:epia-m700 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4351&device=epia-m700&vend… If something broke during this checkin please be a pain in rminnich's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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fixed-location entities in cbfs.
by ron minnich 08 Jun '09

08 Jun '09

Attached are what I view as a transition plan for cbfs to implement cbfs files at fixed addresses. I call this transitional as the approach I am taking is to add capability to cbfstool but not change code in a way that will break existing usages. There is one additional command syntax, so, example: cbfstool add rom romstrap optionrom 0xffffd000 Will add the file to that fix location for a romstrap. The assumption is that the ROM is based at the end of a 32-bit address space. As you can see from the code, that assumption can easily be over-ridden, if we ever need to, with a command option. Here is one example output result. rminnich@xcpu2:~/src/bios/coreboot-v2/util/cbfstool$ ./cbfstool x.cbf print x.cbf: 1024 kB, bootblocksize 32768, romsize 1048576, offset 0x0 Alignment: 16 bytes Name Offset Type Size h 0x0 optionrom 251 0x130 free 917120 h3 0xdffe0 optionrom 251 0xe0110 free 97960 The way this is implemented is pretty simple. I introduce a new operator, split, that splits an unallocated area into two unallocated areas. Then, allocation merely becomes a matter of 0, 1, or 2 splits: 0 split -- the free area is the exact fit 1 splits -- need to split some off the front or back 2 splits -- need to split off BOTH the front and back I think you'll be able to see what I've done. I call this transitional because, in the end state, we only need one allocate function; for now I've left two in, to make sure I don't break compatibilty. Why I like this better than ldscript approach: I like having the ROMSTRAP located by cbfs, not linker scripts. For one thing, it makes romstrap visible as a first class object. I think I would have latched onto a problem I was having much more quickly had I remembered the ROMSTRAP. It gets lost in the linker scripts. Anywhere, here it is.This will allow us to remove a lot of ldscript trickiness. ron

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[v2] r4351 - trunk/coreboot-v2/util/cbfstool
by svn＠coreboot.org 08 Jun '09

08 Jun '09

Author: rminnich Date: 2009-06-08 05:33:57 +0200 (Mon, 08 Jun 2009) New Revision: 4351 Modified: trunk/coreboot-v2/util/cbfstool/add.c trunk/coreboot-v2/util/cbfstool/cbfstool.h trunk/coreboot-v2/util/cbfstool/fs.c trunk/coreboot-v2/util/cbfstool/util.c Log: This is transition code for cbfs to implement cbfs files at fixed addresses. I call this transitional as the approach I am taking is to add capability to cbfstool but not change code in a way that will break existing usages. Later, once we're sure nothing has broken, we can start to smooth the edges. Right now, fixed address file are only supported via the add command. There is one additional command syntax, so, example: cbfstool add rom romstrap optionrom 0xffffd000 Will add the file to that fix location for a romstrap. The assumption is that the ROM is based at the end of a 32-bit address space. As you can see from the code, that assumption can easily be over-ridden, if we ever need to, with a command option. Here is one example output result. rminnich@xcpu2:~/src/bios/coreboot-v2/util/cbfstool$ ./cbfstool x.cbf print x.cbf: 1024 kB, bootblocksize 32768, romsize 1048576, offset 0x0 Alignment: 16 bytes Name Offset Type Size h 0x0 optionrom 251 0x130 free 917120 h3 0xdffe0 optionrom 251 0xe0110 free 97960 The way this is implemented is pretty simple. I introduce a new operator, split, that splits an unallocated area into two unallocated areas. Then, allocation merely becomes a matter of 0, 1, or 2 splits: 0 split -- the free area is the exact fit 1 splits -- need to split some off the front or back 2 splits -- need to split off BOTH the front and back I think you'll be able to see what I've done. I call this transitional because, in the end state, we only need one allocate function; for now I've left two in, to make sure I don't break compatibilty. Why I like this better than ldscript approach: I like having the ROMSTRAP located by cbfs, not linker scripts. For one thing, it makes romstrap visible as a first class object. I think I would have latched onto a problem I was having much more quickly had I remembered the ROMSTRAP. It gets lost in the linker scripts. At this point, we should be able to start removing special ROMSTRAP location code from linker scripts. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/coreboot-v2/util/cbfstool/add.c =================================================================== --- trunk/coreboot-v2/util/cbfstool/add.c 2009-06-07 14:38:32 UTC (rev 4350) +++ trunk/coreboot-v2/util/cbfstool/add.c 2009-06-08 03:33:57 UTC (rev 4351) @@ -76,7 +76,7 @@ return -1; } - ret = rom_add(rom, name, buffer, size, type); + ret = rom_add(rom, name, buffer, 0, size, type); free(buffer); return ret; @@ -165,7 +165,7 @@ } static int add_blob(struct rom *rom, const char *filename, - const char *name, int type) + const char *name, unsigned long address, int type) { void *ptr; struct stat s; @@ -195,7 +195,7 @@ return -1; } - ret = rom_add(rom, name, ptr, s.st_size, type); + ret = rom_add(rom, name, ptr, address, s.st_size, type); munmap(ptr, s.st_size); close(fd); @@ -205,7 +205,7 @@ void add_usage(void) { - printf("add FILE NAME TYPE\tAdd a component\n"); + printf("add FILE NAME TYPE [base address]\tAdd a component\n"); } void add_stage_usage(void) @@ -238,12 +238,17 @@ int add_handler(struct rom *rom, int argc, char **argv) { unsigned int type = CBFS_COMPONENT_NULL; + unsigned long address; - if (argc != 3) { + if ((argc < 3) || (argc > 4)) { add_usage(); return -1; } + if (argc > 3) { + address = strtoul(argv[3], 0, 0); + } + if (!rom_exists(rom)) { ERROR("You need to create the ROM before adding files to it\n"); return -1; @@ -278,7 +283,7 @@ } } - return add_blob(rom, argv[0], argv[1], type); + return add_blob(rom, argv[0], argv[1], address, type); } char *find_tool(char *tool) Modified: trunk/coreboot-v2/util/cbfstool/cbfstool.h =================================================================== --- trunk/coreboot-v2/util/cbfstool/cbfstool.h 2009-06-07 14:38:32 UTC (rev 4350) +++ trunk/coreboot-v2/util/cbfstool/cbfstool.h 2009-06-08 03:33:57 UTC (rev 4351) @@ -31,6 +31,10 @@ struct rom { unsigned char *name; unsigned char *ptr; + /* this will *almost* *always* be 0-rom->size, save for some really + * misdesigned systems (which have existed) + */ + unsigned long rombase; int fd; int size; @@ -51,6 +55,7 @@ #define WARN(err, args...) fprintf(stderr, "(cbfstool) W: " err, ##args) #define VERBOSE(str, args...) printf(str, ##args) +#define TRUNCATE(_v, _a) ( (_v) & ~( (_a) - 1 ) ) #define ALIGN(_v, _a) ( ( (_v) + ( (_a) - 1 ) ) & ~( (_a) - 1 ) ) /* Function prototypes */ @@ -71,7 +76,7 @@ struct cbfs_file *rom_find(struct rom *rom, int offset); struct cbfs_file *rom_find_first(struct rom *); struct cbfs_file *rom_find_next(struct rom *, struct cbfs_file *); -int rom_add(struct rom *rom, const char *name, void *, int size, int type); +int rom_add(struct rom *rom, const char *name, void *, unsigned long address, int size, int type); int rom_set_header(struct rom *rom, struct cbfs_file *c, const char*name, int size, int type); int rom_extract(struct rom *rom, const char *name, void **buf, int *size); Modified: trunk/coreboot-v2/util/cbfstool/fs.c =================================================================== --- trunk/coreboot-v2/util/cbfstool/fs.c 2009-06-07 14:38:32 UTC (rev 4350) +++ trunk/coreboot-v2/util/cbfstool/fs.c 2009-06-08 03:33:57 UTC (rev 4351) @@ -83,7 +83,130 @@ ntohl(rom->header->align)); } + +/* split + * split is a basic primitive in cbfs. Over time, it should be the main operator + * used to allocate space. For now for testing we are only using it in the + * fixed-address allocation. + * Split takes a cbfs_file and splits it into two pieces, as determined + * by the size of the file desired. Split only makes sense on CBFS_COMPONENT_NULL + * files -- splitting real files is an error, but no checking is done. + * @param file cbfs_file to split + * @param size Size of the file desired. + * @returns pointer to a cbfs_file stuct. + */ +static struct cbfs_file *split(struct rom *rom, struct cbfs_file *file, int size) +{ + struct cbfs_file *newfile = NULL; + unsigned long align = ntohl(rom->header->align); + unsigned long nextoffset, truncoffset; + unsigned long offset = ROM_OFFSET(rom, file); + /* figure out the real end of this file, and hence the size */ + /* compute where the next file is */ + nextoffset = ALIGN(offset + ntohl(file->len) + headersize(""), align); + /* compute where the end of this new file might be */ + truncoffset = ALIGN(offset + size + headersize(""), align); + /* If there is more than align bytes difference, create a new empty file */ + /* later, we can add code to merge all empty files. */ + if (nextoffset - truncoffset > align) { + unsigned int csize; + csize = headersize(""); + newfile = (struct cbfs_file *)ROM_PTR(rom, truncoffset); + rom_set_header(rom, newfile, "", + nextoffset - truncoffset - csize, CBFS_COMPONENT_NULL); + file->len = htonl(size); + } + return newfile; +} + + /** + * rom_alloc_fixed + * Given a rom, walk the headers and find the first header of type + * CBFS_COMPONENT_NULL that is >= the desired size and + * contains the (address, length) desired. + * If the CBFS_COMPONENT_NULL is 'align' bytes > size, + * create a new header of CBFS_COMPONENT_NULL following the file. + * The 'len' structure member of the desired file is initialized, but + * nothing else is. + * Simple algorithm: walk until we find an empty file that contains our area, + * and then allocate out of it. + * @param rom The rom + * @param size the size of the file needed + * @returns pointer to a cbfs_file struct. + */ +struct cbfs_file * rom_alloc_fixed(struct rom *rom, const char *name, unsigned long start, unsigned long size, int type) +{ + /* walk the rom and find an empty file with a base > base, + * and a large enough size + */ + unsigned long base, end, alen, baseoff; + unsigned int offset = ntohl(rom->header->offset); + int ret = -1; + struct cbfs_file *c = NULL; + unsigned long align = ntohl(rom->header->align); + + /* compute a base that is aligned to align */ + base = TRUNCATE(start, align); + /* have to leave room for a header! */ + base -= headersize(name); + /* get an offset for that base */ + baseoff = base - rom->rombase; + end = ALIGN(start + size, align); + alen = end - base; + while (offset < rom->fssize) { + + c = (struct cbfs_file *)ROM_PTR(rom, offset); + + if (!strcmp(c->magic, COMPONENT_MAGIC)) { + if (c->type != CBFS_COMPONENT_NULL) { + offset += ALIGN(ntohl(c->offset) + ntohl(c->len), + align); + continue; + } + /* could turn this into a function. */ + /* is the start of this file < our desired start? */ + if (offset > baseoff) + break; + /* Is this file big enough for our needs? */ + if (ntohl(c->len) >= alen){ + ret = offset; + break; + } + offset += ALIGN(ntohl(c->offset) + ntohl(c->len), + align); + } else { + fprintf(stderr, "Corrupt rom -- found no header at %d\n", offset); + exit(1); + } + } + + if (ret < 0) + return NULL; + + /* we have the base offset of our location, and we have the offset for the file we are going to + * split. Split it. + */ + if (baseoff > offset) + c = split(rom, c, baseoff - offset - headersize("")); + /* split off anything left at the end that we don't need */ + split(rom, c, size); + + c->len = htonl(size); + + strcpy(c->magic, COMPONENT_MAGIC); + + c->offset = htonl(headersize(name)); + + c->type = htonl(type); + + setname(c, name); + + return ((struct cbfs_file *)ROM_PTR(rom, ret)); +} + + +/** * rom_alloc * Given a rom, walk the headers and find the first header of type * CBFS_COMPONENT_NULL that is >= the desired size. @@ -263,11 +386,12 @@ * @param rom The rom * @param name file name * @param buffer file data + * @param address base address. 0 means 'whereever it fits' * @param size Amount of data * @param type File type * @returns -1 on failure, 0 on success */ -int rom_add(struct rom *rom, const char *name, void *buffer, int size, int type) +int rom_add(struct rom *rom, const char *name, void *buffer, unsigned long address, int size, int type) { struct cbfs_file *c; @@ -276,7 +400,10 @@ return -1; } - c = rom_alloc(rom, name, size, type); + if (address) + c = rom_alloc_fixed(rom, name, address, size, type); + else + c = rom_alloc(rom, name, size, type); if (c == NULL) { ERROR("There is no more room in this ROM\n"); Modified: trunk/coreboot-v2/util/cbfstool/util.c =================================================================== --- trunk/coreboot-v2/util/cbfstool/util.c 2009-06-07 14:38:32 UTC (rev 4350) +++ trunk/coreboot-v2/util/cbfstool/util.c 2009-06-08 03:33:57 UTC (rev 4351) @@ -158,6 +158,11 @@ } rom->size = ntohl(rom->header->romsize); + /* compute a 32-bit value of rombase. + * This does the right thing on 64-bit machines. + */ + rom->rombase = 0-rom->size; + rom->rombase &= 0xffffffff; rom->fssize = rom->size - ntohl(rom->header->bootblocksize); return 0;

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flashrom -V from Gigabyte EX58-UD4P
by Warren Turkal 08 Jun '09

08 Jun '09

I have good news. I took a huge chance and flashed my Gigabyte EX58-UD4P[1] bios with flashrom. I used the Gigabyte bios, which seems to be an LHA archive, strangely enough. I used the tip of the SVN. wt@mediakitchen:~/projects/coreboot/coreboot-v3/util/flashrom$ svn info Path: . URL: svn://coreboot.org/flashrom/trunk Repository Root: svn://coreboot.org/flashrom Repository UUID: 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 Revision: 580 Node Kind: directory Schedule: normal Last Changed Author: hailfinger Last Changed Rev: 580 Last Changed Date: 2009-06-05 13:53:07 -0700 (Fri, 05 Jun 2009) I had a successful flash, but flashrom didn't seem to be friends with my chips. I attached the output of flashrom -V as flashrom_V.txt. Here's the output of flashrom -wv ex58ud4p.f8: root@mediakitchen:~/test# ../projects/coreboot/coreboot-v3/util/flashrom/flashrom -wv ex58ud4p.f8 flashrom v0.9.0-r580 No coreboot table found. Found chipset "Intel ICH10R", enabling flash write... OK. Calibrating delay loop... OK. Found chip "SST SST25VF080B" (1024 KB) at physical address 0xfff00000. Flash image seems to be a legacy BIOS. Disabling checks. Verifying flash... FAILED at 0x000ec000! Expected=0xff, Read=0x45 A second time yielded the same FAILED. However, this worked. root@mediakitchen:~/test# ../projects/coreboot/coreboot-v3/util/flashrom/flashrom -Ewv ex58ud4p.f8 flashrom v0.9.0-r580 No coreboot table found. Found chipset "Intel ICH10R", enabling flash write... OK. Calibrating delay loop... OK. Found chip "SST SST25VF080B" (1024 KB) at physical address 0xfff00000. Erasing flash chip... SUCCESS. Verifying flash... VERIFIED. The difference is that I manually told it to erase the flash chip. The system boots properly with the new Gigabyte bios. BTW, this mobo has the Gigabyte Dual Bios technology. AFAICT, I only flashed the primary bios, but it definitely works. I also found some docs that may be useful in getting the Intel X58 chipset support at [2]. Please let me know if these are detailed enough to do anything useful. Thanks for working so hard to make a open source bios a reality. [1]http://www.gigabyte.us/Products/Motherboard/Products_Spec.aspx?ClassValue=Motherboard&ProductID=2985&ProductName=GA-EX58-UD4P [2]http://www.intel.com/products/desktop/chipsets/x58/x58-technicaldocuments… Thanks, wt

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[v3] r1171 - in coreboot-v3: device mainboard/amd/serengeti mainboard/emulation/qemu-x86 mainboard/pcengines/alix1c mainboard/pcengines/alix2c3
by svn＠coreboot.org 07 Jun '09

07 Jun '09

Author: stepan Date: 2009-06-07 19:36:43 +0200 (Sun, 07 Jun 2009) New Revision: 1171 Modified: coreboot-v3/device/Kconfig coreboot-v3/mainboard/amd/serengeti/defconfig coreboot-v3/mainboard/emulation/qemu-x86/defconfig coreboot-v3/mainboard/pcengines/alix1c/defconfig coreboot-v3/mainboard/pcengines/alix2c3/defconfig Log: rename VM86 to REALMODE in v3, too, as that is what it really is. (trivial) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: coreboot-v3/device/Kconfig =================================================================== --- coreboot-v3/device/Kconfig 2009-05-29 18:42:23 UTC (rev 1170) +++ coreboot-v3/device/Kconfig 2009-06-07 17:36:43 UTC (rev 1171) @@ -25,12 +25,12 @@ help Execute PCI/AGP option ROMs if available. This is required to enable PCI/AGP VGA plugin cards. This option is not exposed - to the user but set by the options PCI_OPTION_ROM_RUN_VM86 - , PCI_OPTION_ROM_RUN_X86EMU and PCI_OPTION_ROM_RUN_YABEL. + to the user but set by the options PCI_OPTION_ROM_RUN_REALMODE, + PCI_OPTION_ROM_RUN_X86EMU and PCI_OPTION_ROM_RUN_YABEL. choice prompt "Execute PCI Option ROMs" - default PCI_OPTION_ROM_RUN_VM86 + default PCI_OPTION_ROM_RUN_REALMODE help Execute PCI/AGP option ROMs if available. You can choose to execute PCI option ROMs natively (32bit x86 system required), @@ -63,17 +63,17 @@ All 16bit x86 code is executed in an encapsulated environment where it can not break out. -config PCI_OPTION_ROM_RUN_VM86 - bool "vm86" +config PCI_OPTION_ROM_RUN_REALMODE + bool "realmode" select PCI_OPTION_ROM_RUN depends ARCH_X86 help - If you choose this option, the virtual x86 mode "vm86" is used + If you choose this option, the x86 real mode is used to execute 16bit legacy BIOS option ROMs. - vm86 is very small, fast, and probably a little less safe than - x86emu, since it runs option ROMs on the real hardware instead - of an emulator. + The realmode trampoline code is very small, fast, and probably a + little less safe but a little more compatible than x86emu, since it + runs option ROMs on the real hardware instead of an emulator. config PCI_OPTION_ROM_RUN_NONE bool "Disabled" Modified: coreboot-v3/mainboard/amd/serengeti/defconfig =================================================================== --- coreboot-v3/mainboard/amd/serengeti/defconfig 2009-05-29 18:42:23 UTC (rev 1170) +++ coreboot-v3/mainboard/amd/serengeti/defconfig 2009-06-07 17:36:43 UTC (rev 1171) @@ -102,7 +102,7 @@ # Devices # # CONFIG_PCI_OPTION_ROM_RUN_X86EMU is not set -# CONFIG_PCI_OPTION_ROM_RUN_VM86 is not set +# CONFIG_PCI_OPTION_ROM_RUN_REALMODE is not set CONFIG_PCI_OPTION_ROM_RUN_NONE=y # Modified: coreboot-v3/mainboard/emulation/qemu-x86/defconfig =================================================================== --- coreboot-v3/mainboard/emulation/qemu-x86/defconfig 2009-05-29 18:42:23 UTC (rev 1170) +++ coreboot-v3/mainboard/emulation/qemu-x86/defconfig 2009-06-07 17:36:43 UTC (rev 1171) @@ -74,7 +74,7 @@ # CONFIG_PCI_OPTION_ROM_RUN=y # CONFIG_PCI_OPTION_ROM_RUN_X86EMU is not set -CONFIG_PCI_OPTION_ROM_RUN_VM86=y +CONFIG_PCI_OPTION_ROM_RUN_REALMODE=y # CONFIG_PCI_OPTION_ROM_RUN_NONE is not set # CONFIG_MULTIPLE_VGA_INIT is not set # CONFIG_INITIALIZE_ONBOARD_VGA_FIRST is not set Modified: coreboot-v3/mainboard/pcengines/alix1c/defconfig =================================================================== --- coreboot-v3/mainboard/pcengines/alix1c/defconfig 2009-05-29 18:42:23 UTC (rev 1170) +++ coreboot-v3/mainboard/pcengines/alix1c/defconfig 2009-06-07 17:36:43 UTC (rev 1171) @@ -82,7 +82,7 @@ # CONFIG_PCI_OPTION_ROM_RUN=y # CONFIG_PCI_OPTION_ROM_RUN_X86EMU is not set -CONFIG_PCI_OPTION_ROM_RUN_VM86=y +CONFIG_PCI_OPTION_ROM_RUN_REALMODE=y # CONFIG_PCI_OPTION_ROM_RUN_NONE is not set # CONFIG_MULTIPLE_VGA_INIT is not set # CONFIG_INITIALIZE_ONBOARD_VGA_FIRST is not set Modified: coreboot-v3/mainboard/pcengines/alix2c3/defconfig =================================================================== --- coreboot-v3/mainboard/pcengines/alix2c3/defconfig 2009-05-29 18:42:23 UTC (rev 1170) +++ coreboot-v3/mainboard/pcengines/alix2c3/defconfig 2009-06-07 17:36:43 UTC (rev 1171) @@ -75,7 +75,7 @@ # CONFIG_PCI_OPTION_ROM_RUN=y # CONFIG_PCI_OPTION_ROM_RUN_X86EMU is not set -CONFIG_PCI_OPTION_ROM_RUN_VM86=y +CONFIG_PCI_OPTION_ROM_RUN_REALMODE=y # CONFIG_PCI_OPTION_ROM_RUN_NONE is not set # CONFIG_MULTIPLE_VGA_INIT is not set # CONFIG_INITIALIZE_ONBOARD_VGA_FIRST is not set

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build service results for r4350
by coreboot information 07 Jun '09

07 Jun '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "uwe" checked in revision 4350 to the coreboot repository. This caused the following changes: Change Log: A bunch of additional EPIA-M700 cleanups and also some non-cosmetic changes: - Make get_dsdt script executable. - Rename DrivingClkPhaseData.c to driving_clk_phase_data.c. - Set proper IRQ_SLOT_COUNT value in the hope that the '14' from irq_table.c is correct. - Fix broken or incorrect #include names to increase likelyhood of a successful compile. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Configuration of via:epia-m700 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4350&device=epia-m700&vend… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[v2] r4350 - trunk/coreboot-v2/src/mainboard/via/epia-m700
by svn＠coreboot.org 07 Jun '09

07 Jun '09

Author: uwe Date: 2009-06-07 16:38:32 +0200 (Sun, 07 Jun 2009) New Revision: 4350 Added: trunk/coreboot-v2/src/mainboard/via/epia-m700/driving_clk_phase_data.c Removed: trunk/coreboot-v2/src/mainboard/via/epia-m700/DrivingClkPhaseData.c Modified: trunk/coreboot-v2/src/mainboard/via/epia-m700/Options.lb trunk/coreboot-v2/src/mainboard/via/epia-m700/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/via/epia-m700/fadt.c trunk/coreboot-v2/src/mainboard/via/epia-m700/get_dsdt trunk/coreboot-v2/src/mainboard/via/epia-m700/irq_tables.c trunk/coreboot-v2/src/mainboard/via/epia-m700/wakeup.c Log: A bunch of additional EPIA-M700 cleanups and also some non-cosmetic changes: - Make get_dsdt script executable. - Rename DrivingClkPhaseData.c to driving_clk_phase_data.c. - Set proper IRQ_SLOT_COUNT value in the hope that the '14' from irq_table.c is correct. - Fix broken or incorrect #include names to increase likelyhood of a successful compile. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Deleted: trunk/coreboot-v2/src/mainboard/via/epia-m700/DrivingClkPhaseData.c =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m700/DrivingClkPhaseData.c 2009-06-07 13:46:50 UTC (rev 4349) +++ trunk/coreboot-v2/src/mainboard/via/epia-m700/DrivingClkPhaseData.c 2009-06-07 14:38:32 UTC (rev 4350) @@ -1,237 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 One Laptop per Child, Association, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include "northbridge/via/vx800/DrivingClkPhaseData.h" - -// DQS Driving -// Reg0xE0, 0xE1 -// According to #Bank to set DRAM DQS Driving -// #Bank 1 2 3 4 5 6 7 8 -static const u8 DDR2_DQSA_Driving_Table[4] = { 0xEE, 0xEE, 0xEE, 0xEE }; -static const u8 DDR2_DQSB_Driving_Table[2] = { 0xEE, 0xEE }; - -// DQ Driving -// Reg0xE2, 0xE3 -// For DDR2: According to bank to set DRAM DQ Driving -static const u8 DDR2_DQA_Driving_Table[4] = { 0xAC, 0xAC, 0xAC, 0xAC }; -static const u8 DDR2_DQB_Driving_Table[2] = { 0xCA, 0xCA }; - -// CS Driving -// Reg0xE4, 0xE5 -// According to #Bank to set DRAM CS Driving -// DDR1 #Bank 1 2 3 4 5 6 7 8 -static const u8 DDR2_CSA_Driving_Table_x8[4] = { 0x44, 0x44, 0x44, 0x44 }; -static const u8 DDR2_CSB_Driving_Table_x8[2] = { 0x44, 0x44 }; -static const u8 DDR2_CSA_Driving_Table_x16[4] = { 0x44, 0x44, 0x44, 0x44 }; -static const u8 DDR2_CSB_Driving_Table_x16[2] = { 0x44, 0x44 }; - -// MAA Driving -// Reg0xE8, Reg0xE9 -static const u8 DDR2_MAA_Driving_Table[MA_Table][5] = { - // Chip number, 400, 533, 667 800 ;(SRAS, SCAS, SWE)RxE8 - {6, 0x86, 0x86, 0x86, 0x86}, // total MAA chips = 00 ~ 06 - {18, 0x86, 0x86, 0x86, 0x86}, // total MAA chips = 06 ~ 18 - {255, 0xDB, 0xDB, 0xDB, 0xDB}, // total MAA chips = 18 ~ -}; - -static const u8 DDR2_MAB_Driving_Table[MA_Table][2] = { - // Chip number, Value ;(SRAS, SCAS, SWE)RxE9 - {6, 0x86}, // total MAB chips = 00 ~ 06 - {18, 0x86}, // total MAB chips = 06 ~ 18 - {255, 0xDB}, // total MAB chips = 18 ~ -}; - -// DCLK Driving -// Reg0xE6, 0xE7 -// For DDR2: According to #Freq to set DRAM DCLK Driving -// freq 400M, 533M, 667M, 800M -static const u8 DDR2_DCLKA_Driving_Table[4] = { 0xFF, 0xFF, 0xFF, 0xFF }; -static const u8 DDR2_DCLKB_Driving_Table[4] = { 0xFF, 0xFF, 0xFF, 0xFF }; - -/* - * Duty cycle - * Duty cycle Control for DQ/DQS/DDRCKG in ChA & ChB - * D0F3RxEC/D0F3RxED/D0F3RxEE/D0F3RxEF - * According to DRAM frequency to control Duty Cycle - */ -static const u8 ChA_Duty_Control_DDR2[DUTY_CYCLE_REG_NUM][DUTY_CYCLE_FREQ_NUM] = { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0xEC, 0x00, 0x30, 0x30, 0x30, 0x30}, // 1Rank - {0xEE, 0x0F, 0x40, 0x40, 0x00, 0x00}, - {0xEF, 0xCF, 0x00, 0x30, 0x30, 0x30}, -}; - -static const u8 ChB_Duty_Control_DDR2[DUTY_CYCLE_REG_NUM][DUTY_CYCLE_FREQ_NUM] = { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0xED, 0x00, 0x88, 0x88, 0x84, 0x88}, // 1Rank - {0xEE, 0xF0, 0x00, 0x00, 0x00, 0x00}, - {0xEF, 0xFC, 0x00, 0x00, 0x00, 0x00}, -}; - -/* - * DRAM Clock Phase Control for FeedBack Mode - * Modify NB Reg: Rx90[7]/Rx91/Rx92/Rx93/Rx94 - * Processing: - * 1. Program VIA_NB3DRAM_REG90[7]=0b for FeedBack mode. - * 2. Program clock phase value with ChA/B DCLK enable, - * VIA_NB3DRAM_REG91[7:3]=00b - * 3. Check ChB rank #, if 0, VIA_NB3DRAM_REG91[7]=1b, to disable ChB DCLKO - * ChA DCLKO can't be disabled, so always program VIA_NB3DRAM_REG91[3]=0b. - */ -static const u8 DDR2_ChA_Clk_Phase_Table_1R[3][Clk_Phase_Table_DDR2_Width] = { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x91, 0xF8, 0x02, 0x01, 0x00, 0x07}, // 1Rank - {0x92, 0xF8, 0x04, 0x03, 0x03, 0x02}, - {0x93, 0xF8, 0x06, 0x05, 0x04, 0x03}, -}; - -static const u8 DDR2_ChB_Clk_Phase_Table_1R[3][Clk_Phase_Table_DDR2_Width] = { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x91, 0x0F, 0x20, 0x10, 0x00, 0x70}, // 1Rank - {0x92, 0x0F, 0x40, 0x30, 0x30, 0x20}, - {0x93, 0x0F, 0x60, 0x50, 0x40, 0x30}, -}; - -/* vt6413c */ -#if 0 -static const u8 DDR2_ChA_Clk_Phase_Table_2R[3][Clk_Phase_Table_DDR2_Width] = { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x91, 0xF8, 0x04, 0x03, 0x04, 0x01 }, // 1Rank - {0x92, 0xF8, 0x03, 0x06, 0x05, 0x04 }, - {0x93, 0xF8, 0x03, 0x07, 0x06, 0x05 }, -}; -#endif - -/* vt6413d */ -static const u8 DDR2_ChA_Clk_Phase_Table_2R[3][Clk_Phase_Table_DDR2_Width] = { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x91, 0xF8, 0x02, 0x01, 0x00, 0x07}, // 1Rank - {0x92, 0xF8, 0x04, 0x03, 0x03, 0x02}, - {0x93, 0xF8, 0x06, 0x05, 0x04, 0x03}, -}; - -/* - * DRAM Write Data phase control - * Modify NB Reg: Rx74/Rx75/Rx76 - */ -/* vt6413c */ -#if 0 -static const u8 DDR2_ChA_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM] = { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x74, 0xF8, 0x03, 0x04, 0x05, 0x02 }, // 1Rank - {0x75, 0xF8, 0x03, 0x04, 0x05, 0x02 }, - {0x76, 0x00, 0x10, 0x80, 0x00, 0x07 }, -}; -#endif - -/* vt6413D */ -static const u8 DDR2_ChA_WrtData_Phase_Table[WrtData_REG_NUM][WrtData_FREQ_NUM] = { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x74, 0xF8, 0x01, 0x00, 0x00, 0x07}, // 1Rank - {0x75, 0xF8, 0x01, 0x00, 0x00, 0x07}, - {0x76, 0x10, 0x80, 0x87, 0x07, 0x06}, - {0x8C, 0xFC, 0x03, 0x03, 0x03, 0x03}, -}; - -#if 0 -static const u8 DDR2_ChB_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM] = { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x74, 0x8F, 0x30, 0x40, 0x30, 0x20 }, // 1Rank - {0x75, 0x8F, 0x30, 0x40, 0x30, 0x20 }, - {0x8A, 0x00, 0x10, 0x80, 0x07, 0x07 }, -}; -#endif - -/* - * DQ/DQS Output Delay Control - * Modify NB D0F3: RxF0/RxF1/RxF2/RxF3 - */ -static const u8 DDR2_CHA_DQ_DQS_Delay_Table[4][DQ_DQS_Delay_Table_Width] = { - //RxF0 RxF1 RxF2 RxF3 - {0x00, 0x00, 0x00, 0x00}, /* DDR400 */ - {0x00, 0x00, 0x00, 0x00}, /* DDR533 */ - {0x00, 0x00, 0x00, 0x00}, /* DDR667 */ - {0x00, 0x00, 0x00, 0x00}, /* DDR800 */ -}; - -static const u8 DDR2_CHB_DQ_DQS_Delay_Table[4][DQ_DQS_Delay_Table_Width] = { - //RxF4 RxF5 RxF6 RxF7 - {0x00, 0x00, 0x00, 0x00}, /* DDR400 */ - {0x00, 0x00, 0x00, 0x00}, /* DDR533 */ - {0x00, 0x00, 0x00, 0x00}, /* DDR667 */ - {0x00, 0x00, 0x00, 0x00}, /* DDR800 */ -}; - -/* - * DQ/DQS input Capture Control - * modify NB D0F3_Reg:Rx78/Rx79/Rx7A/Rx7B - */ -/* vt6413C */ -#if 0 -static const u8 DDR2_ChA_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM ][DQS_INPUT_CAPTURE_FREQ_NUM] = { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x78, 0x00, 0x83, 0x8D, 0x87, 0x83 }, // 1Rank - {0x7A, 0xF0, 0x00, 0x00, 0x00, 0x00 }, - {0x7B, 0x00, 0x10, 0x30, 0x20, 0x10 } -}; -#endif - -/* vt6413D */ -static const u8DDR2_ChA_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM][DQS_INPUT_CAPTURE_FREQ_NUM] = { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x78, 0xC0, 0x0D, 0x07, 0x03, 0x01}, // 1Rank - {0x7A, 0xF0, 0x00, 0x00, 0x00, 0x00}, - {0x7B, 0x00, 0x34, 0x34, 0x20, 0x10} -}; - -static const u8 DDR2_ChB_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM][DQS_INPUT_CAPTURE_FREQ_NUM] = { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x79, 0x00, 0x89, 0x89, 0x87, 0x83}, // 1Rank - {0x7A, 0x0F, 0x00, 0x00, 0x00, 0x00}, - {0x8B, 0x00, 0x34, 0x34, 0x20, 0x10} -}; - -static const u8 Fixed_DQSA_1_2_Rank_Table[4][2] = { - //Rx70 Rx71 - {0x00, 0x05}, /* DDR800 */ - {0x00, 0x06}, /* DDR667 */ - {0x00, 0x04}, /* DDR533 */ - {0x00, 0x05}, /* DDR400 */ -}; - -static const u8 Fixed_DQSA_3_4_Rank_Table[4][2] = { - //Rx70 Rx71 - {0x00, 0x04}, /* DDR800 */ - {0x00, 0x04}, /* DDR667 */ - {0x00, 0x03}, /* DDR533 */ - {0x00, 0x04}, /* DDR400 */ -}; Modified: trunk/coreboot-v2/src/mainboard/via/epia-m700/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m700/Options.lb 2009-06-07 13:46:50 UTC (rev 4349) +++ trunk/coreboot-v2/src/mainboard/via/epia-m700/Options.lb 2009-06-07 14:38:32 UTC (rev 4350) @@ -120,7 +120,7 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 default HAVE_HARD_RESET = 0 default HAVE_PIRQ_TABLE = 0 -default IRQ_SLOT_COUNT = 10 # FIXME. irq_table.c says 14. +default IRQ_SLOT_COUNT = 14 default HAVE_ACPI_TABLES = 1 default HAVE_OPTION_TABLE = 1 default ROM_IMAGE_SIZE = 128 * 1024 Modified: trunk/coreboot-v2/src/mainboard/via/epia-m700/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m700/cache_as_ram_auto.c 2009-06-07 13:46:50 UTC (rev 4349) +++ trunk/coreboot-v2/src/mainboard/via/epia-m700/cache_as_ram_auto.c 2009-06-07 14:38:32 UTC (rev 4350) @@ -48,12 +48,12 @@ #include "cpu/x86/lapic/boot_cpu.c" /* This file contains the board-special SI value for raminit.c. */ -#include "mainboard/via/6413e/DrivingClkPhaseData.c" +#include "driving_clk_phase_data.c" #include "northbridge/via/vx800/raminit.h" #include "northbridge/via/vx800/raminit.c" #include "cpu/x86/car/copy_and_run.c" -#include "mainboard/via/6413e/wakeup.h" +#include "wakeup.h" /* * This acpi_is_wakeup_early_via_VX800 is from Rudolf's patch on the list: @@ -217,7 +217,7 @@ /* VT3409 no PCI-E */ 0x00, 0xFF, NB_APIC_REG(0x61), 0xFF, 0x0E, // Set Exxxxxxx as pcie mmio config range 0x00, 0xFF, NB_APIC_REG(0x60), 0xF4, 0x0B, // Support extended cfg address of pcie - //0x00, 0xFF, NB_APIC_REG(0x42), 0xF9, 0x02, // APIC Interrupt((BT_INTR)) Control + // 0x00, 0xFF, NB_APIC_REG(0x42), 0xF9, 0x02, // APIC Interrupt((BT_INTR)) Control // Set ROMSIP value by software /* @@ -248,26 +248,27 @@ 0x00, 0xFF, NB_HOST_REG(0x84), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 0) 0x00, 0xFF, NB_HOST_REG(0x85), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 1) 0x00, 0xFF, NB_HOST_REG(0x86), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 2) - 0x00, 0xFF, NB_HOST_REG(0x87), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 3) */ + 0x00, 0xFF, NB_HOST_REG(0x87), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 3) + */ // CPU Host Bus Control 0x00, 0xFF, NB_HOST_REG(0x50), 0x1F, 0x08, // Request phase ctrl: Dynamic Defer Snoop Stall Count = 8 - //0x00, 0xFF, NB_HOST_REG(0x51), 0xFF, 0x7F, // CPU I/F Ctrl-1: Disable Fast DRDY and RAW + // 0x00, 0xFF, NB_HOST_REG(0x51), 0xFF, 0x7F, // CPU I/F Ctrl-1: Disable Fast DRDY and RAW 0x00, 0xFF, NB_HOST_REG(0x51), 0xFF, 0x7C, // CPU I/F Ctrl-1: Disable Fast DRDY and RAW 0x00, 0xFF, NB_HOST_REG(0x52), 0xCB, 0xCB, // CPU I/F Ctrl-2: Enable all for performance - //0x00, 0xFF, NB_HOST_REG(0x53), 0xFF, 0x88, // Arbitration: Host/Master Occupancy timer = 8*4 HCLK + // 0x00, 0xFF, NB_HOST_REG(0x53), 0xFF, 0x88, // Arbitration: Host/Master Occupancy timer = 8*4 HCLK 0x00, 0xFF, NB_HOST_REG(0x53), 0xFF, 0x44, // Arbitration: Host/Master Occupancy timer = 4*4 HCLK 0x00, 0xFF, NB_HOST_REG(0x54), 0x1E, 0x1C, // Misc Ctrl: Enable 8QW burst Mem Access - //0x00, 0xFF, NB_HOST_REG(0x55), 0x06, 0x06, // Miscellaneous Control 2 + // 0x00, 0xFF, NB_HOST_REG(0x55), 0x06, 0x06, // Miscellaneous Control 2 0x00, 0xFF, NB_HOST_REG(0x55), 0x06, 0x04, // Miscellaneous Control 2 0x00, 0xFF, NB_HOST_REG(0x56), 0xF7, 0x63, // Write Policy 1 - //0x00, 0xFF, NB_HOST_REG(0x59), 0x3D, 0x01, // CPU Miscellaneous Control 1, enable Lowest-Priority IPL - //0x00, 0xFF, NB_HOST_REG(0x5c), 0xFF, 0x00, // CPU Miscellaneous Control 2 + // 0x00, 0xFF, NB_HOST_REG(0x59), 0x3D, 0x01, // CPU Miscellaneous Control 1, enable Lowest-Priority IPL + // 0x00, 0xFF, NB_HOST_REG(0x5c), 0xFF, 0x00, // CPU Miscellaneous Control 2 0x00, 0xFF, NB_HOST_REG(0x5D), 0xFF, 0xA2, // Write Policy 0x00, 0xFF, NB_HOST_REG(0x5E), 0xFF, 0x88, // Bandwidth Timer 0x00, 0xFF, NB_HOST_REG(0x5F), 0x46, 0x46, // CPU Misc Ctrl - // 0x00, 0xFF, NB_HOST_REG(0x90), 0xFF, 0x0B, // CPU Miscellaneous Control 3 - //0x00, 0xFF, NB_HOST_REG(0x96), 0x0B, 0x0B, // CPU Miscellaneous Control 2 + // 0x00, 0xFF, NB_HOST_REG(0x90), 0xFF, 0x0B, // CPU Miscellaneous Control 3 + // 0x00, 0xFF, NB_HOST_REG(0x96), 0x0B, 0x0B, // CPU Miscellaneous Control 2 0x00, 0xFF, NB_HOST_REG(0x96), 0x0B, 0x0A, // CPU Miscellaneous Control 2 0x00, 0xFF, NB_HOST_REG(0x98), 0xC1, 0x41, // CPU Miscellaneous Control 3 0x00, 0xFF, NB_HOST_REG(0x99), 0x0E, 0x06, // CPU Miscellaneous Control 4 @@ -285,7 +286,7 @@ #define gCom1Base 0x3f8 #define gCom2Base 0x2f8 -void EmbedComInit() +void EmbedComInit(void) { u8 ByteVal; u16 ComBase; @@ -351,9 +352,7 @@ //noharddrive - /* Set embedded COM1 I/O base = 0x3E8 */ - //D17F0RB4 - //ByteVal = 0xFD; + /* Set embedded COM1 I/O base = 0x3E8 (D17F0RB4, ByteVal = 0xFD) */ if (USE_COM1 == 1) { ByteVal = (u8) ((gCom1Base >> 3) | 0x80); pci_write_config8(PCI_DEV(0, 17, 0), 0xB4, ByteVal); @@ -362,9 +361,7 @@ pci_write_config8(PCI_DEV(0, 17, 0), 0xB2, ByteVal); } - /* Set embedded COM2 I/O base = 0x2E8. */ - //D17F0RB5 - //ByteVal = 0xDD; + /* Set embedded COM2 I/O base = 0x2E8 (D17F0RB5, ByteVal = 0xDD). */ if (USE_COM2 == 1) { ByteVal = (u8) ((gCom2Base >> 3) | 0x80); pci_write_config8(PCI_DEV(0, 17, 0), 0xB5, ByteVal); Copied: trunk/coreboot-v2/src/mainboard/via/epia-m700/driving_clk_phase_data.c (from rev 4349, trunk/coreboot-v2/src/mainboard/via/epia-m700/DrivingClkPhaseData.c) =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m700/driving_clk_phase_data.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/via/epia-m700/driving_clk_phase_data.c 2009-06-07 14:38:32 UTC (rev 4350) @@ -0,0 +1,237 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 One Laptop per Child, Association, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "northbridge/via/vx800/driving_clk_phase_data.h" + +// DQS Driving +// Reg0xE0, 0xE1 +// According to #Bank to set DRAM DQS Driving +// #Bank 1 2 3 4 5 6 7 8 +static const u8 DDR2_DQSA_Driving_Table[4] = { 0xEE, 0xEE, 0xEE, 0xEE }; +static const u8 DDR2_DQSB_Driving_Table[2] = { 0xEE, 0xEE }; + +// DQ Driving +// Reg0xE2, 0xE3 +// For DDR2: According to bank to set DRAM DQ Driving +static const u8 DDR2_DQA_Driving_Table[4] = { 0xAC, 0xAC, 0xAC, 0xAC }; +static const u8 DDR2_DQB_Driving_Table[2] = { 0xCA, 0xCA }; + +// CS Driving +// Reg0xE4, 0xE5 +// According to #Bank to set DRAM CS Driving +// DDR1 #Bank 1 2 3 4 5 6 7 8 +static const u8 DDR2_CSA_Driving_Table_x8[4] = { 0x44, 0x44, 0x44, 0x44 }; +static const u8 DDR2_CSB_Driving_Table_x8[2] = { 0x44, 0x44 }; +static const u8 DDR2_CSA_Driving_Table_x16[4] = { 0x44, 0x44, 0x44, 0x44 }; +static const u8 DDR2_CSB_Driving_Table_x16[2] = { 0x44, 0x44 }; + +// MAA Driving +// Reg0xE8, Reg0xE9 +static const u8 DDR2_MAA_Driving_Table[MA_Table][5] = { + // Chip number, 400, 533, 667 800 ;(SRAS, SCAS, SWE)RxE8 + {6, 0x86, 0x86, 0x86, 0x86}, // total MAA chips = 00 ~ 06 + {18, 0x86, 0x86, 0x86, 0x86}, // total MAA chips = 06 ~ 18 + {255, 0xDB, 0xDB, 0xDB, 0xDB}, // total MAA chips = 18 ~ +}; + +static const u8 DDR2_MAB_Driving_Table[MA_Table][2] = { + // Chip number, Value ;(SRAS, SCAS, SWE)RxE9 + {6, 0x86}, // total MAB chips = 00 ~ 06 + {18, 0x86}, // total MAB chips = 06 ~ 18 + {255, 0xDB}, // total MAB chips = 18 ~ +}; + +// DCLK Driving +// Reg0xE6, 0xE7 +// For DDR2: According to #Freq to set DRAM DCLK Driving +// freq 400M, 533M, 667M, 800M +static const u8 DDR2_DCLKA_Driving_Table[4] = { 0xFF, 0xFF, 0xFF, 0xFF }; +static const u8 DDR2_DCLKB_Driving_Table[4] = { 0xFF, 0xFF, 0xFF, 0xFF }; + +/* + * Duty cycle + * Duty cycle Control for DQ/DQS/DDRCKG in ChA & ChB + * D0F3RxEC/D0F3RxED/D0F3RxEE/D0F3RxEF + * According to DRAM frequency to control Duty Cycle + */ +static const u8 ChA_Duty_Control_DDR2[DUTY_CYCLE_REG_NUM][DUTY_CYCLE_FREQ_NUM] = { + // (And NOT) DDR800 DDR667 DDR533 DDR400 + //Reg Mask Value Value Value Value + {0xEC, 0x00, 0x30, 0x30, 0x30, 0x30}, // 1Rank + {0xEE, 0x0F, 0x40, 0x40, 0x00, 0x00}, + {0xEF, 0xCF, 0x00, 0x30, 0x30, 0x30}, +}; + +static const u8 ChB_Duty_Control_DDR2[DUTY_CYCLE_REG_NUM][DUTY_CYCLE_FREQ_NUM] = { + // (And NOT) DDR800 DDR667 DDR533 DDR400 + //Reg Mask Value Value Value Value + {0xED, 0x00, 0x88, 0x88, 0x84, 0x88}, // 1Rank + {0xEE, 0xF0, 0x00, 0x00, 0x00, 0x00}, + {0xEF, 0xFC, 0x00, 0x00, 0x00, 0x00}, +}; + +/* + * DRAM Clock Phase Control for FeedBack Mode + * Modify NB Reg: Rx90[7]/Rx91/Rx92/Rx93/Rx94 + * Processing: + * 1. Program VIA_NB3DRAM_REG90[7]=0b for FeedBack mode. + * 2. Program clock phase value with ChA/B DCLK enable, + * VIA_NB3DRAM_REG91[7:3]=00b + * 3. Check ChB rank #, if 0, VIA_NB3DRAM_REG91[7]=1b, to disable ChB DCLKO + * ChA DCLKO can't be disabled, so always program VIA_NB3DRAM_REG91[3]=0b. + */ +static const u8 DDR2_ChA_Clk_Phase_Table_1R[3][Clk_Phase_Table_DDR2_Width] = { + // (And NOT) DDR800 DDR667 DDR533 DDR400 + //Reg Mask Value Value Value Value + {0x91, 0xF8, 0x02, 0x01, 0x00, 0x07}, // 1Rank + {0x92, 0xF8, 0x04, 0x03, 0x03, 0x02}, + {0x93, 0xF8, 0x06, 0x05, 0x04, 0x03}, +}; + +static const u8 DDR2_ChB_Clk_Phase_Table_1R[3][Clk_Phase_Table_DDR2_Width] = { + // (And NOT) DDR800 DDR667 DDR533 DDR400 + //Reg Mask Value Value Value Value + {0x91, 0x0F, 0x20, 0x10, 0x00, 0x70}, // 1Rank + {0x92, 0x0F, 0x40, 0x30, 0x30, 0x20}, + {0x93, 0x0F, 0x60, 0x50, 0x40, 0x30}, +}; + +/* vt6413c */ +#if 0 +static const u8 DDR2_ChA_Clk_Phase_Table_2R[3][Clk_Phase_Table_DDR2_Width] = { + // (And NOT) DDR800 DDR667 DDR533 DDR400 + //Reg Mask Value Value Value Value + {0x91, 0xF8, 0x04, 0x03, 0x04, 0x01 }, // 1Rank + {0x92, 0xF8, 0x03, 0x06, 0x05, 0x04 }, + {0x93, 0xF8, 0x03, 0x07, 0x06, 0x05 }, +}; +#endif + +/* vt6413d */ +static const u8 DDR2_ChA_Clk_Phase_Table_2R[3][Clk_Phase_Table_DDR2_Width] = { + // (And NOT) DDR800 DDR667 DDR533 DDR400 + //Reg Mask Value Value Value Value + {0x91, 0xF8, 0x02, 0x01, 0x00, 0x07}, // 1Rank + {0x92, 0xF8, 0x04, 0x03, 0x03, 0x02}, + {0x93, 0xF8, 0x06, 0x05, 0x04, 0x03}, +}; + +/* + * DRAM Write Data phase control + * Modify NB Reg: Rx74/Rx75/Rx76 + */ +/* vt6413c */ +#if 0 +static const u8 DDR2_ChA_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM] = { + // (And NOT) DDR800 DDR667 DDR533 DDR400 + //Reg Mask Value Value Value Value + {0x74, 0xF8, 0x03, 0x04, 0x05, 0x02 }, // 1Rank + {0x75, 0xF8, 0x03, 0x04, 0x05, 0x02 }, + {0x76, 0x00, 0x10, 0x80, 0x00, 0x07 }, +}; +#endif + +/* vt6413D */ +static const u8 DDR2_ChA_WrtData_Phase_Table[WrtData_REG_NUM][WrtData_FREQ_NUM] = { + // (And NOT) DDR800 DDR667 DDR533 DDR400 + //Reg Mask Value Value Value Value + {0x74, 0xF8, 0x01, 0x00, 0x00, 0x07}, // 1Rank + {0x75, 0xF8, 0x01, 0x00, 0x00, 0x07}, + {0x76, 0x10, 0x80, 0x87, 0x07, 0x06}, + {0x8C, 0xFC, 0x03, 0x03, 0x03, 0x03}, +}; + +#if 0 +static const u8 DDR2_ChB_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM] = { + // (And NOT) DDR800 DDR667 DDR533 DDR400 + //Reg Mask Value Value Value Value + {0x74, 0x8F, 0x30, 0x40, 0x30, 0x20 }, // 1Rank + {0x75, 0x8F, 0x30, 0x40, 0x30, 0x20 }, + {0x8A, 0x00, 0x10, 0x80, 0x07, 0x07 }, +}; +#endif + +/* + * DQ/DQS Output Delay Control + * Modify NB D0F3: RxF0/RxF1/RxF2/RxF3 + */ +static const u8 DDR2_CHA_DQ_DQS_Delay_Table[4][DQ_DQS_Delay_Table_Width] = { + //RxF0 RxF1 RxF2 RxF3 + {0x00, 0x00, 0x00, 0x00}, /* DDR400 */ + {0x00, 0x00, 0x00, 0x00}, /* DDR533 */ + {0x00, 0x00, 0x00, 0x00}, /* DDR667 */ + {0x00, 0x00, 0x00, 0x00}, /* DDR800 */ +}; + +static const u8 DDR2_CHB_DQ_DQS_Delay_Table[4][DQ_DQS_Delay_Table_Width] = { + //RxF4 RxF5 RxF6 RxF7 + {0x00, 0x00, 0x00, 0x00}, /* DDR400 */ + {0x00, 0x00, 0x00, 0x00}, /* DDR533 */ + {0x00, 0x00, 0x00, 0x00}, /* DDR667 */ + {0x00, 0x00, 0x00, 0x00}, /* DDR800 */ +}; + +/* + * DQ/DQS input Capture Control + * modify NB D0F3_Reg:Rx78/Rx79/Rx7A/Rx7B + */ +/* vt6413C */ +#if 0 +static const u8 DDR2_ChA_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM ][DQS_INPUT_CAPTURE_FREQ_NUM] = { + // (And NOT) DDR800 DDR667 DDR533 DDR400 + //Reg Mask Value Value Value Value + {0x78, 0x00, 0x83, 0x8D, 0x87, 0x83 }, // 1Rank + {0x7A, 0xF0, 0x00, 0x00, 0x00, 0x00 }, + {0x7B, 0x00, 0x10, 0x30, 0x20, 0x10 } +}; +#endif + +/* vt6413D */ +static const u8DDR2_ChA_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM][DQS_INPUT_CAPTURE_FREQ_NUM] = { + // (And NOT) DDR800 DDR667 DDR533 DDR400 + //Reg Mask Value Value Value Value + {0x78, 0xC0, 0x0D, 0x07, 0x03, 0x01}, // 1Rank + {0x7A, 0xF0, 0x00, 0x00, 0x00, 0x00}, + {0x7B, 0x00, 0x34, 0x34, 0x20, 0x10} +}; + +static const u8 DDR2_ChB_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM][DQS_INPUT_CAPTURE_FREQ_NUM] = { + // (And NOT) DDR800 DDR667 DDR533 DDR400 + //Reg Mask Value Value Value Value + {0x79, 0x00, 0x89, 0x89, 0x87, 0x83}, // 1Rank + {0x7A, 0x0F, 0x00, 0x00, 0x00, 0x00}, + {0x8B, 0x00, 0x34, 0x34, 0x20, 0x10} +}; + +static const u8 Fixed_DQSA_1_2_Rank_Table[4][2] = { + //Rx70 Rx71 + {0x00, 0x05}, /* DDR800 */ + {0x00, 0x06}, /* DDR667 */ + {0x00, 0x04}, /* DDR533 */ + {0x00, 0x05}, /* DDR400 */ +}; + +static const u8 Fixed_DQSA_3_4_Rank_Table[4][2] = { + //Rx70 Rx71 + {0x00, 0x04}, /* DDR800 */ + {0x00, 0x04}, /* DDR667 */ + {0x00, 0x03}, /* DDR533 */ + {0x00, 0x04}, /* DDR400 */ +}; Modified: trunk/coreboot-v2/src/mainboard/via/epia-m700/fadt.c =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m700/fadt.c 2009-06-07 13:46:50 UTC (rev 4349) +++ trunk/coreboot-v2/src/mainboard/via/epia-m700/fadt.c 2009-06-07 14:38:32 UTC (rev 4350) @@ -23,7 +23,7 @@ #include <arch/acpi.h> #include <../../../northbridge/via/vx800/vx800.h> -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) { acpi_header_t *header = &(fadt->header); Property changes on: trunk/coreboot-v2/src/mainboard/via/epia-m700/get_dsdt ___________________________________________________________________ Added: svn:executable + * Modified: trunk/coreboot-v2/src/mainboard/via/epia-m700/irq_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m700/irq_tables.c 2009-06-07 13:46:50 UTC (rev 4349) +++ trunk/coreboot-v2/src/mainboard/via/epia-m700/irq_tables.c 2009-06-07 14:38:32 UTC (rev 4350) @@ -23,7 +23,7 @@ const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ PIRQ_VERSION, /* u16 version */ - 32 + 16 * 14, /* There can be total 14 devices on the bus */ + 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x11 << 3) | 0x0, /* Where the interrupt router lies (dev) */ 0xc20, /* IRQs devoted exclusively to PCI usage */ Modified: trunk/coreboot-v2/src/mainboard/via/epia-m700/wakeup.c =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia-m700/wakeup.c 2009-06-07 13:46:50 UTC (rev 4349) +++ trunk/coreboot-v2/src/mainboard/via/epia-m700/wakeup.c 2009-06-07 14:38:32 UTC (rev 4350) @@ -19,7 +19,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* reboot.c from Linux. */ +/* Parts of this code is taken from reboot.c from Linux. */ /* * This file mostly copied from Rudolf's S3 patch, some changes in @@ -57,12 +57,12 @@ unsigned short pad; } __attribute__ ((packed)); -static struct Xgt_desc_struct - real_mode_gdt = - { sizeof(real_mode_gdt_entries) - 1, (long)real_mode_gdt_entries }, - real_mode_idt = { -0x3ff, 0}, no_idt = { -0, 0}; +static struct Xgt_desc_struct real_mode_gdt = { + sizeof(real_mode_gdt_entries) - 1, + (long)real_mode_gdt_entries +}, +real_mode_idt = {0x3ff, 0}, +no_idt = { 0, 0 }; /* * This is 16-bit protected mode code to disable paging and the cache, @@ -85,16 +85,16 @@ * occurred; hopefully real BIOSs don't assume much. */ -// 0x66, 0x0d, 0x00, 0x00, 0x00, 0x60, /* orl $0x60000000,%eax */ +// 0x66, 0x0d, 0x00, 0x00, 0x00, 0x60, /* orl $0x60000000, %eax */ static unsigned char real_mode_switch[] = { - 0x66, 0x0f, 0x20, 0xc0, /* movl %cr0,%eax */ - 0x24, 0xfe, /* andb $0xfe,al */ - 0x66, 0x0f, 0x22, 0xc0 /* movl %eax,%cr0 */ + 0x66, 0x0f, 0x20, 0xc0, /* movl %cr0,%eax */ + 0x24, 0xfe, /* andb $0xfe,al */ + 0x66, 0x0f, 0x22, 0xc0 /* movl %eax,%cr0 */ }; static unsigned char jump_to_wakeup[] = { - 0xea, 0x00, 0x00, 0x00, 0xe0 /* ljmp $0xffff, $0x0000 */ + 0xea, 0x00, 0x00, 0x00, 0xe0 /* ljmp $0xffff, $0x0000 */ }; /* @@ -103,18 +103,17 @@ * We assume that length will aways be less that 100! */ static unsigned char show31[6] = { - 0xb0, 0x31, 0xe6, 0x80, 0xeb, 0xFA /* ljmp $0xffff,$0x0000 */ + 0xb0, 0x31, 0xe6, 0x80, 0xeb, 0xFA /* ljmp $0xffff, $0x0000 */ }; static unsigned char show32[6] = { - 0xb0, 0x32, 0xe6, 0x80, 0xeb, 0xFA /* ljmp $0xffff,$0x0000 */ + 0xb0, 0x32, 0xe6, 0x80, 0xeb, 0xFA /* ljmp $0xffff, $0x0000 */ }; void acpi_jump_wake(u32 vector) { - u32 tmp; + u32 tmp, dwEip; u16 tmpvector; - u32 dwEip; u8 Data; struct Xgt_desc_struct *wake_thunk16_Xgt_desc; @@ -137,7 +136,7 @@ jason_tsc_count_end(); unsigned long long *real_mode_gdt_entries_at_eseg; - real_mode_gdt_entries_at_eseg = WAKE_THUNK16_GDT; //copy from real_mode_gdt_entries and change limition to 1M and data base to 0; + real_mode_gdt_entries_at_eseg = WAKE_THUNK16_GDT; /* Copy from real_mode_gdt_entries and change limition to 1M and data base to 0; */ real_mode_gdt_entries_at_eseg[0] = 0x0000000000000000ULL; /* Null descriptor */ real_mode_gdt_entries_at_eseg[1] = 0x000f9a000000ffffULL; /* 16-bit real-mode 1M code at 0x00000000 */ real_mode_gdt_entries_at_eseg[2] = 0x000f93000000ffffULL; /* 16-bit real-mode 1M data at 0x00000000 */ @@ -150,24 +149,25 @@ wake_thunk16_Xgt_desc[2].size = 0; wake_thunk16_Xgt_desc[2].address = 0; - /*added this code to get current value of EIP - */ - __asm__ volatile ("calll geip\n\t" - "geip: \n\t" "popl %0\n\t":"=a" (dwEip) - ); + /* Added this code to get current value of EIP. */ + __asm__ volatile ( + "calll geip\n\t" + "geip: \n\t" + "popl %0\n\t" + : "=a" (dwEip) + ); - unsigned char *dest; - unsigned char *src; + unsigned char *dest, *src; src = (unsigned char *)dwEip; dest = WAKE_RECOVER1M_CODE; u32 i; for (i = 0; i < 0x200; i++) dest[i] = src[i]; - __asm__ __volatile__("ljmp $0x0010,%0" //08 error + __asm__ __volatile__("ljmp $0x0010,%0" /* 08 error */ ::"i"((void *)(WAKE_RECOVER1M_CODE + 0x20))); - /*added 0x20 "nop" to make sure the ljmp will not jump then halt */ + /* Added 0x20 "nop" to make sure the ljmp will not jump then halt. */ asm volatile ("nop"); asm volatile ("nop"); asm volatile ("nop"); @@ -202,104 +202,126 @@ asm volatile ("nop"); __asm__ volatile ( - /* set new esp, maybe ebp should not equal to esp?, - due to the variable in acpi_jump_wake?, anyway, this may be not a big problem. - and I didnt clear the area (ef000+-0x200) to zero. - */ - "movl %0, %%ebp\n\t" - "movl %0, %%esp\n\t"::"a" (WAKE_THUNK16_STACK) - ); + /* + * Set new esp, maybe ebp should not equal to esp?, due to the + * variable in acpi_jump_wake?, anyway, this may be not a big + * problem. and I didn't clear the area (ef000+-0x200) to zero. + */ + "movl %0, %%ebp\n\t" + "movl %0, %%esp\n\t"::"a" (WAKE_THUNK16_STACK) + ); - /* added this - only "src" and "dest" use the new stack, and the esp maybe also used in resumevector + /* + * Only "src" and "dest" use the new stack, and the esp maybe also + * used in resumevector. */ -#if PAYLOAD_IS_SEABIOS==1 - // WAKE_MEM_INFO inited in get_set_top_available_mem in tables.c +#if PAYLOAD_IS_SEABIOS == 1 + /* WAKE_MEM_INFO inited in get_set_top_available_mem in tables.c. */ src = (unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 - 0x100000); dest = 0; - for (i = 0; i < 0xa0000; i++) //if recovered 0-e0000, then when resume, before winxp turn on the desktop screen ,there is gray background which last 1sec. + + /* + * If recovered 0-e0000, then when resume, before WinXP turn on the + * desktop screen, there is gray background which last 1sec. + */ + for (i = 0; i < 0xa0000; i++) dest[i] = src[i]; - /*__asm__ volatile ( - "movl %0, %%esi\n\t" - "movl $0, %%edi\n\t" - "movl $0xa0000, %%ecx\n\t" - "shrl $2, %%ecx\n\t" - "rep movsd\n\t" - ::"a"(src) - );*/ - src = - (unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 - 0x100000 + - 0xc0000); - //dest = 0xc0000; - //for (i = 0; i < 0x20000; i++) - // dest[i] = src[i]; - /* __asm__ volatile ( - "movl %0, %%esi\n\t" - "movl $0xc0000, %%edi\n\t" - "movl $0x20000, %%ecx\n\t" - "shrl $2, %%ecx\n\t" - "rep movsd\n\t" - ::"a"(src) - ); */ - src = - (unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 - 0x100000 + - 0xe0000 + WAKE_SPECIAL_SIZE); - //dest = 0xf0000; - //for (i = 0; i < 0x10000; i++) - // dest[i] = src[i]; - __asm__ volatile ("movl %0, %%esi\n\t" - "movl %1, %%edi\n\t" - "movl %2, %%ecx\n\t" - "shrl $2, %%ecx\n\t" - "rep movsd\n\t"::"r" (src), - "r"(0xe0000 + WAKE_SPECIAL_SIZE), - "r"(0x10000 - WAKE_SPECIAL_SIZE) - ); +#if 0 + __asm__ volatile ( + "movl %0, %%esi\n\t" + "movl $0, %%edi\n\t" + "movl $0xa0000, %%ecx\n\t" + "shrl $2, %%ecx\n\t" + "rep movsd\n\t" + ::"a"(src) + ); +#endif + src = (unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 + - 0x100000 + 0xc0000); - src = - (unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 - 0x100000 + - 0xf0000); - //dest = 0xf0000; - //for (i = 0; i < 0x10000; i++) - // dest[i] = src[i]; - __asm__ volatile ("movl %0, %%esi\n\t" - "movl $0xf0000, %%edi\n\t" - "movl $0x10000, %%ecx\n\t" - "shrl $2, %%ecx\n\t" "rep movsd\n\t"::"a" (src) - ); +#if 0 + dest = 0xc0000; + for (i = 0; i < 0x20000; i++) + dest[i] = src[i]; + __asm__ volatile ( + "movl %0, %%esi\n\t" + "movl $0xc0000, %%edi\n\t" + "movl $0x20000, %%ecx\n\t" + "shrl $2, %%ecx\n\t" + "rep movsd\n\t" + ::"a"(src) + ); +#endif + + src = (unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 + - 0x100000 + 0xe0000 + WAKE_SPECIAL_SIZE); + + /* dest = 0xf0000; */ + /* for (i = 0; i < 0x10000; i++) */ + /* dest[i] = src[i]; */ + __asm__ volatile ( + "movl %0, %%esi\n\t" + "movl %1, %%edi\n\t" + "movl %2, %%ecx\n\t" + "shrl $2, %%ecx\n\t" + "rep movsd\n\t"::"r" (src), + "r"(0xe0000 + WAKE_SPECIAL_SIZE), + "r"(0x10000 - WAKE_SPECIAL_SIZE) + ); + + src = (unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 + - 0x100000 + 0xf0000); + /* dest = 0xf0000; */ + /* for (i = 0; i < 0x10000; i++) */ + /* dest[i] = src[i]; */ + __asm__ volatile ( + "movl %0, %%esi\n\t" + "movl $0xf0000, %%edi\n\t" + "movl $0x10000, %%ecx\n\t" + "shrl $2, %%ecx\n\t" "rep movsd\n\t"::"a" (src) + ); + asm volatile ("wbinvd"); #endif /* Set up the IDT for real mode. */ asm volatile ("lidt %0"::"m" (wake_thunk16_Xgt_desc[1])); - /* Set up a GDT from which we can load segment descriptors for real - mode. The GDT is not used in real mode; it is just needed here to - prepare the descriptors. */ + /* + * Set up a GDT from which we can load segment descriptors for real + * mode. The GDT is not used in real mode; it is just needed here to + * prepare the descriptors. + */ asm volatile ("lgdt %0"::"m" (wake_thunk16_Xgt_desc[0])); - /* Load the data segment registers, and thus the descriptors ready for - real mode. The base address of each segment is 0x100, 16 times the - selector value being loaded here. This is so that the segment - registers don't have to be reloaded after switching to real mode: - the values are consistent for real mode operation already. */ + /* + * Load the data segment registers, and thus the descriptors ready for + * real mode. The base address of each segment is 0x100, 16 times the + * selector value being loaded here. This is so that the segment + * registers don't have to be reloaded after switching to real mode: + * the values are consistent for real mode operation already. + */ + __asm__ __volatile__( + "movl $0x0010,%%eax\n" + "\tmovl %%eax,%%ds\n" + "\tmovl %%eax,%%es\n" + "\tmovl %%eax,%%fs\n" + "\tmovl %%eax,%%gs\n" + "\tmovl %%eax,%%ss":::"eax" + ); - __asm__ __volatile__("movl $0x0010,%%eax\n" - "\tmovl %%eax,%%ds\n" - "\tmovl %%eax,%%es\n" - "\tmovl %%eax,%%fs\n" - "\tmovl %%eax,%%gs\n" "\tmovl %%eax,%%ss":::"eax"); + /* + * Jump to the 16-bit code that we copied earlier. It disables paging + * and the cache, switches to real mode, and jumps to the BIOS reset + * entry point. + */ - /* Jump to the 16-bit code that we copied earlier. It disables paging - and the cache, switches to real mode, and jumps to the BIOS reset - entry point. */ - - __asm__ - __volatile__("ljmp $0x0008,%0"::"i" - ((void *)(WAKE_THUNK16_ADDR - - sizeof(real_mode_switch) - 100))); + __asm__ __volatile__( + "ljmp $0x0008,%0"::"i" + ((void *)(WAKE_THUNK16_ADDR - sizeof(real_mode_switch) - 100)) + ); } /* -*- linux-c -*- ------------------------------------------------------- * @@ -318,7 +340,7 @@ * Enable A20 gate (return -1 on failure) */ -//#include "boot.h" +// #include "boot.h" #define MAX_8042_LOOPS 100000 @@ -429,9 +451,10 @@ /* Try enabling A20 through the keyboard controller */ empty_8042(); -//if (a20_test_short()) -// return 0; /* BIOS worked, but with delayed reaction */ + // if (a20_test_short()) + // return 0; /* BIOS worked, but with delayed reaction */ + enable_a20_kbc(); if (a20_test_long()) return 0;

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coreboot June 2009