coreboot May 2009

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build service results for r4299
by coreboot information 26 May '09

26 May '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 4299 to the coreboot repository. This caused the following changes: Change Log: Cosmetic cbfstool update (trivial) * remove some dead code * fix indentation * comment in some destructors and fix some other warnings * use HOSTCC instead of CC (not all the way cosmetic, but very simple) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of asus:mew-am is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4299&device=mew-am&vendor=… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[v2] r4301 - trunk/coreboot-v2/src/arch/i386/boot
by svn＠coreboot.org 26 May '09

26 May '09

Author: stepan Date: 2009-05-26 14:33:52 +0200 (Tue, 26 May 2009) New Revision: 4301 Modified: trunk/coreboot-v2/src/arch/i386/boot/acpi.c Log: acpi.c: add a cast to remove warning (trivial) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/src/arch/i386/boot/acpi.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/acpi.c 2009-05-26 12:33:06 UTC (rev 4300) +++ trunk/coreboot-v2/src/arch/i386/boot/acpi.c 2009-05-26 12:33:52 UTC (rev 4301) @@ -495,7 +495,7 @@ return NULL; printk_debug("FADT found at %p\n", fadt); - facs = fadt->firmware_ctrl; + facs = (acpi_facs_t *)fadt->firmware_ctrl; if (facs == NULL) { printk_debug("No FACS found, wake up from S3 not possible.\n");

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[v2] r4300 - trunk/coreboot-v2/src/arch/i386/lib
by svn＠coreboot.org 26 May '09

26 May '09

Author: stepan Date: 2009-05-26 14:33:06 +0200 (Tue, 26 May 2009) New Revision: 4300 Modified: trunk/coreboot-v2/src/arch/i386/lib/cpu.c Log: remove some dead code from cpu.c (trivial) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/src/arch/i386/lib/cpu.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/lib/cpu.c 2009-05-26 12:22:10 UTC (rev 4299) +++ trunk/coreboot-v2/src/arch/i386/lib/cpu.c 2009-05-26 12:33:06 UTC (rev 4300) @@ -134,11 +134,9 @@ static void identify_cpu(struct device *cpu) { char vendor_name[16]; - int cpuid_level; int i; vendor_name[0] = '\0'; /* Unset */ - cpuid_level = -1; /* Maximum supported CPUID level, -1=no CPUID */ /* Find the id and vendor_name */ if (!have_cpuid_p()) { @@ -158,6 +156,7 @@ } } if (have_cpuid_p()) { + int cpuid_level; struct cpuid_result result; result = cpuid(0x00000000); cpuid_level = result.eax;

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[v2] r4299 - in trunk/coreboot-v2/util/cbfstool: . tools tools/lzma tools/lzma/C/7zip/Compress/LZ tools/lzma/C/Common
by svn＠coreboot.org 26 May '09

26 May '09

Author: stepan Date: 2009-05-26 14:22:10 +0200 (Tue, 26 May 2009) New Revision: 4299 Modified: trunk/coreboot-v2/util/cbfstool/Makefile trunk/coreboot-v2/util/cbfstool/resize.c trunk/coreboot-v2/util/cbfstool/tools/Makefile trunk/coreboot-v2/util/cbfstool/tools/cbfs-mkstage.c trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZ/IMatchFinder.h trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/MyWindows.h trunk/coreboot-v2/util/cbfstool/tools/lzma/minilzma.cc Log: Cosmetic cbfstool update (trivial) * remove some dead code * fix indentation * comment in some destructors and fix some other warnings * use HOSTCC instead of CC (not all the way cosmetic, but very simple) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/util/cbfstool/Makefile =================================================================== --- trunk/coreboot-v2/util/cbfstool/Makefile 2009-05-23 22:02:31 UTC (rev 4298) +++ trunk/coreboot-v2/util/cbfstool/Makefile 2009-05-26 12:22:10 UTC (rev 4299) @@ -8,7 +8,9 @@ OBJ=$(COMMANDS) cbfstool.o util.o fs.o INC=cbfstool.h cbfs.h -CC=gcc +HOSTCC ?= gcc +HOSTCXX ?= g++ + CFLAGS=-g -Wall -W -Werror DESTDIR ?= /usr/local/bin @@ -16,7 +18,7 @@ all: $(obj)/cbfstool $(obj)/tools/cbfs-mkpayload $(obj)/tools/cbfs-mkstage $(obj)/cbfstool: $(patsubst %,$(obj)/%,$(OBJ)) - $(CC) -o $@ $(patsubst %,$(obj)/%,$(OBJ)) + $(HOSTCC) -o $@ $(patsubst %,$(obj)/%,$(OBJ)) tobj = $(obj)/tools tsrc = $(shell pwd)/tools @@ -24,7 +26,7 @@ include $(tsrc)/Makefile $(obj)/%.o: %.c $(INC) - $(CC) $(CFLAGS) -c -o $@ $< + $(HOSTCC) $(CFLAGS) -c -o $@ $< install: $(obj)/cbfstool $(obj)/tools/cbfs-mkpayload $(obj)/tools/cbfs-mkstage @ install -d $(DESTDIR) Modified: trunk/coreboot-v2/util/cbfstool/resize.c =================================================================== --- trunk/coreboot-v2/util/cbfstool/resize.c 2009-05-23 22:02:31 UTC (rev 4298) +++ trunk/coreboot-v2/util/cbfstool/resize.c 2009-05-26 12:22:10 UTC (rev 4299) @@ -95,7 +95,6 @@ /* The first entry doesn't have to move */ c = rom_find(rom, rom->header->offset); - offset = rom->header->offset; while (c) { struct cbfs_file *n = rom_find_next(rom, c); @@ -105,10 +104,8 @@ break; /* Calculate a new location for the entry */ - next = - ROM_OFFSET(rom, - c) + ALIGN(ntohl(c->offset) + - ntohl(c->len), align); + next = ROM_OFFSET(rom, c) + + ALIGN(ntohl(c->offset) + ntohl(c->len), align); /* Copy the next entry there */ memmove(ROM_PTR(rom, next), n, @@ -116,8 +113,10 @@ c = (struct cbfs_file *)ROM_PTR(rom, next); - /* If the previous header wasn't overwritten by the change, - corrupt the header so we don't accidently find it */ + /* If the previous header wasn't overwritten by + * the change, corrupt the header so we don't + * accidently find it + */ if (ROM_OFFSET(rom, n) > next + ntohl(c->len) + ntohl(c->offset)) Modified: trunk/coreboot-v2/util/cbfstool/tools/Makefile =================================================================== --- trunk/coreboot-v2/util/cbfstool/tools/Makefile 2009-05-23 22:02:31 UTC (rev 4298) +++ trunk/coreboot-v2/util/cbfstool/tools/Makefile 2009-05-26 12:22:10 UTC (rev 4299) @@ -12,13 +12,13 @@ COMMON = common.o compress.o $(LZMA_OBJ) $(tobj)/cbfs-mkstage: $(tobj)/cbfs-mkstage.o $(patsubst %,$(tobj)/%,$(COMMON)) - $(CXX) $(CFLAGS) -o $@ $^ + $(HOSTCXX) $(CFLAGS) -o $@ $^ $(tobj)/cbfs-mkpayload: $(tobj)/cbfs-mkpayload.o $(patsubst %,$(tobj)/%,$(COMMON)) - $(CXX) $(CFLAGS) -o $@ $^ + $(HOSTCXX) $(CFLAGS) -o $@ $^ $(tobj)/%.o: %.c - $(CC) $(CFLAGS) -c -o $@ $< + $(HOSTCC) $(CFLAGS) -c -o $@ $< tools-clean: rm -f $(tobj)/cbfs-mkpayload.o $(tobj)/cbfs-mkstage.o $(patsubst %,$(tobj)/%,$(COMMON)) Modified: trunk/coreboot-v2/util/cbfstool/tools/cbfs-mkstage.c =================================================================== --- trunk/coreboot-v2/util/cbfstool/tools/cbfs-mkstage.c 2009-05-23 22:02:31 UTC (rev 4298) +++ trunk/coreboot-v2/util/cbfstool/tools/cbfs-mkstage.c 2009-05-26 12:22:10 UTC (rev 4299) @@ -34,7 +34,6 @@ { Elf32_Phdr *phdr; Elf32_Ehdr *ehdr = (Elf32_Ehdr *) input; - Elf32_Shdr *shdr; char *header, *buffer; unsigned char *out; @@ -47,7 +46,6 @@ header = (char *)ehdr; phdr = (Elf32_Phdr *) & (header[ehdr->e_phoff]); - shdr = (Elf32_Shdr *) & (header[ehdr->e_shoff]); /* Now, regular headers - we only care about PT_LOAD headers, * because thats what we're actually going to load Modified: trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZ/IMatchFinder.h =================================================================== --- trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZ/IMatchFinder.h 2009-05-23 22:02:31 UTC (rev 4298) +++ trunk/coreboot-v2/util/cbfstool/tools/lzma/C/7zip/Compress/LZ/IMatchFinder.h 2009-05-26 12:22:10 UTC (rev 4299) @@ -26,7 +26,7 @@ struct IMatchFinderSetNumPasses { - //virtual ~IMatchFinderSetNumPasses(){} + virtual ~IMatchFinderSetNumPasses(){} virtual void SetNumPasses(UInt32 numPasses) PURE; }; Modified: trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/MyWindows.h =================================================================== --- trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/MyWindows.h 2009-05-23 22:02:31 UTC (rev 4298) +++ trunk/coreboot-v2/util/cbfstool/tools/lzma/C/Common/MyWindows.h 2009-05-26 12:22:10 UTC (rev 4299) @@ -101,7 +101,7 @@ struct IUnknown { - //virtual ~IUnknown() {} + virtual ~IUnknown() {} STDMETHOD(QueryInterface) (REFIID iid, void **outObject) PURE; STDMETHOD_(ULONG, AddRef)() PURE; STDMETHOD_(ULONG, Release)() PURE; Modified: trunk/coreboot-v2/util/cbfstool/tools/lzma/minilzma.cc =================================================================== --- trunk/coreboot-v2/util/cbfstool/tools/lzma/minilzma.cc 2009-05-23 22:02:31 UTC (rev 4298) +++ trunk/coreboot-v2/util/cbfstool/tools/lzma/minilzma.cc 2009-05-26 12:22:10 UTC (rev 4299) @@ -303,12 +303,12 @@ void do_lzma_uncompress(char *dst, int dst_len, char *src, int src_len) { std::vector<unsigned char> result; result = LZMADeCompress(std::vector<unsigned char>(src, src + src_len)); - if (result.size() <= dst_len) + if (result.size() <= (SizeT)dst_len) std::memcpy(dst, &result[0], result.size()); else { fprintf(stderr, "Not copying %d bytes to %d-byte buffer!\n", - result.size(), dst_len); + (unsigned int)result.size(), dst_len); exit(1); } }

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[flashrom] r548 - trunk
by svn＠coreboot.org 26 May '09

26 May '09

Author: libv Date: 2009-05-26 11:48:28 +0200 (Tue, 26 May 2009) New Revision: 548 Modified: trunk/board_enable.c trunk/chipset_enable.c Log: Add NForce2 chipset enable. While the other chipset enables for nvidia could potentially also work, this one, by not touching other bits, seems like the safest solution. Uwe tested this on his Asus A7N8X Deluxe, so hopefully the A7N8X-E (reporter unknown) is now no longer an issue. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-05-25 23:26:50 UTC (rev 547) +++ trunk/board_enable.c 2009-05-26 09:48:28 UTC (rev 548) @@ -717,6 +717,7 @@ { "ASUS", "P2B-F", }, { "ASUS", "P2B-D", }, { "ASUS", "P2B-DS", }, + { "ASUS", "A7N8X Deluxe", }, { "ASUS", "A7V400-MX", }, { "ASUS", "A7V8X-MX", }, { "ASUS", "P4B266", }, @@ -781,7 +782,6 @@ const struct board_info boards_bad[] = { /* Verified non-working boards (for now). */ { "Abit", "IS-10", }, - { "ASUS", "A7N8X-E Deluxe", }, { "ASUS", "MEW-AM", }, { "ASUS", "MEW-VM", }, { "ASUS", "P3B-F", }, Modified: trunk/chipset_enable.c =================================================================== --- trunk/chipset_enable.c 2009-05-25 23:26:50 UTC (rev 547) +++ trunk/chipset_enable.c 2009-05-26 09:48:28 UTC (rev 548) @@ -769,6 +769,19 @@ return 0; } +static int enable_flash_nvidia_nforce2(struct pci_dev *dev, const char *name) +{ + uint8_t tmp; + + pci_write_byte(dev, 0x92, 0); + + tmp = pci_read_byte(dev, 0x6d); + tmp |= 0x01; + pci_write_byte(dev, 0x6d, tmp); + + return 0; +} + static int enable_flash_ck804(struct pci_dev *dev, const char *name) { uint8_t old, new; @@ -981,6 +994,7 @@ {0x8086, 0x122e, OK, "Intel", "PIIX", enable_flash_piix4}, {0x10de, 0x0050, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* LPC */ {0x10de, 0x0051, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* Pro */ + {0x10de, 0x0060, OK, "NVIDIA", "NForce2", enable_flash_nvidia_nforce2}, /* Slave, should not be here, to fix known bug for A01. */ {0x10de, 0x00d3, OK, "NVIDIA", "CK804", enable_flash_ck804}, {0x10de, 0x0260, NT, "NVIDIA", "MCP51", enable_flash_ck804},

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Re: [coreboot] coreboot for VX800+Nano
by Konsstantin Lazarev 26 May '09

26 May '09

Hi Bari, I have board awailable and it would be nice to have --- On Mon, 5/25/09, bari <bari(a)onelabs.com> wrote: From: bari <bari(a)onelabs.com> Subject: Re: [coreboot] coreboot for VX800+Nano To: "Konsstantin Lazarev" <klazarev(a)sbcglobal.net> Cc: coreboot(a)coreboot.org Date: Monday, May 25, 2009, 8:13 PM Konsstantin Lazarev wrote: > Thank you, Bari, for youe response. > I have fiollowing questions: > 1. May I count on this release during next week? I have very tught schedule for this project. Yes. But, the version to go public will need some work. > 2. Does coreboot support output to UART ports in vx800? I haven't tried the patch yet on actual hardware myself. It was definitely working on a vx800 dev board. UART support should be simple since serial debug is they way coreboot was developed on this board. I can't tell you if that dev board used the vx800 uarts or an external uart. Maybe someone else that climbed through the patch can tell you more. -Bari

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Re: [coreboot] coreboot for VX800+Nano
by Konsstantin Lazarev 26 May '09

26 May '09

Hi Bari, I have board available and that would be nice to have those sources as soon as possible. I could try them on real hardware and help with debugging. As I said I will provide results to my work back to community. Thank you, Konstantin Lazarev. --- On Mon, 5/25/09, bari <bari(a)onelabs.com> wrote: From: bari <bari(a)onelabs.com> Subject: Re: [coreboot] coreboot for VX800+Nano To: "Konsstantin Lazarev" <klazarev(a)sbcglobal.net> Cc: coreboot(a)coreboot.org Date: Monday, May 25, 2009, 8:13 PM Konsstantin Lazarev wrote: > Thank you, Bari, for youe response. > I have fiollowing questions: > 1. May I count on this release during next week? I have very tught schedule for this project. Yes. But, the version to go public will need some work. > 2. Does coreboot support output to UART ports in vx800? I haven't tried the patch yet on actual hardware myself. It was definitely working on a vx800 dev board. UART support should be simple since serial debug is they way coreboot was developed on this board. I can't tell you if that dev board used the vx800 uarts or an external uart. Maybe someone else that climbed through the patch can tell you more. -Bari

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Re: [coreboot] coreboot for VX800+Nano
by Konsstantin Lazarev 26 May '09

26 May '09

Hi Bari, I have board awailable and it would be nice to ha --- On Mon, 5/25/09, bari <bari(a)onelabs.com> wrote: From: bari <bari(a)onelabs.com> Subject: Re: [coreboot] coreboot for VX800+Nano To: "Konsstantin Lazarev" <klazarev(a)sbcglobal.net> Cc: coreboot(a)coreboot.org Date: Monday, May 25, 2009, 8:13 PM Konsstantin Lazarev wrote: > Thank you, Bari, for youe response. > I have fiollowing questions: > 1. May I count on this release during next week? I have very tught schedule for this project. Yes. But, the version to go public will need some work. > 2. Does coreboot support output to UART ports in vx800? I haven't tried the patch yet on actual hardware myself. It was definitely working on a vx800 dev board. UART support should be simple since serial debug is they way coreboot was developed on this board. I can't tell you if that dev board used the vx800 uarts or an external uart. Maybe someone else that climbed through the patch can tell you more. -Bari

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Re: [coreboot] coreboot for VX800+Nano
by Konsstantin Lazarev 26 May '09

26 May '09

Hi Bari, I have board awailable and it would be nice to --- On Mon, 5/25/09, bari <bari(a)onelabs.com> wrote: From: bari <bari(a)onelabs.com> Subject: Re: [coreboot] coreboot for VX800+Nano To: "Konsstantin Lazarev" <klazarev(a)sbcglobal.net> Cc: coreboot(a)coreboot.org Date: Monday, May 25, 2009, 8:13 PM Konsstantin Lazarev wrote: > Thank you, Bari, for youe response. > I have fiollowing questions: > 1. May I count on this release during next week? I have very tught schedule for this project. Yes. But, the version to go public will need some work. > 2. Does coreboot support output to UART ports in vx800? I haven't tried the patch yet on actual hardware myself. It was definitely working on a vx800 dev board. UART support should be simple since serial debug is they way coreboot was developed on this board. I can't tell you if that dev board used the vx800 uarts or an external uart. Maybe someone else that climbed through the patch can tell you more. -Bari

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coreboot for VX800+Nano
by Konsstantin Lazarev 26 May '09

26 May '09

Hello, I am interested to participate in development of coreboot support for VIA VX8xx+Nano. I have experience in adaptation of LinuxBIOS for GeodeLX platforms in a past. And I have experience in low-level programming and vendor BIOSes (GS, Phoenix) adaptation for other VIA chipsets (CN400, VT8237, CX700, C3, C7). Now I am working on bringing up VX800+Nano based platform (hardware is available) and very interested in moving it to open-source BIOS instead of vendor one. And any existing coreboot source code for VIA VX8xx would be very helpful. I will be glad to contribute my work to open-source BIOS project. I (my employer) have NDA signed with VIA. Thank you, Konstantin Lazarev.

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coreboot May 2009