coreboot May 2009

coreboot@coreboot.org

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571 discussions

build service results for r4295
by coreboot information 23 May '09

23 May '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "ward" checked in revision 4295 to the coreboot repository. This caused the following changes: Change Log: Fix MAINBOARD_PART_NUMBER to be h8dme, I forgot to change it from the h8dmr tree it was copied from. This is a trivial patch. Signed-off-by: Ward Vandewege <ward(a)gnu.org> Acked-by: Ward Vandewege <ward(a)gnu.org> Build Log: Compilation of asus:mew-am is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4295&device=mew-am&vendor=… If something broke during this checkin please be a pain in ward's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[v2] r4295 - trunk/coreboot-v2/src/mainboard/supermicro/h8dme
by svn＠coreboot.org 23 May '09

23 May '09

Author: ward Date: 2009-05-22 18:03:04 +0200 (Fri, 22 May 2009) New Revision: 4295 Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb Log: Fix MAINBOARD_PART_NUMBER to be h8dme, I forgot to change it from the h8dmr tree it was copied from. This is a trivial patch. Signed-off-by: Ward Vandewege <ward(a)gnu.org> Acked-by: Ward Vandewege <ward(a)gnu.org> Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb 2009-05-21 15:12:39 UTC (rev 4294) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb 2009-05-22 16:03:04 UTC (rev 4295) @@ -251,7 +251,7 @@ ## ## Clean up the motherboard id strings ## -default MAINBOARD_PART_NUMBER="h8dmr" +default MAINBOARD_PART_NUMBER="h8dme" default MAINBOARD_VENDOR="Supermicro" default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15d9 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1511

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[flashrom] nic3com: A thanks, a question and a suggestion
by Urja Rannikko 22 May '09

22 May '09

Hello all, First thanks to Uwe for nic3com support and to Mats Erik (IIRC) for helping with (or atleast pointing out the lack of) 3C905B support - i just tested a SST 29EE010 on an 3C905B-TXNM that had been useless for a while - works :) Anyways, does anyone know how big flash chips these 3com's support? The SST i tested is 128k - i can propably (given time) test 256k also, but just curious. And also, if i plan on using this for "hotflashing" a chip from another box to do my various hacks, it would be very much indeed too easy to accidentally write flashrom -w <file> instead of flashrom -p nic3com -w <file> . I'm not 100% sure whether this is a good idea (some might find it annoying), but i suggest that in case of "flashrom -w" or "flashrom -E" it would ask for sure, eg. "This will erase/write your INTERNAL flash chip. Are you sure (y/n)?". If given flashrom -p internal -w (or -E) it would not ask (for scripting). -- urjaman

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[flashrom] r544 - trunk
by svn＠coreboot.org 22 May '09

22 May '09

Author: uwe Date: 2009-05-22 15:18:38 +0200 (Fri, 22 May 2009) New Revision: 544 Modified: trunk/README Log: Add website section (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/README =================================================================== --- trunk/README 2009-05-22 11:37:27 UTC (rev 543) +++ trunk/README 2009-05-22 13:18:38 UTC (rev 544) @@ -85,5 +85,10 @@ Please check the output of 'flashrom -L' for the list of supported flash chips, chipsets/southbridges, mainboards, and flash programmers. -See also http://coreboot.org/Flashrom for more details. +Website +------- +The official flashrom website is: + + http://coreboot.org/Flashrom +

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[flashrom] Asus A7N8X-E Support.
by Luc Verhaegen 22 May '09

22 May '09

With the discussion of the board_enables table, i ended up looking at the flashrom page on coreboot.org and spotted a bunch of boards that are known to not work. The first one i looked at was the aforementioned and this here is what is needed for the flash enable of that board. { uint8_t tmp; pci_write_byte(dev, 0x92, 0); tmp = pci_read_byte(dev, 0x6D); tmp |= 0x01; pci_write_byte(dev, 0x6D, tmp); } While it seems that the second operation seems to match both ck804 and mcp55 chip enables, this is not true. The device used is 0:01.0 (ISA bridge) and not 0:01.1 (SMB controller). I googled, but could not find a report to the coreboot (or linuxbios) list of this board being tested. Does anyone remember who reported this as broken? Luc Verhaegen.

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[flashrom] r543 - trunk
by svn＠coreboot.org 22 May '09

22 May '09

Author: oxygene Date: 2009-05-22 13:37:27 +0200 (Fri, 22 May 2009) New Revision: 543 Modified: trunk/board_enable.c trunk/chipset_enable.c trunk/flashrom.8 trunk/flashrom.c trunk/satasii.c Log: A bunch of output beautifications and improvements, as well as doc fixes: - Update manpage, we now report supported boards via -L. - Add some missing escaping for '-' characters in the manpage. - Shorten some of the really long device names, so that -L output looks nicer. - Display a "table header" for all entries/columns in -L output. - Make -L output tabular for all lists for better readability. - Do not print "unknown XXXX SPI chip" entries in -L output. - And random other cosmetics... Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-05-21 17:11:25 UTC (rev 542) +++ trunk/board_enable.c 2009-05-22 11:37:27 UTC (rev 543) @@ -822,7 +822,9 @@ int i, j; struct board_pciid_enable *b = board_pciid_enables; - printf("\nSupported boards which need write-enable code:\n\n"); + printf("\nSupported boards which need write-enable code:\n\nVendor: " + " Board: Required option:\n\n"); + for (i = 0; b[i].vendor_name != NULL; i++) { printf("%s", b[i].vendor_name); for (j = 0; j < 25 - strlen(b[i].vendor_name); j++) @@ -831,9 +833,9 @@ for (j = 0; j < 25 - strlen(b[i].board_name); j++) printf(" "); if (b[i].lb_vendor != NULL) - printf("(-m %s:%s)\n", b[i].lb_vendor, b[i].lb_part); + printf("-m %s:%s\n", b[i].lb_vendor, b[i].lb_part); else - printf("(autodetected)\n"); + printf("(none, board is autodetected)\n"); } printf("\nSupported boards which don't need write-enable code:\n\n"); Modified: trunk/chipset_enable.c =================================================================== --- trunk/chipset_enable.c 2009-05-21 17:11:25 UTC (rev 542) +++ trunk/chipset_enable.c 2009-05-22 11:37:27 UTC (rev 543) @@ -26,6 +26,7 @@ #define _LARGEFILE64_SOURCE #include <stdlib.h> +#include <string.h> #include <sys/types.h> #include <sys/stat.h> #include <sys/mman.h> @@ -1011,16 +1012,21 @@ void print_supported_chipsets(void) { - int i; + int i, j; + const struct penable *c = chipset_enables; - printf("\nSupported chipsets:\n\n"); + printf("\nSupported chipsets:\n\nVendor: Chipset:" + " PCI IDs:\n\n"); - for (i = 0; chipset_enables[i].vendor_name != NULL; i++) { - printf("%s %s [%04x:%04x]%s\n", chipset_enables[i].vendor_name, - chipset_enables[i].device_name, - chipset_enables[i].vendor_id, - chipset_enables[i].device_id, - (chipset_enables[i].status == OK) ? "" : " (untested)"); + for (i = 0; c[i].vendor_name != NULL; i++) { + printf("%s", c[i].vendor_name); + for (j = 0; j < 25 - strlen(c[i].vendor_name); j++) + printf(" "); + printf("%s", c[i].device_name); + for (j = 0; j < 25 - strlen(c[i].device_name); j++) + printf(" "); + printf("%04x:%04x%s\n", c[i].vendor_id, c[i].device_id, + (c[i].status == OK) ? "" : " (untested)"); } } Modified: trunk/flashrom.8 =================================================================== --- trunk/flashrom.8 2009-05-21 17:11:25 UTC (rev 542) +++ trunk/flashrom.8 2009-05-22 11:37:27 UTC (rev 543) @@ -1,4 +1,4 @@ -.TH FLASHROM 8 "May 14, 2009" +.TH FLASHROM 8 "May 21, 2009" .SH NAME flashrom \- detect, read, write, verify and erase flash chips .SH SYNOPSIS @@ -7,7 +7,7 @@ [\fB\-l\fR file] [\fB\-i\fR image] [\fB\-p\fR programmer] [file] .SH DESCRIPTION .B flashrom -is a utility for detecting, reading, writing, verifying and erasing flash ROM +is a utility for detecting, reading, writing, verifying and erasing flash chips. It's often used to flash BIOS/EFI/coreboot/firmware images in-system using a supported mainboard, but it also supports flashing of network cards (NICs), SATA controller cards, and other external devices which can program @@ -23,8 +23,7 @@ .SH OPTIONS Please note that the command line interface for flashrom will change before flashrom 1.0. Do not use flashrom in scripts or other automated tools without -checking that your flashrom version won't interpret them in a totally different -way. +checking that your flashrom version won't interpret options in a different way. .PP If no file is specified, then all that happens is that flash info is dumped and the flash chip is set to writable. @@ -77,7 +76,7 @@ .sp Currently overlapping sections are not supported. .sp -ROM layouts should replace the -s and -e option since they are more +ROM layouts should replace the \-s and \-e option since they are more flexible and they should lead to a ROM update file format with the ROM layout and the ROM image in one file (cpio, zip or something?). .TP @@ -89,11 +88,11 @@ .sp flashrom reads the coreboot table to determine the current mainboard. If no coreboot table could be read or if you want to override these values, you can -specify -m, e.g.: +specify \-m, e.g.: .sp .B " flashrom -w --mainboard AGAMI:ARUMA agami_aruma.rom" .sp -See the 'Supported mainboards' section in the output of 'flashrom -L' for +See the 'Supported mainboards' section in the output of 'flashrom \-L' for a list of boards which require the specification of the board name, if no coreboot table is found. .TP @@ -114,18 +113,14 @@ from flash layout. .TP .B "\-L, \-\-list\-supported" -List the ROM chips, chipsets, and mainboards supported by flashrom. -The list of mainboards consists of those boards which need a special -ROM write-enable function for flashrom to work. +List the flash chips, chipsets, mainboards, and PCI card "programmers" +supported by flashrom. .sp -There are many other boards which will work out of the box, without such -special support in flashrom. Some of the known-good/known-bad and tested ones -are listed at -.BR http://coreboot.org/Flashrom#Supported_mainboards , -but the list is not exhaustive, of course. -.sp -Please let us know if you can verify other boards to work or not work out -of the box. +There are many unlisted boards which will work out of the box, without +special support in flashrom. Please let us know if you can verify that +other boards work or do not work out of the box. For verification you have +to test an ERASE and/or WRITE operation, so make sure you only do that +if you have proper means to recover from failure! .TP .B "\-p, \-\-programmer <name>" Specify the programmer device. Currently supported are: Modified: trunk/flashrom.c =================================================================== --- trunk/flashrom.c 2009-05-21 17:11:25 UTC (rev 542) +++ trunk/flashrom.c 2009-05-22 11:37:27 UTC (rev 543) @@ -313,7 +313,7 @@ void print_supported_chips(void) { - int okcol = 0, pos = 0; + int okcol = 0, pos = 0, i; struct flashchip *f; for (f = flashchips; f->name != NULL; f++) { @@ -323,7 +323,8 @@ } okcol = (okcol + 7) & ~7; - POS_PRINT("Supported flash chips:"); + printf("Supported flash chips:\n\n"); + POS_PRINT("Vendor: Device:"); while (pos < okcol) { printf("\t"); pos += 8 - (pos % 8); @@ -331,8 +332,16 @@ printf("Tested OK operations:\tKnown BAD operations:\n\n"); for (f = flashchips; f->name != NULL; f++) { - printf("%s %s", f->vendor, f->name); - pos = strlen(f->vendor) + 1 + strlen(f->name); + /* Don't print "unknown XXXX SPI chip" entries. */ + if (!strncmp(f->name, "unknown", 7)) + continue; + + printf("%s", f->vendor); + for (i = 0; i < 10 - strlen(f->vendor); i++) + printf(" "); + printf("%s", f->name); + + pos = 10 + strlen(f->name); while (pos < okcol) { printf("\t"); pos += 8 - (pos % 8); @@ -368,13 +377,13 @@ void usage(const char *name) { printf("usage: %s [-EVfLhR] [-r file] [-w file] [-v file] [-c chipname] [-s addr]\n" - " [-e addr] [-m [vendor:]part] [-l file] [-i image] [-p programmer] [file]", + " [-e addr] [-m [vendor:]part] [-l file] [-i image] [-p programmer] [file]\n\n", name); - printf("\n\nPlease note that the command line interface for flashrom will " - "change before flashrom 1.0.\nDo not use flashrom in scripts or " - "other automated tools without checking that your flashrom\n" - "version won't interpret them in a totally different way.\n\n"); + printf("Please note that the command line interface for flashrom will " + "change before\nflashrom 1.0. Do not use flashrom in scripts " + "or other automated tools without\nchecking that your flashrom" + " version won't interpret options in a different way.\n\n"); printf (" -r | --read: read flash and save into file\n" @@ -387,7 +396,7 @@ " -e | --eend <addr>: exclude end postion\n" " -m | --mainboard <[vendor:]part>: override mainboard settings\n" " -f | --force: force write without checking image\n" - " -l | --layout <file.layout>: read rom layout from file\n" + " -l | --layout <file.layout>: read ROM layout from file\n" " -i | --image <name>: only flash image name from flash layout\n" " -L | --list-supported: print supported devices\n" " -p | --programmer <name>: specify the programmer device\n" Modified: trunk/satasii.c =================================================================== --- trunk/satasii.c 2009-05-21 17:11:25 UTC (rev 542) +++ trunk/satasii.c 2009-05-22 11:37:27 UTC (rev 543) @@ -34,11 +34,11 @@ uint16_t id; struct pcidev_status satas_sii[] = { - {0x1095, 0x0680, PCI_OK, "Silicon Image", "PCI0680 Ultra ATA-133 Host Controller"}, - {0x1095, 0x3114, PCI_OK, "Silicon Image", "SiI 3114 [SATALink/SATARaid] Serial ATA Controller"}, - {0x1095, 0x3124, PCI_NT, "Silicon Image", "SiI 3124 PCI-X Serial ATA Controller"}, - {0x1095, 0x3132, PCI_OK, "Silicon Image", "SiI 3132 Serial ATA Raid II Controller"}, - {0x1095, 0x3512, PCI_NT, "Silicon Image", "SiI 3512 [SATALink/SATARaid] Serial ATA Controller"}, + {0x1095, 0x0680, PCI_OK, "Silicon Image", "PCI0680 Ultra ATA-133 Host Ctrl"}, + {0x1095, 0x3114, PCI_OK, "Silicon Image", "SiI 3114 [SATALink/SATARaid] SATA Ctrl"}, + {0x1095, 0x3124, PCI_NT, "Silicon Image", "SiI 3124 PCI-X SATA Ctrl"}, + {0x1095, 0x3132, PCI_OK, "Silicon Image", "SiI 3132 SATA Raid II Ctrl"}, + {0x1095, 0x3512, PCI_NT, "Silicon Image", "SiI 3512 [SATALink/SATARaid] SATA Ctrl"}, {}, };

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Uh oh, looks like trouble...
by Joshua McDowell 22 May '09

22 May '09

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 So I am able to some what force read the chip, although it's not correct, I can see clearly parts of what I know is the Linux BIOS binary, and stuff that I know is not. My research tells me it uses a "28F320C3B" flash rom chip. I am starting to think I am completely screwed here, any help at all would be greatly appreciated. Joshua McDowell -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkoUMa4ACgkQDiqOyViXQA4LUACeNLWGMfDAY3iy/OuZzzCX4cJI K7oAnAvUekh+XP2RxN+fXieo9vGArIyB =y+nW -----END PGP SIGNATURE-----

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[USBOPTIONROM] Turn Real Mode to PM mode
by Jason Wang 22 May '09

22 May '09

Hi all, I am trying to make optionrom can be run in PM 32 bit mode, and my work flow is 1)load gdt 2)open A20 3) set cro bit 4) take the long jump to 32 bit PM. After step 3) optionrom has already in 16bit PM,but the long jump did not work, which should run in to 32bit PM. I paste the whole assemble file here. Is there any one who can give a hand about this? .text .code16 # Real mode by default (prefix 66 or 67 to 32 bits instructions) rom_size = 0x04 # ROM size in multiple of 512 bytes os_load_seg = 0x0000 # this is working if lgdt is passed with an absolute address os_code_size = ((rom_size - 1)*512) os_code_size16 = ( os_code_size / 2 ) _base_address: .word 0xAA55 # Rom signature .byte rom_size # Size of this ROM, see definition above jmp _init # jump to PCI initialization function .org 0x18 .word _pci_data_struct # Pointer to PCI HDR structure (at 18h) .word _pnp_header # PnP Expansion Header Pointer (at 1Ah) # -------------------------------------------- # PCI data structure # _pci_data_struct: .ascii "PCIR" # PCI Header Sign .word 0x8086 # Vendor ID .word 0x7000 # Device ID .word 0x00 # VPD .word 0x18 # PCI data struc length (byte) .byte 0x00 # PCI Data struct Rev .byte 0x02 # Base class code, 02h == Network Controller .byte 0x00 # Sub class code = 00h and interface = 00h -->Ethernet Controller .byte 0x00 # Interface code, see PCI Rev2.1 Spec Appendix D .word rom_size # Image length in mul of 512 byte, little endian format .word 0x00 # rev level .byte 0x00 # Code type = x86 .byte 0x80 # last image indicator .word 0x00 # reserved # ----------------------------- # PnP ROM Bios Header # _pnp_header: .ascii "$PnP" # PnP Rom header sign .byte 0x01 # Structure Revision .byte 0x02 # Header structure Length in mul of 16 bytes .word 0x00 # Offset to next header (00 if none) .byte 0x00 # reserved .byte 0x00 # 8-Bit checksum for this header, calculated and patched by build_rom .long 0x00 # PnP Device ID (0h in Realtek RPL ROM, we just follow it) .word 0x00 # pointer to manufacturer string, we use empty string .word 0x00 # pointer to product string, we use empty string .byte 0x02,0x00,0x00 # Device Type code 3 byte .byte 0x14 # Device Indicator, 14h from Realtek RPL ROM-->See Page 18 of # PnP BIOS spec., Lo nibble (4) means IPL device .word 0x00 # Boot Connection Vector, 00h = disabled .word 0x00 # Disconnect Vector, 00h = disabled .word _start # Bootstrap Entry Vector (BEV) .word 0x00 # reserved .word 0x00 # Static resource Information vector (0000h if unused) #-------------------------------------------------------------------- # PCI Option ROM initialization Code (init function) # _init: /////////////////////////////////////////////// 1: jmp 1b jmp _setup ret //////////////////////////////////////////////////////// andw $0xCF, %ax # inform system BIOS that an IPL device attached orw $0x20, %ax # see PnP spec 1.0A p21 for info's lret # return far to system BIOS #-------------------------------------------------------------------- # entry point/BEV implementation (invoked during bootstrap / int 19h) # .global _start # entry point _start: movw $0x9000, %ax # setup temporary stack movw %ax, %ss # ss = 0x9000 # move ourself from "ROM" -> RAM 0x0000 movw %cs, %ax # initialize source address movw %ax, %ds movw $os_load_seg, %ax # point to OS segment movw %ax, %es movl $os_code_size16, %ecx subw %di, %di subw %si, %si cld rep movsw ljmp $os_load_seg, $_setup _setup: movw %cs, %ax # initialize segment registers (this is needed since lgdt is %ds dependent??) movw %ax, %ds xorl %eax,%eax # Compute gdt_base movw %cs,%ax # (Convert %ds:gdt to a linear ptr) shll $4, %eax addl $(gdt_desc), %eax movl %eax, (gdt_desc+2) lgdt (gdt_desc) # load GDT to GDTR (we load both limit and base address) # --------------------------------------------------------------------- # Switch to P-Mode and jump to C-Compiled kernel # cli # disable interrupt // enable a20 inb $0x0092, %al orb $0x02, %al outb %al, $0x0092 movl %cr0, %eax # switch to P-Mode or $1, %eax movl %eax, %cr0 # haven't yet in P-Mode, we need a FAR Jump .byte 0x66, 0xea # prefix + jmpi-opcode (this force P-Mode to be reached i.e. CS updated) .long do_pm # 32-bit linear address (jump target) .word SEG_CODE_SEL # code segment selector .code32 do_pm: // xorl %esi, %esi // xorl %edi, %edi movw $0x10, %ax # Save data segment identifier (see GDT) movw %ax, %ds movw $0x18, %ax # Save stack segment identifier movw %ax, %ss movl $0x90000, %esp jmp main # jump to main function .align 8, 0 # align GDT in 8 bytes boundary # ----------------------------------------------------- # GDT definition # gdt_marker: # dummy Segment Descriptor (GDT) .long 0 .long 0 SEG_CODE_SEL = ( . - gdt_marker) SegDesc1: # kernel CS (08h) PL0, 08h is an identifier .word 0xffff # seg_length0_15 .word 0 # base_addr0_15 .byte 0 # base_addr16_23 .byte 0x9A # flags 9b? .byte 0xcf # access .byte 0 # base_addr24_31 SEG_DATA_SEL = ( . - gdt_marker) SegDesc2: # kernel DS (10h) PL0 .word 0xffff # seg_length0_15 .word 0 # base_addr0_15 .byte 0 # base_addr16_23 .byte 0x92 # flags .byte 0xcf # access .byte 0 # base_addr24_31 SEG_STACK_SEL = ( . - gdt_marker) SegDesc3: # kernel SS (18h) PL0 .word 0xffff # seg_length0_15 .word 0 # base_addr0_15 .byte 0 # base_addr16_23 .byte 0x92 # flags .byte 0xcf # access .byte 0 # base_addr24_31 gdt_end: gdt_desc: .word (gdt_end - gdt_marker - 1) # GDT limit .long (gdt_marker - _base_address-8) # physical addr of GDT -- Jason Wang Peking University

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Re: [coreboot] jarrell_rom_jumper.c ( I think I found it )
by ron minnich 22 May '09

22 May '09

On Thu, May 21, 2009 at 11:57 AM, Joshua McDowell <JMcDowell(a)issisolutions.com> wrote: > Also, the factory flash docs never mention changing a jumper.. > A jumper would be surprising. Intel stopped doing jumpers on many boards before this board was made. ron

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Re: [coreboot] jarrell_rom_jumper.c ( I think I found it )
by Peter Stuge 22 May '09

22 May '09

Joshua McDowell wrote: > Forcing the use of "SST49LF160C" as the prom dumps the bios > perfectly every time, even before the use of the newly discovered > source code. Unfortunately that doesn't mean very much. A forced read disregards everything needed for writing or erasing a chip and only tries desperately to read the contents. It's only some minimal functionality that doesn't help us for write or erase. Maybe you can try playing with the rom_jumper source a bit. Try to get it where it says that the jumper value is 1-2 instead? Maybe there is even a hardware jumper on the board? Can you check? //Peter

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coreboot May 2009