coreboot May 2009

coreboot@coreboot.org

92 participants
571 discussions

build service results for r4297
by coreboot information 24 May '09

24 May '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 4297 to the coreboot repository. This caused the following changes: Change Log: fix comment in keyboard driver (trivial) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of asus:mew-am is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4297&device=mew-am&vendor=… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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Development of Live-CD
by Christian Ziegenrücker 24 May '09

24 May '09

Hey folks, I am really impressed by your coreboot project. So i decided to help, but im only familiar with basic C++ development. So i am quite sure that developing is nothing for me. Despite that I want to create the Live-CD for coreboot that is mentiond here (-> http://www.coreboot.org/Flashrom_Live_CD). I am familiar with the creation of ubuntu live-cd's from scratch and I think that is really helpfull. If you want to I deliver a first preview-version soon. Just tell me if you want one. I would prefer a german developer that tells me if the cd is good or bad and how things shall be changed, because i am not really good in english. Best regards, Christian Ziegenrücker _________________________________________________________________ http://redirect.gimas.net/?n=M0905xIE8_MSN3 Hol Dir den neuen Internet Explorer 8 mit MSN-Toolbar

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[v2] r4298 - trunk/coreboot-v2/src/pc80
by svn＠coreboot.org 24 May '09

24 May '09

Author: stepan Date: 2009-05-24 00:02:31 +0200 (Sun, 24 May 2009) New Revision: 4298 Modified: trunk/coreboot-v2/src/pc80/keyboard.c Log: keyboard driver: function definitions should not omit void if they don't take parameters. (trivial) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/src/pc80/keyboard.c =================================================================== --- trunk/coreboot-v2/src/pc80/keyboard.c 2009-05-23 22:00:58 UTC (rev 4297) +++ trunk/coreboot-v2/src/pc80/keyboard.c 2009-05-23 22:02:31 UTC (rev 4298) @@ -194,7 +194,7 @@ * Not well documented. Google - 0xcb keyboard controller * This is called before pc_keyboard_init(). */ -void set_kbc_ps2_mode() +void set_kbc_ps2_mode(void) { /* clean up any junk that might have been in the kbc */ if (!kbc_cleanup_buffers()) return;

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[v2] r4297 - trunk/coreboot-v2/src/pc80
by svn＠coreboot.org 24 May '09

24 May '09

Author: stepan Date: 2009-05-24 00:00:58 +0200 (Sun, 24 May 2009) New Revision: 4297 Modified: trunk/coreboot-v2/src/pc80/keyboard.c Log: fix comment in keyboard driver (trivial) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/src/pc80/keyboard.c =================================================================== --- trunk/coreboot-v2/src/pc80/keyboard.c 2009-05-22 18:17:06 UTC (rev 4296) +++ trunk/coreboot-v2/src/pc80/keyboard.c 2009-05-23 22:00:58 UTC (rev 4297) @@ -111,7 +111,7 @@ if (!kbc_input_buffer_empty()) return; outb(0x60, 0x64); if (!kbc_input_buffer_empty()) return; - outb(0x20, 0x60); /* send cmd: enable keyboard and IRQ 1 */ + outb(0x20, 0x60); /* send cmd: enable keyboard */ if ((inb(0x64) & 0x01)) { regval = inb(0x60); }

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Re: [coreboot] [flashrom] r545 - trunk
by Uwe Hermann 23 May '09

23 May '09

On Sat, May 23, 2009 at 02:56:50AM +0200, svn(a)coreboot.org wrote: > + {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, "msi", "kt4ultra", "MSI", "KT4 Ultra", board_msi_kt4v}, For future reference, here's the lspci from that board. 00:00.0 Host bridge: VIA Technologies, Inc. VT8377 [KT400/KT600 AGP] Host Bridge Subsystem: VIA Technologies, Inc. KT4AV motherboard (KT400A) Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR+ INTx- Latency: 8 Region 0: Memory at e0000000 (32-bit, prefetchable) [size=128M] Capabilities: [80] AGP version 3.5 Status: RQ=32 Iso- ArqSz=0 Cal=2 SBA+ ITACoh- GART64- HTrans- 64bit- FW+ AGP3+ Rate=x4,x8 Command: RQ=32 ArqSz=0 Cal=0 SBA- AGP- GART64- 64bit- FW- Rate=<none> Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00: 06 11 89 31 06 00 30 a2 00 00 00 06 00 08 00 00 10: 08 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 06 11 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 40: 00 19 88 80 82 44 01 00 11 19 88 10 82 44 00 00 50: c0 00 00 00 32 84 40 40 f1 10 20 40 40 40 40 40 60: 00 aa 0f 20 b6 99 00 19 21 ad 65 d0 41 27 00 00 70: 82 c8 00 01 00 09 50 00 01 00 00 00 00 00 00 02 80: 02 c0 35 00 1b 0a 00 1f 00 00 00 1f 00 00 00 00 90: 00 03 00 00 20 0f 01 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 21 98 00 88 b0: 7f 00 00 00 44 00 00 00 88 00 00 00 00 00 00 86 c0: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 16 f4 69 ea 0f 1c f1 79 21 ff 00 00 21 32 74 00 e0: 00 00 00 00 00 ff 01 00 9a 77 cc 00 00 9a 20 00 f0: 00 00 00 00 00 00 05 00 00 00 00 00 00 04 00 00 00:01.0 PCI bridge: VIA Technologies, Inc. VT8235 PCI Bridge (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR- INTx- Latency: 0 Bus: primary=00, secondary=01, subordinate=01, sec-latency=0 I/O behind bridge: 0000f000-00000fff Memory behind bridge: dde00000-dfefffff Prefetchable memory behind bridge: cdd00000-ddcfffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA+ MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [80] Power Management version 2 Flags: PMEClk- DSI- D1+ D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00: 06 11 68 b1 07 01 30 22 00 00 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 01 01 00 f0 00 00 00 20: e0 dd e0 df d0 cd c0 dd 00 00 00 00 00 00 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 0c 00 40: 81 c0 80 44 24 72 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 01 00 02 02 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0a.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ (rev 10) Subsystem: Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32 (8000ns min, 16000ns max) Interrupt: pin A routed to IRQ 17 Region 0: I/O ports at e000 [size=256] Region 1: Memory at dfffef00 (32-bit, non-prefetchable) [size=256] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0-,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: 8139too Kernel modules: 8139cp, 8139too 00: ec 10 39 81 07 00 90 02 10 00 00 02 00 20 00 00 10: 01 e0 00 00 00 ef ff df 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 ec 10 39 81 30: 00 00 00 00 50 00 00 00 00 00 00 00 05 01 20 40 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 00 c2 f7 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0b.0 Ethernet controller: Realtek Semiconductor Co., Ltd. Device 8039 (rev 10) Subsystem: Unex Technology Corp. Device d010 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR+ INTx- Latency: 32 (8000ns min, 16000ns max) Interrupt: pin A routed to IRQ 10 Region 0: I/O ports at dc00 [size=256] Region 1: Memory at 50000000 (32-bit, non-prefetchable) [size=256] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1+ D2- AuxCurrent=160mA PME(D0-,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00: ec 10 39 80 07 00 90 82 10 00 00 02 00 20 00 00 10: 01 dc 00 00 00 00 00 50 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 29 14 10 d0 30: 00 00 00 00 50 00 00 00 00 00 00 00 0a 01 20 40 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 00 c2 f2 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0c.0 Multimedia audio controller: C-Media Electronics Inc CM8738 (rev 10) Subsystem: Micro-Star International Co., Ltd. Device 5900 Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32 (500ns min, 6000ns max) Interrupt: pin A routed to IRQ 11 Region 0: I/O ports at d800 [size=256] Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00: f6 13 11 01 05 00 10 02 10 00 01 04 00 20 00 00 10: 01 d8 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 62 14 00 59 30: 00 00 00 00 c0 00 00 00 00 00 00 00 0b 01 02 18 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 01 00 02 06 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0d.0 RAID bus controller: Promise Technology, Inc. PDC20376 (FastTrak 376) (rev 02) Subsystem: Promise Technology, Inc. Device 6620 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 96 (1000ns min, 4500ns max), Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 19 Region 0: I/O ports at ec00 [size=64] Region 1: I/O ports at e800 [size=16] Region 2: I/O ports at e400 [size=128] Region 3: Memory at dffff000 (32-bit, non-prefetchable) [size=4K] Region 4: Memory at dffc0000 (32-bit, non-prefetchable) [size=128K] Capabilities: [60] Power Management version 2 Flags: PMEClk- DSI+ D1+ D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: sata_promise Kernel modules: sata_promise 00: 5a 10 76 33 17 00 30 02 02 00 04 01 08 60 00 00 10: 01 ec 00 00 01 e8 00 00 01 e4 00 00 00 f0 ff df 20: 00 00 fc df 00 00 00 00 00 00 00 00 5a 10 20 66 30: 00 00 00 00 60 00 00 00 00 00 00 00 0a 01 04 12 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 01 00 22 02 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 ff ff 03 00 00 00 00 00 00 00 00 00 00:10.0 USB Controller: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller (rev 80) (prog-if 00 [UHCI]) Subsystem: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32, Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 21 Region 4: I/O ports at cc00 [size=32] Capabilities: [80] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: uhci_hcd Kernel modules: uhci-hcd 00: 06 11 38 30 17 00 10 02 80 00 03 0c 08 20 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 cc 00 00 00 00 00 00 00 00 00 00 06 11 38 30 30: 00 00 00 00 80 00 00 00 00 00 00 00 0b 01 00 00 40: 40 12 03 00 00 00 00 00 00 0b 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 01 00 c2 ff 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 00 00:10.1 USB Controller: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller (rev 80) (prog-if 00 [UHCI]) Subsystem: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32, Cache Line Size: 32 bytes Interrupt: pin B routed to IRQ 21 Region 4: I/O ports at d000 [size=32] Capabilities: [80] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: uhci_hcd Kernel modules: uhci-hcd 00: 06 11 38 30 17 00 10 02 80 00 03 0c 08 20 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 d0 00 00 00 00 00 00 00 00 00 00 06 11 38 30 30: 00 00 00 00 80 00 00 00 00 00 00 00 05 02 00 00 40: 40 12 03 00 00 00 00 00 00 0b 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 01 00 c2 ff 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 00 00:10.2 USB Controller: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller (rev 80) (prog-if 00 [UHCI]) Subsystem: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32, Cache Line Size: 32 bytes Interrupt: pin C routed to IRQ 21 Region 4: I/O ports at d400 [size=32] Capabilities: [80] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: uhci_hcd Kernel modules: uhci-hcd 00: 06 11 38 30 17 00 10 02 80 00 03 0c 08 20 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 d4 00 00 00 00 00 00 00 00 00 00 06 11 38 30 30: 00 00 00 00 80 00 00 00 00 00 00 00 0a 03 00 00 40: 40 12 03 00 00 00 00 00 00 0b 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 01 00 c2 ff 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 00 00:10.3 USB Controller: VIA Technologies, Inc. USB 2.0 (rev 82) (prog-if 20 [EHCI]) Subsystem: VIA Technologies, Inc. USB 2.0 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32, Cache Line Size: 64 bytes Interrupt: pin D routed to IRQ 21 Region 0: Memory at dfffed00 (32-bit, non-prefetchable) [size=256] Capabilities: [80] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: ehci_hcd Kernel modules: ehci-hcd 00: 06 11 04 31 17 00 10 02 82 20 03 0c 10 20 00 00 10: 00 ed ff df 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 06 11 04 31 30: 00 00 00 00 80 00 00 00 00 00 00 00 0a 04 00 00 40: 00 00 03 00 00 00 00 00 80 10 00 09 00 00 00 00 50: 00 5a 04 80 00 00 00 00 04 0b 66 66 33 66 00 00 60: 20 20 01 00 00 00 00 00 01 00 00 00 00 00 08 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 01 00 c2 ff 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 00 00:11.0 ISA bridge: VIA Technologies, Inc. VT8235 ISA Bridge Subsystem: VIA Technologies, Inc. KT4AV motherboard Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping+ SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00: 06 11 77 31 87 00 10 02 00 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 06 11 00 00 30: 00 00 00 00 c0 00 00 00 00 00 00 00 00 00 00 00 40: 54 7f f8 0b 00 00 00 00 0c 20 00 00 44 00 08 08 50: c1 0d 09 00 00 00 00 00 43 00 ff 00 00 00 04 08 60: 00 00 00 00 10 00 02 04 00 00 00 00 00 00 00 00 70: 06 11 00 00 00 00 00 00 00 00 00 00 20 00 00 00 80: 20 84 59 00 9a 10 00 00 01 08 00 00 04 18 00 00 90: 00 21 11 00 b0 c4 00 00 50 05 20 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 01 04 01 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 14 08 c3 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 05 00 00 00 00 00 00 00 00 00 00:11.1 IDE interface: VIA Technologies, Inc. VT82C586A/B/VT82C686/A/B/VT823x/A/C PIPC Bus Master IDE (rev 06) (prog-if 8a [Master SecP PriP]) Subsystem: VIA Technologies, Inc. VT82C586/B/VT82C686/A/B/VT8233/A/C/VT8235 PIPC Bus Master IDE Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32 Interrupt: pin A routed to IRQ 255 Region 0: [virtual] Memory at 000001f0 (32-bit, non-prefetchable) [size=8] Region 1: [virtual] Memory at 000003f0 (type 3, non-prefetchable) [size=1] Region 2: [virtual] Memory at 00000170 (32-bit, non-prefetchable) [size=8] Region 3: [virtual] Memory at 00000370 (type 3, non-prefetchable) [size=1] Region 4: I/O ports at fc00 [size=16] Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: VIA_IDE Kernel modules: pata_via 00: 06 11 71 05 07 00 90 02 06 8a 01 01 00 20 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 fc 00 00 00 00 00 00 00 00 00 00 06 11 71 05 30: 00 00 00 00 c0 00 00 00 00 00 00 00 ff 01 00 00 40: 0b f2 09 05 18 1c c0 00 a8 a8 a8 20 ff 00 b6 20 50: 07 07 17 e6 4c 03 00 00 a8 a8 a8 a8 00 00 00 00 60: 00 02 00 00 00 00 00 00 00 02 00 00 00 00 00 00 70: 02 01 00 00 00 00 00 00 82 01 00 00 00 00 00 00 80: 00 50 b8 37 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 06 00 71 05 06 11 71 05 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 07 00 00 00 00 00 00 00 00 00 01:00.0 VGA compatible controller: nVidia Corporation NV18 [GeForce4 MX 4000] (rev c1) (prog-if 00 [VGA controller]) Subsystem: Micro-Star International Co., Ltd. Device 9363 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32 (1250ns min, 250ns max) Interrupt: pin A routed to IRQ 11 Region 0: Memory at de000000 (32-bit, non-prefetchable) [size=16M] Region 1: Memory at d0000000 (32-bit, prefetchable) [size=128M] Expansion ROM at dfee0000 [disabled] [size=128K] Capabilities: [60] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [44] AGP version 3.0 Status: RQ=32 Iso- ArqSz=0 Cal=3 SBA+ ITACoh- GART64- HTrans- 64bit- FW+ AGP3+ Rate=x4,x8 Command: RQ=1 ArqSz=0 Cal=0 SBA- AGP- GART64- 64bit- FW- Rate=<none> 00: de 10 85 01 07 00 b0 02 c1 00 00 03 00 20 00 00 10: 00 00 00 de 08 00 00 d0 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 62 14 63 93 30: 00 00 ee df 60 00 00 00 00 00 00 00 0b 01 05 01 40: 62 14 63 93 02 00 30 00 1b 0e 00 1f 00 00 00 00 50: 01 00 00 00 01 00 00 00 ce d6 23 00 0f 00 00 00 60: 01 44 02 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

1 0

[flashrom] r545 - trunk
by svn＠coreboot.org 23 May '09

23 May '09

Author: uwe Date: 2009-05-23 02:56:49 +0200 (Sat, 23 May 2009) New Revision: 545 Modified: trunk/board_enable.c Log: Autodetection support and write-enable for the MSI KT4 Ultra. Thanks Christian Ruppert <spooky85(a)gmail.com> for testing on hardware. (also: Fix a typo and some whitespace while I'm at it) Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-05-22 13:18:38 UTC (rev 544) +++ trunk/board_enable.c 2009-05-23 00:56:49 UTC (rev 545) @@ -619,6 +619,7 @@ * * Suited for: * - MSI KT4V and KT4V-L: AMD K7 + VIA KT400 + VT8235 + * - MSI KT4 Ultra: AMD K7 + VIA KT400 + VT8235 * - MSI KT3 Ultra2: AMD K7 + VIA KT333 + VT8235 */ static int board_msi_kt4v(const char *name) @@ -664,8 +665,8 @@ /* Please keep this list alphabetically ordered by vendor/board name. */ struct board_pciid_enable board_pciid_enables[] = { - /* first pci-id set [4], second pci-id set [4], coreboot id [2], vendor name board name flash enable */ - {0x8086, 0x1130, 0, 0, 0x105a, 0x0d30, 0x105a, 0x4d33, "acorp", "6a815epd", "Acorp", "6A815EPD", board_acorp_6a815epd}, + /* first pci-id set [4], second pci-id set [4], coreboot id [2], vendor name board name flash enable */ + {0x8086, 0x1130, 0, 0, 0x105a, 0x0d30, 0x105a, 0x4d33, "acorp", "6a815epd", "Acorp", "6A815EPD", board_acorp_6a815epd}, {0x1022, 0x746B, 0x1022, 0x36C0, 0, 0, 0, 0, "AGAMI", "ARUMA", "agami", "Aruma", w83627hf_gpio24_raise_2e}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, "artecgroup", "dbe61", "Artec Group", "DBE61", board_artecgroup_dbe6x}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, "artecgroup", "dbe62", "Artec Group", "DBE62", board_artecgroup_dbe6x}, @@ -693,6 +694,7 @@ {0x10de, 0x005e, 0, 0, 0, 0, 0, 0, "msi", "k8n-neo3", "MSI", "K8N Neo3", w83627thf_gpio4_4_raise_4e}, {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, "MSI", "K8T Neo2", w83627thf_gpio4_4_raise_2e}, {0x1106, 0x0571, 0x1462, 0x7120, 0, 0, 0, 0, "msi", "kt4v", "MSI", "KT4V", board_msi_kt4v}, + {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, "msi", "kt4ultra", "MSI", "KT4 Ultra", board_msi_kt4v}, {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, "MSI", "MS-7046", ich6_gpio19_raise}, {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", board_asus_a7v8x_mx}, {0x1106, 0x0314, 0x1106, 0xaa08, 0x1106, 0x3227, 0x1106, 0xAA08, NULL, NULL, "VIA", "EPIA-CN", board_via_epia_sp}, @@ -764,7 +766,7 @@ { "Tyan", "S5220", }, { "Tyan", "S5375", }, { "Tyan", "iS5375-1U", }, - { "Tyan", "S5376G2NR/S5376}WAG2NR", }, + { "Tyan", "S5376G2NR/S5376WAG2NR", }, { "Tyan", "S5377", }, { "Tyan", "S5397", }, { "VIA", "EPIA-M", },

1 0

(no subject)
by Konsstantin Lazarev 22 May '09

22 May '09

Hello, I am interested to participate in development of coreboot support for VIA VX8xx+Nano. I have experience in adaptation of LinuxBIOS for GeodeLX platforms in a past. And I have experience in low-level programming and vendor BIOSes (GS, Phoenix) adaptation for other VIA chipsets (CN400, VT8237, CX700, C3, C7). Now I am working on bringing up VX800+Nano based platform (hardware is available) and very interested in moving it to open-source BIOS instead of vendor one. And any existing coreboot source code for VIA VX8xx would be very helpful. I will be glad to contribute my work to open-source BIOS project. I (my employer) have NDA signed with VIA. Thank you, Konstantin Lazarev.

1 0

build service results for r4296
by coreboot information 22 May '09

22 May '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "uwe" checked in revision 4296 to the coreboot repository. This caused the following changes: Change Log: Make the getpir output look less crappy and add a license header template, as people keep forgetting them. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of asus:mew-am is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4296&device=mew-am&vendor=… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[v2] r4296 - trunk/util/getpir
by svn＠coreboot.org 22 May '09

22 May '09

Author: uwe Date: 2009-05-22 20:17:06 +0200 (Fri, 22 May 2009) New Revision: 4296 Modified: trunk/util/getpir/code_gen.c Log: Make the getpir output look less crappy and add a license header template, as people keep forgetting them. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/util/getpir/code_gen.c =================================================================== --- trunk/util/getpir/code_gen.c 2009-05-22 16:03:04 UTC (rev 4295) +++ trunk/util/getpir/code_gen.c 2009-05-22 18:17:06 UTC (rev 4296) @@ -3,21 +3,34 @@ #include "pirq_routing.h" static char *preamble[] = { - "/* This file was generated by getpir.c, do not modify!\n", - " * (but if you do, please run checkpir on it to verify)\n", + + "/*\n", + " * This file is part of the coreboot project.\n", " *\n", - " * Contains the IRQ Routing Table dumped directly from your\n", - " * memory, which BIOS sets up.\n", + " * Copyright (C) 200x TODO <TODO@TODO>\n", " *\n", - " * Documentation at: http://www.microsoft.com/whdc/archive/pciirq.mspx\n */\n\n", - "#ifdef GETPIR\n", - "#include \"pirq_routing.h\"\n", - "#else\n" + " * This program is free software; you can redistribute it and/or modify\n", + " * it under the terms of the GNU General Public License as published by\n", + " * the Free Software Foundation; either version 2 of the License, or\n", + " * (at your option) any later version.\n", + " *\n", + " * This program is distributed in the hope that it will be useful,\n", + " * but WITHOUT ANY WARRANTY; without even the implied warranty of\n", + " * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n", + " * GNU General Public License for more details.\n", + " *\n", + " * You should have received a copy of the GNU General Public License\n", + " * along with this program; if not, write to the Free Software\n", + " * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\n", + " */\n\n", + "#ifdef GETPIR /* TODO: Drop this when copying to coreboot. */\n", + "#include \"pirq_routing.h\" /* TODO: Drop this when copying to coreboot. */\n", + "#else /* TODO: Drop this when copying to coreboot. */\n" "#include <arch/pirq_routing.h>\n", - "#endif\n\n" + "#endif /* TODO: Drop this when copying to coreboot. */\n\n" "const struct irq_routing_table intel_irq_routing_table = {\n", - "\tPIRQ_SIGNATURE, /* u32 signature */\n", - "\tPIRQ_VERSION, /* u16 version */\n", + "\tPIRQ_SIGNATURE, /* u32 signature */\n", + "\tPIRQ_VERSION, /* u16 version */\n", 0 }; @@ -36,25 +49,25 @@ while (*code) fprintf(fpir, "%s", *code++); - fprintf(fpir, "\t32+16*%d, /* There can be total %d devices on the bus */\n", + fprintf(fpir, "\t32 + 16 * %d, /* Max. number of devices on the bus */\n", ts, ts); - fprintf(fpir, "\t0x%02x, /* Where the interrupt router lies (bus) */\n", + fprintf(fpir, "\t0x%02x, /* Interrupt router bus */\n", rt->rtr_bus); - fprintf(fpir, "\t(0x%02x<<3)|0x%01x, /* Where the interrupt router lies (dev) */\n", + fprintf(fpir, "\t(0x%02x << 3) | 0x%01x, /* Interrupt router dev */\n", rt->rtr_devfn >> 3, rt->rtr_devfn & 7); - fprintf(fpir, "\t%#x, /* IRQs devoted exclusively to PCI usage */\n", + fprintf(fpir, "\t%#x, /* IRQs devoted exclusively to PCI usage */\n", rt->exclusive_irqs); - fprintf(fpir, "\t%#x, /* Vendor */\n", rt->rtr_vendor); - fprintf(fpir, "\t%#x, /* Device */\n", rt->rtr_device); - fprintf(fpir, "\t%#x, /* Miniport */\n", + fprintf(fpir, "\t%#x, /* Vendor */\n", rt->rtr_vendor); + fprintf(fpir, "\t%#x, /* Device */\n", rt->rtr_device); + fprintf(fpir, "\t%#x, /* Miniport */\n", rt->miniport_data); fprintf(fpir, "\t{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */\n"); - fprintf(fpir, "\t%#x, /* u8 checksum. This has to be set to some\n value that would give 0 after the sum of all\n bytes for this structure (including checksum) */\n", + fprintf(fpir, "\t%#x, /* Checksum (has to be set to some value that\n * would give 0 after the sum of all bytes\n * for this structure (including checksum).\n */\n", rt->checksum); fprintf(fpir, "\t{\n"); - fprintf(fpir, "\t\t/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */\n"); + fprintf(fpir, "\t\t/* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */\n"); for (i = 0; i < ts; i++) { - fprintf(fpir, "\t\t{0x%02x,(0x%02x<<3)|0x%01x, {{0x%02x, 0x%04x}, {0x%02x, 0x%04x}, {0x%02x, 0x%04x}, {0x%02x, 0x%04x}}, 0x%x, 0x%x},\n", + fprintf(fpir, "\t\t{0x%02x, (0x%02x << 3) | 0x%01x, {{0x%02x, 0x%04x}, {0x%02x, 0x%04x}, {0x%02x, 0x%04x}, {0x%02x, 0x%04x}}, 0x%x, 0x%x},\n", (se_arr+i)->bus, (se_arr+i)->devfn >> 3, (se_arr+i)->devfn & 7, (se_arr+i)->irq[0].link, (se_arr+i)->irq[0].bitmap, (se_arr+i)->irq[1].link,

1 0

SeaBIOS, serial output, and grub
by Ward Vandewege 22 May '09

22 May '09

I've been experimenting with SeaBIOS, and I like what I'm seeing a lot. Great work Kevin! I think I found one bug, and I have a feature request. Feature request: I'd really like a serial console for SeaBIOS. I 'd like serial to just mirror the VGA console so that either could be used for viewing and input. Right now, it seems only sending debug output to the console is supported. Bug: I have grub configured to pause 5 seconds while giving the user to select either serial or VGA console for input. This is done with these lines in menu.lst: serial --unit=0 --speed=115200 --word=8 --parity=no --stop=1 terminal --timeout=5 serial console This does not appear to go over well. The symptoms I see are: a) the 'Press any key to continue' is only printed on the VGA console, not on serial b) it takes way more than 1 second between the 'Press any key to continue' lines - presumably because writing to serial is somehow failing c) while this is happening, keyboard nor serial console input works If I press enough keys before I get to grub and/or during this serial/console detection, I can sometimes get it to show the menu on the VGA console (it defaults to serial). If I get to that point, the keyboard usually works just fine. Also, the keyboard works fine before I get to grub, but it's hard to catch the F12 keypress as everything goes pretty fast. I've tried with and without CONFIG_DEBUG_SERIAL set in src/config.h. It does not seem to make a difference. CONFIG_SERIAL is set to 1. Suggestions? Thanks, Ward. -- Ward Vandewege <ward(a)fsf.org> Free Software Foundation - Senior Systems Administrator

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coreboot May 2009