coreboot May 2009

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[flashrom] r550 - trunk
by svn＠coreboot.org 26 May '09

26 May '09

Author: hailfinger Date: 2009-05-26 23:26:23 +0200 (Tue, 26 May 2009) New Revision: 550 Modified: trunk/flash.h trunk/flashchips.c Log: Add TI TMS29F002RT and TMS29F002RB probe and read support to flashrom. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-05-26 21:25:08 UTC (rev 549) +++ trunk/flash.h 2009-05-26 21:26:23 UTC (rev 550) @@ -525,6 +525,9 @@ #define S29C31004T 0x63 #define TI_ID 0x97 /* Texas Instruments */ +#define TI_OLD_ID 0x01 /* TI chips from last century */ +#define TI_TMS29F002RT 0xB0 +#define TI_TMS29F002RB 0x34 /* * W25X chips are SPI, first byte of device ID is memory type, second Modified: trunk/flashchips.c =================================================================== --- trunk/flashchips.c 2009-05-26 21:25:08 UTC (rev 549) +++ trunk/flashchips.c 2009-05-26 21:26:23 UTC (rev 550) @@ -2055,6 +2055,34 @@ }, { + .vendor = "Texas Instruments", + .name = "TMS29F002RB", + .manufacture_id = TI_OLD_ID, + .model_id = TI_TMS29F002RB, + .total_size = 256, + .page_size = 16384, /* Non-uniform sectors */ + .tested = TEST_UNTESTED, + .probe = probe_jedec, + .erase = NULL, + .write = NULL, + .read = read_memmapped, + }, + + { + .vendor = "Texas Instruments", + .name = "TMS29F002RT", + .manufacture_id = TI_OLD_ID, + .model_id = TI_TMS29F002RT, + .total_size = 256, + .page_size = 16384, /* Non-uniform sectors */ + .tested = TEST_UNTESTED, + .probe = probe_jedec, + .erase = NULL, + .write = NULL, + .read = read_memmapped, + }, + + { .vendor = "Winbond", .name = "W25x10", .manufacture_id = WINBOND_NEX_ID,

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[PATCH] flashrom: Use REMS instead of RES in the ICH SPI opcode table
by Carl-Daniel Hailfinger 26 May '09

26 May '09

Use REMS instead of RES in the ICH SPI default opcode table. RES is Read Electronic Signature (1 Byte, identical for different chips) REMS is Read Electronic Manufacturer Signature (2 Bytes, unique) Of the chips which don't support RDID, a sizable portion supports REMS which gives us both a manufacturer ID and a device ID. This is clearly superior to having only a device ID (the RES case) which has multiple documented collisions. The best way forward would be to have the ICH SPI driver reprogram the opcode menu on the fly if the opcode menu doesn't contain the requested opcode and the opcode menu is not locked. Until that happens, this patch improves detection accuracy by a factor of 256 for some chips. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-ichspi_res_rems_exchange/ichspi.c =================================================================== --- flashrom-ichspi_res_rems_exchange/ichspi.c (Revision 515) +++ flashrom-ichspi_res_rems_exchange/ichspi.c (Arbeitskopie) @@ -186,7 +186,7 @@ {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data {JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 1}, // Erase Sector {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg - {JEDEC_RES, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Resume Deep Power-Down + {JEDEC_REMS, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Electronic Manufacturer Signature {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 1}, // Write Status Register {JEDEC_RDID, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read JDEC ID {JEDEC_CE_C7, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 1}, // Bulk erase -- http://www.hailfinger.org/ Index: flashrom-ichspi_res_rems_exchange/ichspi.c =================================================================== --- flashrom-ichspi_res_rems_exchange/ichspi.c (Revision 515) +++ flashrom-ichspi_res_rems_exchange/ichspi.c (Arbeitskopie) @@ -186,7 +186,7 @@ {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data {JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 1}, // Erase Sector {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg - {JEDEC_RES, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Resume Deep Power-Down + {JEDEC_REMS, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Electronic Manufacturer Signature {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 1}, // Write Status Register {JEDEC_RDID, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read JDEC ID {JEDEC_CE_C7, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 1}, // Bulk erase

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[flashrom] r549 - trunk
by svn＠coreboot.org 26 May '09

26 May '09

Author: hailfinger Date: 2009-05-26 23:25:08 +0200 (Tue, 26 May 2009) New Revision: 549 Modified: trunk/ichspi.c Log: Use REMS instead of RES in the ICH SPI default opcode table. RES is Read Electronic Signature (1 Byte, identical for different chips) REMS is Read Electronic Manufacturer Signature (2 Bytes, mostly unique) RDID is Read JEDEC ID (3 bytes, unique) Of the chips which don't support RDID, a sizable portion supports REMS which gives us both a manufacturer ID and a device ID. This is clearly superior to having only a device ID (the RES case) which has multiple documented collisions. The RES/REMS problem is aggravated by inconsistent naming in vendor data sheets. What's in a name? Considering that we have 1-byte IDs, 2-byte IDs and 3+byte IDs with varying names but mostly consistent opcodes, it makes sense to set our own standard about how the opcodes are called. The best way forward would be to have the ICH SPI driver reprogram the opcode menu on the fly if the opcode menu doesn't contain the requested opcode and the opcode menu is not locked. Until that happens, this patch improves detection accuracy by a factor of 256 for some chips. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Tested-by: Uwe Hermann with the flash chip "SST SST25VF040.REMS". Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: trunk/ichspi.c =================================================================== --- trunk/ichspi.c 2009-05-26 09:48:28 UTC (rev 548) +++ trunk/ichspi.c 2009-05-26 21:25:08 UTC (rev 549) @@ -179,7 +179,7 @@ {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data {JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 1}, // Erase Sector {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg - {JEDEC_RES, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Resume Deep Power-Down + {JEDEC_REMS, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Electronic Manufacturer Signature {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 1}, // Write Status Register {JEDEC_RDID, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read JDEC ID {JEDEC_CE_C7, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 1}, // Bulk erase

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build service results for r4311
by coreboot information 26 May '09

26 May '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "oxygene" checked in revision 4311 to the coreboot repository. This caused the following changes: Change Log: Clean up acpi table writing code, and don't rely on a given alignment for the RSDP and RSDT - look it up instead. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Myles Watson <mylesgw(a)gmail.com> Build Log: Compilation of embeddedplanet:ep405pc is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4311&device=ep405pc&vendor… Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4311&device=sandpointx3_al… Compilation of totalimpact:briq is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4311&device=briq&vendor=to… If something broke during this checkin please be a pain in oxygene's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[v2] r4311 - trunk/coreboot-v2/src/arch/i386/boot
by svn＠coreboot.org 26 May '09

26 May '09

Author: oxygene Date: 2009-05-26 21:39:14 +0200 (Tue, 26 May 2009) New Revision: 4311 Modified: trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c trunk/coreboot-v2/src/arch/i386/boot/tables.c Log: Clean up acpi table writing code, and don't rely on a given alignment for the RSDP and RSDT - look it up instead. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c 2009-05-26 18:01:53 UTC (rev 4310) +++ trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c 2009-05-26 19:39:14 UTC (rev 4311) @@ -429,9 +429,8 @@ low_table_end); head = lb_table_init(low_table_end); lb_forward(head, (struct lb_header*)rom_table_end); - lb_table_fini(head, 0); - low_table_end = (unsigned long)head; + low_table_end = (unsigned long) lb_table_fini(head, 0); printk_debug("New low_table_end: 0x%08lx\n", low_table_end); printk_debug("Now going to write high coreboot table at 0x%08lx\n", rom_table_end); Modified: trunk/coreboot-v2/src/arch/i386/boot/tables.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/tables.c 2009-05-26 18:01:53 UTC (rev 4310) +++ trunk/coreboot-v2/src/arch/i386/boot/tables.c 2009-05-26 19:39:14 UTC (rev 4311) @@ -63,20 +63,15 @@ { unsigned long low_table_start, low_table_end; unsigned long rom_table_start, rom_table_end; -#if HAVE_MP_TABLE == 1 - unsigned long new_low_table_end; -#endif /* Even if high tables are configured, some tables are copied both to * the low and the high area, so payloads and OSes don't need to know * about the high tables. */ - unsigned long high_rsdp; - unsigned long high_table_start=0, high_table_end=0; + unsigned long high_table_end=0; if (high_tables_base) { printk_debug("High Tables Base is %llx.\n", high_tables_base); - high_table_start = high_tables_base; high_table_end = high_tables_base; } else { printk_err("ERROR: High Tables Base is not set.\n"); @@ -111,14 +106,22 @@ /* Write ACPI tables to F segment and high tables area */ #if HAVE_ACPI_TABLES == 1 if (high_tables_base) { - unsigned long rsdt_location; - high_rsdp = ALIGN(high_table_end, 16); + unsigned long acpi_start = high_table_end; + rom_table_end = ALIGN(rom_table_end, 16); high_table_end = write_acpi_tables(high_table_end); + while (acpi_start < high_table_end) { + if (memcmp(((acpi_rsdp_t *)acpi_start)->signature, RSDP_SIG, 8) == 0) { + break; + } + acpi_start++; + } + if (acpi_start != high_table_end) { + acpi_write_rsdp((acpi_rsdp_t *)rom_table_end, ((acpi_rsdp_t *)acpi_start)->rsdt_address); + } else { + printk_err("ERROR: Didn't find RSDP in high table.\n"); + } high_table_end = ALIGN(high_table_end, 1024); - rsdt_location = (unsigned long)(((acpi_rsdp_t*)high_rsdp)->rsdt_address); - printk_debug("high mem RSDP at %x, RSDT at %x\n", high_rsdp, rsdt_location); - acpi_write_rsdp((acpi_rsdp_t *)rom_table_end, (acpi_rsdt_t *)rsdt_location); - rom_table_end = ALIGN(ALIGN(rom_table_end, 16) + sizeof(acpi_rsdp_t), 16); + rom_table_end = ALIGN(rom_table_end + sizeof(acpi_rsdp_t), 16); } else { rom_table_end = write_acpi_tables(rom_table_end); rom_table_end = ALIGN(rom_table_end, 1024); @@ -164,7 +167,11 @@ if (high_tables_base) { /* Also put a forwarder entry into 0-4K */ write_coreboot_table(low_table_start, low_table_end, - high_table_start, high_table_end); + high_tables_base, high_table_end); + if (high_table_end > high_tables_base + high_tables_size) + printk_err("%s: High tables didn't fit in %llx (%llx)\n", + __func__, high_tables_size, high_table_end - + high_tables_base); } else { /* The coreboot table must be in 0-4K or 960K-1M */ write_coreboot_table(low_table_start, low_table_end,

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[PATCH] Table cleanup continued
by Myles Watson 26 May '09

26 May '09

I'm still worried about someone changing the alignment of the rdsp and breaking the high tables code. This patch moves rsdp table generation into acpi_tables and cleans up a couple of unused variables. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

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status of coreboot on Asus A8N-E
by Pierre Schmitz 26 May '09

26 May '09

Hi there, I have an A8N-E from Asus and according to your wiki it is supported by coreboot: http://www.coreboot.org/ASUS_A8N-E I did search the wiki, mailing list archives and even had a look at the source. But I am not sure about the statement about the PCIx16 slot: "Doesn't seem to work, yet (?)" Is this still valid and would it mean I wont have any display output? The latter would be some kind of showstopper for me :-) Greetings, Pierre -- Pierre Schmitz Clemens-August-Straße 76 53115 Bonn Telefon 0228 9716608 Mobil 0160 95269831 Jabber pierre(a)jabber.archlinux.de WWW http://www.archlinux.de

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build service results for r4310
by coreboot information 26 May '09

26 May '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 4310 to the coreboot repository. This caused the following changes: Change Log: Tell lpgcc about the target architecture directory. This slipped through since FILO does not use lpgcc (yet) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Build Log: Compilation of embeddedplanet:ep405pc is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4310&device=ep405pc&vendor… Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4310&device=sandpointx3_al… Compilation of totalimpact:briq is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4310&device=briq&vendor=to… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[v2] r4310 - trunk/payloads/libpayload/bin
by svn＠coreboot.org 26 May '09

26 May '09

Author: stepan Date: 2009-05-26 20:01:53 +0200 (Tue, 26 May 2009) New Revision: 4310 Modified: trunk/payloads/libpayload/bin/lpgcc Log: Tell lpgcc about the target architecture directory. This slipped through since FILO does not use lpgcc (yet) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: trunk/payloads/libpayload/bin/lpgcc =================================================================== --- trunk/payloads/libpayload/bin/lpgcc 2009-05-26 14:49:59 UTC (rev 4309) +++ trunk/payloads/libpayload/bin/lpgcc 2009-05-26 18:01:53 UTC (rev 4310) @@ -48,6 +48,9 @@ # This will set the _LIBDIR and _INCDIR variables used below . $BASE/lp.functions +# include libpayload config +. $BASE/../libpayload.config + _LDSCRIPT="-Wl,-T,$_LIBDIR/libpayload.ldscript" trygccoption() { @@ -97,8 +100,16 @@ shift done -_CFLAGS="-m32 -nostdinc -nostdlib -I$_INCDIR" +if [ "$CONFIG_TARGET_I386" = "y" ]; then + _ARCHINCDIR=$_INCDIR/i386 +fi +if [ "$CONFIG_TARGET_POWERPC" = "y" ]; then + _ARCHINCDIR=$_INCDIR/powerpc +fi + +_CFLAGS="-m32 -nostdinc -nostdlib -I$_INCDIR -I$_ARCHINCDIR" + # Check for the -fno-stack-protector silliness trygccoption -fno-stack-protector

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build service results for r4309
by coreboot information 26 May '09

26 May '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "oxygene" checked in revision 4309 to the coreboot repository. This caused the following changes: Change Log: Make printk_* behaviour more consistent. Without it, side effects in the arguments (eg. a pci config read, or variable increment) "vanish" with the message, and the behaviour changes. Some of these effects might be unwanted, but at least they are consistent now. To reduce the memory footprint slightly, the formatted strings are discarded. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of embeddedplanet:ep405pc is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4309&device=ep405pc&vendor… Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4309&device=sandpointx3_al… Compilation of totalimpact:briq is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4309&device=briq&vendor=to… If something broke during this checkin please be a pain in oxygene's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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coreboot May 2009