coreboot May 2009

coreboot@coreboot.org

92 participants
571 discussions

Asus M2V flashrom success
by Henri Valta 28 May '09

28 May '09

Hello, I just upgraded the BIOS on my Asus M2V using flashrom (version r0.9+r446, from debian package) successfully. This mainboard is not currently on the supported mainboards list, so it should probably be added. Regards, Henri Valta

2 2

Debug help
by Myles Watson 28 May '09

28 May '09

I can't figure out how to track this down. I get serial corruption and missing output lines. The difference in the setup is that one boot has a module installed and the other one doesn't. The broken one doesnt :( Look at the first two lines of the logs... How would I go about tracking this down? What could eat my serial output? I'm on a single processor machine. Full logs available if anyone wants them. BTW: I've never gotten scan-build to work right on my machine. Patrick or Stefan, do you have a new run available somewhere? Thanks, Myles Broken log: PCI: 00:0d.0 compute_allocate_resource 0000a0 gran: 20 done mputeemem: base: fff00000 size: 00000000 align: 20 gran: 20 PCI: 00:0d.0 read_resources bCI00e:0:01.00.0 1820x00002087] io PCI: 00:07.0 14 * [0x00002090 - 0x00002093] io PCI: 00:07.0 1c * [0x000020a0 - 0x000020a3] io PCI: 00:08.0 14 * [0x000020b0 - 0x000020b3] io PCI: 00:08.0 1c * [0x000020c0 - 0x000020c3] io OK log: PCI: 00:0d.0 compute_allocate_resource prefmem: base: 00000000 size: 00000000 align: 20 gran: 20 done PCI: 00:0d.0 compute_allocate_resource prefmem: base: fff00000 size: 00000000 align: 20 gran: 20 PCI: 00:0d.0 read_resources bus 2 link: 0 PCI: 00:0d.0 read_resources bus 2 link: 0 done PCI: 00:0d.0 compute_allocate_resource prefmem: base: fff00000 size: 00000000 align: 20 gran: 20 done PCI: 00:0d.0 24 <- [0x00fff00000 - 0x00ffefffff] size 0x00000000 gran 0x14 bus 02 prefmem PCI: 00:0d.0 compute_allocate_resource mem: base: 00000000 size: 00000000 align: 20 gran: 20 PCI: 00:0d.0 read_resources bus 2 link: 0 PCI: 00:0d.0 read_resources bus 2 link: 0 done PCI: 00:0d.0 compute_allocate_resource mem: base: 00000000 size: 00000000 align: 20 gran: 20 done PCI: 00:0d.0 compute_allocate_resource mem: base: fff00000 size: 00000000 align: 20 gran: 20 PCI: 00:0d.0 read_resources bus 2 link: 0 PCI: 00:0d.0 read_resources bus 2 link: 0 done PCI: 00:0d.0 compute_allocate_resource mem: base: fff00000 size: 00000000 align: 20 gran: 20 done PCI: 00:0d.0 20 <- [0x00fff00000 - 0x00ffefffff] size 0x00000000 gran 0x14 bus 02 mem PCI: 00:0e.0 compute_allocate_resource io: base: 00000000 size: 00000000 align: 12 gran: 12 PCI: 00:0e.0 read_resources bus 3 link: 0 PCI: 00:0e.0 read_resources bus 3 link: 0 done PCI: 00:0e.0 compute_allocate_resource io: base: 00000000 size: 00000000 align: 12 gran: 12 done PCI: 00:0e.0 compute_allocate_resource io: base: fffff000 size: 00000000 align: 12 gran: 12 PCI: 00:0e.0 read_resources bus 3 link: 0 PCI: 00:0e.0 read_resources bus 3 link: 0 done PCI: 00:0e.0 compute_allocate_resource io: base: fffff000 size: 00000000 align: 12 gran: 12 done PCI: 00:0e.0 1c <- [0x00fffff000 - 0x00ffffefff] size 0x00000000 gran 0x0c bus 03 io PCI: 00:0e.0 compute_allocate_resource prefmem: base: 00000000 size: 00000000 align: 20 gran: 20 PCI: 00:0e.0 read_resources bus 3 link: 0 PCI: 00:0e.0 read_resources bus 3 link: 0 done PCI: 00:0e.0 compute_allocate_resource prefmem: base: 00000000 size: 00000000 align: 20 gran: 20 done PCI: 00:0e.0 compute_allocate_resource prefmem: base: fff00000 size: 00000000 align: 20 gran: 20 PCI: 00:0e.0 read_resources bus 3 link: 0 PCI: 00:0e.0 read_resources bus 3 link: 0 done PCI: 00:0e.0 compute_allocate_resource prefmem: base: fff00000 size: 00000000 align: 20 gran: 20 done PCI: 00:0e.0 24 <- [0x00fff00000 - 0x00ffefffff] size 0x00000000 gran 0x14 bus 03 prefmem PCI: 00:0e.0 compute_allocate_resource mem: base: 00000000 size: 00000000 align: 20 gran: 20 PCI: 00:0e.0 read_resources bus 3 link: 0 PCI: 00:0e.0 read_resources bus 3 link: 0 done PCI: 00:0e.0 compute_allocate_resource mem: base: 00000000 size: 00000000 align: 20 gran: 20 done PCI: 00:0e.0 compute_allocate_resource mem: base: fff00000 size: 00000000 align: 20 gran: 20 PCI: 00:0e.0 read_resources bus 3 link: 0 PCI: 00:0e.0 read_resources bus 3 link: 0 done PCI: 00:0e.0 compute_allocate_resource mem: base: fff00000 size: 00000000 align: 20 gran: 20 done PCI: 00:0e.0 20 <- [0x00fff00000 - 0x00ffefffff] size 0x00000000 gran 0x14 bus 03 mem PCI: 00:18.0 read_resources bus 0 link: 0 done PCI: 00:09.0 1c * [0x00000000 - 0x00000fff] io PCI: 00:01.0 60 * [0x00001000 - 0x000010ff] io PCI: 00:01.0 64 * [0x00001400 - 0x000014ff] io PCI: 00:01.0 68 * [0x00001800 - 0x000018ff] io PCI: 00:01.0 10 * [0x00001c00 - 0x00001c7f] io PCI: 00:01.1 20 * [0x00001c80 - 0x00001cbf] io PCI: 00:01.1 24 * [0x00001cc0 - 0x00001cff] io PCI: 00:01.1 10 * [0x00002000 - 0x0000201f] io PCI: 00:06.0 20 * [0x00002020 - 0x0000202f] io PCI: 00:07.0 20 * [0x00002030 - 0x0000203f] io PCI: 00:08.0 20 * [0x00002040 - 0x0000204f] io PCI: 00:07.0 10 * [0x00002050 - 0x00002057] io PCI: 00:07.0 18 * [0x00002060 - 0x00002067] io PCI: 00:08.0 10 * [0x00002070 - 0x00002077] io PCI: 00:08.0 18 * [0x00002080 - 0x00002087] io PCI: 00:07.0 14 * [0x00002090 - 0x00002093] io PCI: 00:07.0 1c * [0x000020a0 - 0x000020a3] io PCI: 00:08.0 14 * [0x000020b0 - 0x000020b3] io PCI: 00:08.0 1c * [0x000020c0 - 0x000020c3] io

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[flashrom] r554 - trunk
by svn＠coreboot.org 28 May '09

28 May '09

Author: uwe Date: 2009-05-28 17:07:42 +0200 (Thu, 28 May 2009) New Revision: 554 Modified: trunk/README trunk/board_enable.c trunk/flash.h Log: Random flashrom updates: - Add explicit installation instructions in the README. - Code cleanups, coding style fixes, drop dead code. - Drop duplicate board listings from -L output (some boards were explicitly recorded in boards_ok[] _and_ implicitly via the board-enables table. - Add MS-xxxx numbers to MSI boards where we can find that info. - Fix typo, "K8T Neo2" should have been "K8T Neo2-F" actually, at least according to the comment of w83627thf_gpio4_4_raise_2e() which says "Suited for: MSI K8T Neo2-F". Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/README =================================================================== --- trunk/README 2009-05-28 00:00:23 UTC (rev 553) +++ trunk/README 2009-05-28 15:07:42 UTC (rev 554) @@ -15,7 +15,7 @@ (see http://coreboot.org for details on coreboot) -Build Requirements +Build Instructions ------------------ To build flashrom you need to install the following packages or ports: @@ -55,6 +55,18 @@ DirectIO is available at http://www.coresystems.de/en/directio. +Installation +------------ + +In order to install flashrom and the manpage into /usr/local, type: + + sudo make install + +For installation in a different directory use DESTDIR, e.g. like this: + + sudo make DESTDIR=/usr install + + Usage / Options --------------- Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-05-28 00:00:23 UTC (rev 553) +++ trunk/board_enable.c 2009-05-28 15:07:42 UTC (rev 554) @@ -688,10 +688,10 @@ /* Note: There are >= 2 version of the Kontron 986LCD-M/mITX! */ {0x8086, 0x27b8, 0, 0, 0, 0, 0, 0, "kontron", "986lcd-m", "Kontron", "986LCD-M", board_kontron_986lcd_m}, {0x10ec, 0x8168, 0x10ec, 0x8168, 0x104c, 0x8023, 0x104c, 0x8019, "kontron", "986lcd-m", "Kontron", "986LCD-M", board_kontron_986lcd_m}, - {0x10de, 0x005e, 0, 0, 0, 0, 0, 0, "msi", "k8n-neo3", "MSI", "K8N Neo3", w83627thf_gpio4_4_raise_4e}, - {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, "MSI", "K8T Neo2", w83627thf_gpio4_4_raise_2e}, - {0x1106, 0x0571, 0x1462, 0x7120, 0, 0, 0, 0, "msi", "kt4v", "MSI", "KT4V", board_msi_kt4v}, - {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, "msi", "kt4ultra", "MSI", "KT4 Ultra", board_msi_kt4v}, + {0x10de, 0x005e, 0, 0, 0, 0, 0, 0, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", w83627thf_gpio4_4_raise_4e}, + {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, "MSI", "MS-6702E (K8T Neo2-F)",w83627thf_gpio4_4_raise_2e}, + {0x1106, 0x0571, 0x1462, 0x7120, 0, 0, 0, 0, "msi", "kt4v", "MSI", "MS-6712 (KT4V)", board_msi_kt4v}, + {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, "msi", "kt4ultra", "MSI", "MS-6590 (KT4 Ultra)",board_msi_kt4v}, {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, "MSI", "MS-7046", ich6_gpio19_raise}, {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", board_asus_a7v8x_mx}, {0x1106, 0x0314, 0x1106, 0xaa08, 0x1106, 0x3227, 0x1106, 0xAA08, NULL, NULL, "VIA", "EPIA-CN", board_via_epia_sp}, @@ -721,7 +721,6 @@ { "ASUS", "A7N8X Deluxe", }, { "ASUS", "A7V400-MX", }, { "ASUS", "A7V8X-MX", }, - { "ASUS", "P4B266", }, { "ASUS", "A8V-E SE", }, { "ASUS", "P2L97-S", }, { "ASUS", "M2A-MX", }, @@ -734,9 +733,7 @@ { "GIGABYTE", "GA-6ZMA", }, { "Intel", "EP80759", }, { "Jetway", "J7F4K1G5D-PB", }, - { "MSI", "K7N2", }, - { "MSI", "KT4V", }, - { "MSI", "MS-7046", }, + { "MSI", "MS-6570 (K7N2)", }, { "MSI", "MS-7065", }, { "MSI", "MS-7236 (945PL Neo3)", }, { "MSI", "MS-7345 (P35 Neo2-FIR)", }, @@ -771,9 +768,6 @@ { "Tyan", "S5376G2NR/S5376WAG2NR", }, { "Tyan", "S5377", }, { "Tyan", "S5397", }, - { "VIA", "EPIA-M", }, - { "VIA", "EPIA-MII", }, - { "VIA", "EPIA-CN", }, { "VIA", "EPIA-LN", }, { "VIA", "VB700X", }, { "VIA", "NAB74X0", }, Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-05-28 00:00:23 UTC (rev 553) +++ trunk/flash.h 2009-05-28 15:07:42 UTC (rev 554) @@ -92,7 +92,8 @@ int (*init) (void); int (*shutdown) (void); - void * (*map_flash_region) (const char *descr, unsigned long phys_addr, size_t len); + void * (*map_flash_region) (const char *descr, unsigned long phys_addr, + size_t len); void (*unmap_flash_region) (void *virt_addr, size_t len); void (*chip_writeb) (uint8_t val, chipaddr addr); @@ -151,20 +152,20 @@ #define TEST_UNTESTED 0 -#define TEST_OK_PROBE (1<<0) -#define TEST_OK_READ (1<<1) -#define TEST_OK_ERASE (1<<2) -#define TEST_OK_WRITE (1<<3) -#define TEST_OK_PR (TEST_OK_PROBE|TEST_OK_READ) -#define TEST_OK_PRE (TEST_OK_PROBE|TEST_OK_READ|TEST_OK_ERASE) -#define TEST_OK_PREW (TEST_OK_PROBE|TEST_OK_READ|TEST_OK_ERASE|TEST_OK_WRITE) +#define TEST_OK_PROBE (1 << 0) +#define TEST_OK_READ (1 << 1) +#define TEST_OK_ERASE (1 << 2) +#define TEST_OK_WRITE (1 << 3) +#define TEST_OK_PR (TEST_OK_PROBE | TEST_OK_READ) +#define TEST_OK_PRE (TEST_OK_PROBE | TEST_OK_READ | TEST_OK_ERASE) +#define TEST_OK_PREW (TEST_OK_PROBE | TEST_OK_READ | TEST_OK_ERASE | TEST_OK_WRITE) #define TEST_OK_MASK 0x0f -#define TEST_BAD_PROBE (1<<4) -#define TEST_BAD_READ (1<<5) -#define TEST_BAD_ERASE (1<<6) -#define TEST_BAD_WRITE (1<<7) -#define TEST_BAD_PREW (TEST_BAD_PROBE|TEST_BAD_READ|TEST_BAD_ERASE|TEST_BAD_WRITE) +#define TEST_BAD_PROBE (1 << 4) +#define TEST_BAD_READ (1 << 5) +#define TEST_BAD_ERASE (1 << 6) +#define TEST_BAD_WRITE (1 << 7) +#define TEST_BAD_PREW (TEST_BAD_PROBE | TEST_BAD_READ | TEST_BAD_ERASE | TEST_BAD_WRITE) #define TEST_BAD_MASK 0xf0 extern struct flashchip flashchips[]; @@ -534,7 +535,7 @@ * byte of device ID is related to log(bitsize). */ #define WINBOND_ID 0xDA /* Winbond */ -#define WINBOND_NEX_ID 0xEF /* Winbond (ex Nexcom) serial flash devices */ +#define WINBOND_NEX_ID 0xEF /* Winbond (ex Nexcom) serial flashes */ #define W_25X10 0x3011 #define W_25X20 0x3012 #define W_25X40 0x3013 @@ -659,8 +660,6 @@ /* nic3com.c */ int nic3com_init(void); int nic3com_shutdown(void); -void *nic3com_map(const char *descr, unsigned long phys_addr, size_t len); -void nic3com_unmap(void *virt_addr, size_t len); void nic3com_chip_writeb(uint8_t val, chipaddr addr); uint8_t nic3com_chip_readb(const chipaddr addr); extern struct pcidev_status nics_3com[]; @@ -668,8 +667,6 @@ /* satasii.c */ int satasii_init(void); int satasii_shutdown(void); -void *satasii_map(const char *descr, unsigned long phys_addr, size_t len); -void satasii_unmap(void *virt_addr, size_t len); void satasii_chip_writeb(uint8_t val, chipaddr addr); uint8_t satasii_chip_readb(const chipaddr addr); extern struct pcidev_status satas_sii[]; @@ -850,7 +847,8 @@ /* wbsio_spi.c */ int wbsio_check_for_spi(const char *name); -int wbsio_spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); +int wbsio_spi_command(unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr); int wbsio_spi_read(struct flashchip *flash, uint8_t *buf); int wbsio_spi_write_1(struct flashchip *flash, uint8_t *buf);

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[flashrom] GIGABYTE MA780G-UD3H identify as GA-MA78GM-S2H
by Stefan Roggensack 28 May '09

28 May '09

Hello, when I run flashrom (r551) it identfiy my board as GA-MA78GM-S2H. But I have a Gigabyte MA780G-UD3H. I try to read my BIOS and it seems to work. (File size is the same as the backup made with the Gigabyte Q-Flash; For writting I don't have the boldness ...) I attach the output of lspci and flashrom. Maybe the identifying could be adjust. Stefan flashrom v0.9.0-r551 No coreboot table found. Found chipset "AMD SB700", enabling flash write... OK. Found board "GIGABYTE GA-MA78GM-S2H", enabling flash write... Serial flash segment 0xfffe0000-0xffffffff enabled Serial flash segment 0x000e0000-0x000fffff enabled Serial flash segment 0xffee0000-0xffefffff disabled Serial flash segment 0xfff80000-0xfffeffff enabled LPC write to serial flash enabled serial flash pin 29 OK. Calibrating delay loop... OK. Found chip "SST SST25VF080B" (1024 KB) at physical address 0xfff00000. No operations were specified. 00:00.0 Host bridge: Advanced Micro Devices [AMD] RS780 Host Bridge 00:01.0 PCI bridge: Advanced Micro Devices [AMD] RS780 PCI to PCI bridge (int gfx) 00:0a.0 PCI bridge: Advanced Micro Devices [AMD] RS780 PCI to PCI bridge (PCIE port 5) 00:11.0 SATA controller: ATI Technologies Inc SB700/SB800 SATA Controller [AHCI mode] 00:12.0 USB Controller: ATI Technologies Inc SB700/SB800 USB OHCI0 Controller 00:12.1 USB Controller: ATI Technologies Inc SB700 USB OHCI1 Controller 00:12.2 USB Controller: ATI Technologies Inc SB700/SB800 USB EHCI Controller 00:13.0 USB Controller: ATI Technologies Inc SB700/SB800 USB OHCI0 Controller 00:13.1 USB Controller: ATI Technologies Inc SB700 USB OHCI1 Controller 00:13.2 USB Controller: ATI Technologies Inc SB700/SB800 USB EHCI Controller 00:14.0 SMBus: ATI Technologies Inc SBx00 SMBus Controller (rev 3a) 00:14.1 IDE interface: ATI Technologies Inc SB700/SB800 IDE Controller 00:14.2 Audio device: ATI Technologies Inc SBx00 Azalia (Intel HDA) 00:14.3 ISA bridge: ATI Technologies Inc SB700/SB800 LPC host controller 00:14.4 PCI bridge: ATI Technologies Inc SBx00 PCI to PCI Bridge 00:14.5 USB Controller: ATI Technologies Inc SB700/SB800 USB OHCI2 Controller 00:18.0 Host bridge: Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] HyperTransport Configuration 00:18.1 Host bridge: Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] Address Map 00:18.2 Host bridge: Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] DRAM Controller 00:18.3 Host bridge: Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] Miscellaneous Control 00:18.4 Host bridge: Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] Link Control 01:05.0 VGA compatible controller: ATI Technologies Inc Radeon HD 3200 Graphics 01:05.1 Audio device: ATI Technologies Inc RS780 Azalia controller 02:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller (rev 02) 03:0e.0 FireWire (IEEE 1394): Texas Instruments TSB43AB23 IEEE-1394a-2000 Controller (PHY/Link)

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Re: [coreboot] [v2] r4317 - trunk/coreboot-v2/src/northbridge/via/vx800
by Peter Stuge 28 May '09

28 May '09

svn(a)coreboot.org wrote: > Make directory hierarchy flat to match the same layout we use > for other chipsets, as suggested on IRC. I don't agree so much with this but oh well. Maybe there will be opportunity for unifying DDR2 code. //Peter

4 4

Fwd: Board-Info
by ron minnich 28 May '09

28 May '09

---------- Forwarded message ---------- From: Tobias Müller <Tobias_Mueller(a)twam.info> Date: 2009/5/19 Subject: Board-Info To: rminnich(a)gmail.com Hello, I've got an "855GME-MGF" Board from "DFI". Flashrom didn't work me here: server ~ # flashrom -w -v 55PMD810.BIN Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel 6300ESB", enabling flash write... OK. Found chip "Winbond W39V040FA" (512 KB) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. 0007 at address: 0x00070000 Verifying flash... FAILED at 0x00000000! Expected=0xa6, Read=0x49 server ~ # flashrom -E Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel 6300ESB", enabling flash write... OK. Found chip "Winbond W39V040FA" (512 KB) at physical address 0xfff80000. Erasing flash chip... FAILED! ERROR at 0x00000000: Expected=0xff, Read=0x49 And I've got another Board, an ALIX.3D3 from PC Engines, the successor of ALIX.3C3. Here it works fine. Cheers Tobias

2 1

[Patch] Flashrom: Add nforce2 chipset enable.
by Luc Verhaegen 28 May '09

28 May '09

Since no-one seems to have solid information as to the origins of the supposedly known brokenness of flashrom on the Asus A7N8X-E, i attach here a patch to add nforce2 support, which will hopefully fix this board. Attached as well is some lspci info i managed to pluck off the interweb. No subsystem ids though, but a board specific enable does not seem necessary for this board. Luc Verhaegen.

3 6

[flashrom] r553 - trunk
by svn＠coreboot.org 28 May '09

28 May '09

Author: uwe Date: 2009-05-28 02:00:23 +0200 (Thu, 28 May 2009) New Revision: 553 Modified: trunk/board_enable.c Log: A bunch of flashrom board updates: Marked as OK: - ASUS M2V (reported by Henri Valta <henri.valta(a)kemi.fi>) http://www.coreboot.org/pipermail/coreboot/2009-May/048674.html - Jetway J7F4K1G5D-PB (reported by Kevin O'Connor <kevin(a)koconnor.net>) - PC Engines Alix.3d3 (reported by Tobias M?\195?\188ller <Tobias_Mueller(a)twam.info>) http://www.coreboot.org/pipermail/coreboot/2009-May/048549.html - MSI K7N2 (reported by Maciej Pijanka <maciej.pijanka(a)gmail.com>) http://www.coreboot.org/pipermail/coreboot/2009-May/048777.html Marked as (so far) non-working: - DFI 855GME-MGF (reported by Tobias M?\195?\188ller <Tobias_Mueller(a)twam.info>) http://www.coreboot.org/pipermail/coreboot/2009-May/048549.html - ASUS M3N78 Pro (reported by Piotr Esden-Tempski <esden(a)esden.net>) As discussed on IRC this is an MCP78 chipset with SPI translation apparently done in the southbridge, and we have no NVIDIA datasheets, of course. So the situation for this board will probably not change anytime soon. - MSI MS-6178 (reported by Uwe Hermann <uwe(a)hermann-uwe.de>) I tested write/erase will not work on this board, so a write-enable is needed. In _addition_, the board immediately powers off if you hot-unplug the PLCC chip, so I guess there's some SMI interference. - GIGABYTE GA-K8N-SLI (reported by Alexander Gordeev <lasaine(a)lvk.cs.msu.su>) This is currently being discussed on the mailing list (see http://www.coreboot.org/pipermail/coreboot/2009-May/048717.html) and it's very likely that we'll be able to add a board-enable, so this board can be maked as OK soonish. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-05-27 23:17:40 UTC (rev 552) +++ trunk/board_enable.c 2009-05-28 00:00:23 UTC (rev 553) @@ -713,6 +713,7 @@ { "ASUS", "A8V-E Deluxe", }, { "ASUS", "M2A-VM", }, { "ASUS", "M2N-E", }, + { "ASUS", "M2V", }, { "ASUS", "P2B", }, { "ASUS", "P2B-F", }, { "ASUS", "P2B-D", }, @@ -732,6 +733,8 @@ { "GIGABYTE", "GA-6BXDU", }, { "GIGABYTE", "GA-6ZMA", }, { "Intel", "EP80759", }, + { "Jetway", "J7F4K1G5D-PB", }, + { "MSI", "K7N2", }, { "MSI", "KT4V", }, { "MSI", "MS-7046", }, { "MSI", "MS-7065", }, @@ -743,6 +746,7 @@ { "PC Engines", "Alix.2c2", }, { "PC Engines", "Alix.2c3", }, { "PC Engines", "Alix.3c3", }, + { "PC Engines", "Alix.3d3", }, { "RCA", "RM4100", }, { "Supermicro", "H8QC8", }, { "Sun", "Blade x6250", }, @@ -782,6 +786,7 @@ const struct board_info boards_bad[] = { /* Verified non-working boards (for now). */ { "Abit", "IS-10", }, + { "ASUS", "M3N78 Pro", }, { "ASUS", "MEW-AM", }, { "ASUS", "MEW-VM", }, { "ASUS", "P3B-F", }, @@ -789,7 +794,10 @@ { "ASUS", "P5BV-M", }, { "Biostar", "M6TBA", }, { "Boser", "HS-6637", }, + { "DFI", "855GME-MGF", }, { "FIC", "VA-502", }, + { "GIGABYTE", "GA-K8N-SLI", }, + { "MSI", "MS-6178", }, { "MSI", "MS-7260 (K9N Neo)", }, { "PCCHIPS", "M537DMA33", }, { "Soyo", "SY-5VD", },

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[flashrom] r552 - trunk
by svn＠coreboot.org 27 May '09

27 May '09

Author: uwe Date: 2009-05-28 01:17:40 +0200 (Thu, 28 May 2009) New Revision: 552 Modified: trunk/flashchips.c Log: Change 'Texas Instruments' to 'TI' in the flash chip table, as this is a very long name and currently even breaks -L output. We could of course fix that, but we already use short / abbreviated names for other vendors (AMD, ST, SST, PMC) so do it for TI also. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/flashchips.c =================================================================== --- trunk/flashchips.c 2009-05-27 11:40:08 UTC (rev 551) +++ trunk/flashchips.c 2009-05-27 23:17:40 UTC (rev 552) @@ -2055,7 +2055,7 @@ }, { - .vendor = "Texas Instruments", + .vendor = "TI", .name = "TMS29F002RB", .manufacture_id = TI_OLD_ID, .model_id = TI_TMS29F002RB, @@ -2069,7 +2069,7 @@ }, { - .vendor = "Texas Instruments", + .vendor = "TI", .name = "TMS29F002RT", .manufacture_id = TI_OLD_ID, .model_id = TI_TMS29F002RT,

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build service results for r4318
by coreboot information 27 May '09

27 May '09

Dear coreboot readers! This is the automatic build system of coreboot. The developer "uwe" checked in revision 4318 to the coreboot repository. This caused the following changes: Change Log: First batch of indent-aided code cleanups, more will follow. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of embeddedplanet:ep405pc is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4318&device=ep405pc&vendor… Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4318&device=sandpointx3_al… Compilation of totalimpact:briq is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4318&device=briq&vendor=to… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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coreboot May 2009