coreboot January 2009

coreboot@coreboot.org

66 participants
320 discussions

generic cpu detection proposal
by Holger Hesselbarth 27 Jan '09

27 Jan '09

i'm back after quite some time of silence but i've never lost track of the coreboot development though. the time has come to contribute some real code. i decided to start with a generic cpu detection routine that at a later point should be able to detect all cpus from the original Pentium upwards. my next step is to write configuration functions for all models depending on the manufacturer. the first goal is to make L2 cache available for all Slot1/Socket370 processors. i already took a look at the L2 init code from coreboot v1 and i guess i got it. some official intel document on L2 cache init would help though. the benefit of a generic would be that exchanging the cpu wouldn't rise the need to compile a new bios first. even if changing from one manufacturer to another. the drawback of a generic init routine would be that all init routines would be included in the final bios. so the routines should be kept as short as possible. to make some things user-configurable i propose a new section in the options file: cpu settings. mttr configuration could be called from the configuration routines or included in them. any thoughts on that? i also propose to enforce maximum performance settings on VIA/Cyrix, Centaur and older AMD processors as they have feature control registers which where meant to disable some advanced functions to maintain Intel Pentium compatibility. talking about Cyrix: i'll use the famous 5/2 division to identify the 6x86 with switched off cpuid and enable it by writing its internal configuration registers. i attached the files with the detection routines and the modified header files. the cpu_data structure in the cpu.h is losely based on the sources of x86info by Dave Jones. i also took the check_cpuid from his code. the copyright headers are not set in any of the files yet, but i didn't commit anything anyway ;) i didn't try to compile it, i just wanted to make sure i'm heading in the right direction. /* * (C) 2001 Dave Jones. * 2009 adapted for coreboot by Holger Hesselbarth * * Licensed under the terms of the GNU GPL License version 2. */ static int flag_is_changeable_p(unsigned long flag) { unsigned long f1, f2; __asm__ volatile("pushf\n\t" "pushf\n\t" "pop %0\n\t" "mov %0,%1\n\t" "xor %2,%0\n\t" "push %0\n\t" "popf\n\t" "pushf\n\t" "pop %0\n\t" "popf\n\t" : "=&r" (f1), "=&r" (f2) : "ir" (flag)); return ((f1^f2) & flag) != 0; } int check_cpuid(void) { return flag_is_changeable_p(0x200000); } /* * (C) 2009 Holger Hesselbarth */ #include <cpu/cpu.h> #include <identify_cpu.h> static void identify_cpu(struct cpu_data *cpu) { /* check if cpuid is supported */ if((check_cpuid()) == 0) { // TODO : check if this is a Cyrix cpu with cpuid disabled return; } /* gather basic cpu information */ get_basic_cpu_information(cpu); /* gather extended cpu information */ get_extended_cpu_information(cpu); return; }; static void get_basic_cpu_information(struct cpu_data *cpu) { unsigned int maxbi, vendor; /* get basic cpu information */ cpuid(CPU_BASIC_INF, &maxbi, &vendor, NULL, NULL); cpu->maxbi = (maxbi & 0xFFFF ); /* high-order word is non-zero on some Cyrix cpus */ if(cpu->maxbi < 1) { return; } /* get family, model, stepping and feature flags */ cpuid((CPU_BASIC_INF + 1), &eax, &ebx, &ecx, &edx); cpu->stepping = (eax & 0x0F); cpu->model = ((eax >> 4) & 0x0F); cpu->family = ((eax >> 8) & 0x0F); cpu->ecx_bi_flags = ecx; cpu->edx_bi_flags = edx; /* get more basic cpu information based on vendor */ switch(vendor) { case 0x756e6547 : /* uneG */ cpu->vendor = X86_VENDOR_INTEL; cpu->type = ((eax >> 12) & 0x03); if(cpu->family == 0xF) { cpu->emodel = ((eax >> 16) & 0x0F); cpu->efamily = ((eax >> 20) & 0xFF); } else if(cpu->family == 0x6) { cpu->emodel = ((eax >> 16) & 0x0F); } cpu->brand = (ebx & 0xFF); cpu->clflush = ((ebx >> 8) & 0xFF); cpu->apicid = ((ebx >> 24) & 0xFF); break; case 0x68747541 : /* thuA */ cpu->vendor = X86_VENDOR_AMD; // TODO : check for extended family & model break; case 0x69727943 : /* iryC */ cpu->vendor = X86_VENDOR_CYRIX; break; case 0x746e6543 : /* tneC */ cpu->vendor = X86_VENDOR_CENTAUR; break; // TODO : add more cpu makers default : cpu->vendor = X86_VENDOR_UNKNOWN; break; } return; }; static void get_extended_cpu_information(struct cpu_data *cpu) { /* get extended cpu information * the IDT WinChip C6 needs a special treatment */ if((cpu->vendor == X86_VENDOR_CENTAUR) && (cpu->model == 4)) { cpuid(CPU_C6_EXT_INF, &(cpu->maxei), NULL, NULL, NULL); } else { cpuid(CPU_EXT_INF, &(cpu->maxei), NULL, NULL, NULL); } return; }; #ifndef CPU_X86_IDENTIFY_CPU_H #define CPU_X86_IDENTIFY_CPU_H extern int check_cpuid(void); #define CPU_BASIC_INF 0x00000000 #define CPU_EXT_INF 0x80000000 #define CPU_C6_EXT_INF 0xC0000000 #endif /* CPU_Xf86_IDENTIFY_CPU_H */ #ifndef CPU_CPU_H #define CPU_CPU_H #include <arch/cpu.h> #define CPU_NAME_LEN 80 struct cpu_data { struct cpudata *next; unsigned char number; unsigned char vendor; unsigned char family; unsigned char model; unsigned char type; unsigned char stepping; unsigned char efamily; unsigned char emodel; unsigned char platform_id; unsigned char maxbi; unsigned int maxei; unsigned int ecx_bi_flags; unsigned int edx_bi_flags; unsigned int cachesize_L1_I; unsigned int cachesize_L1_D; unsigned int cachesize_L2; unsigned int cachesize_L3; unsigned int cachesize_trace; char name[CPU_NAME_LEN]; unsigned int nr_cores; unsigned int nr_logical; /* Intel specific bits */ unsigned char brand; unsigned char clflush; unsigned char apicid; /* Intel Pentium III serial number (PSN) */ unsigned int serialno[2]; }; struct device; struct bus; void cpu_initialize(void); void initialize_cpus(struct bus *cpu_bus); #define __cpu_driver __attribute__ ((used,__section__(".rodata.cpu_driver"))) /** start of compile time generated pci driver array */ extern struct cpu_driver cpu_drivers[]; /** end of compile time generated pci driver array */ extern struct cpu_driver ecpu_drivers[]; #endif /* CPU_CPU_H */

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Helping coreboot
by shirish 27 Jan '09

27 Jan '09

Hi all, I read a very interesting thread at ubuntuforums while I was looking for solution for my BIOS. http://ubuntuforums.org/showthread.php?t=961975 I saw the whole thread and at the very end http://ubuntuforums.org/showpost.php?p=6154877&postcount=32 "Developers on the Coreboot mailing list have clearly stated that this information is spamming the list. Unless you want to try a patch or make your own patch and you are fully ready to test Coreboot on your system there is no point in posting your information to the list," This is a pity. Is there a possibility that perhaps some of the info. could be put up somewhere and could be used at a later stage/state by the developers if it could be put at some central location? A kind of repository for the info. Another thing, (just for fun) I checked out the trunk and tried to make getpir . I do get the following error. shirish@shirish-desktop:~/coreboot-v2/util/getpir$ sudo make [sudo] password for shirish: gcc -O2 -D_GNU_SOURCE -DGETPIR -Wall -c -o getpir.o getpir.c gcc -O2 -D_GNU_SOURCE -DGETPIR -Wall -c -o checksum.o checksum.c gcc -O2 -D_GNU_SOURCE -DGETPIR -Wall -c -o code_gen.o code_gen.c gcc -O2 -D_GNU_SOURCE -DGETPIR -Wall -o getpir getpir.o checksum.o code_gen.o ./getpir Probing PIRQ table in memory. Found PCI IRQ routing table signature at 0xf7a00. Validating... checksum is ok. Creating irq_tables.c ... Done, you can move the file to the coreboot tree now. gcc -O2 -D_GNU_SOURCE -DGETPIR -Wall -c -o irq_tables.o irq_tables.c irq_tables.c:43: error: expected identifier or '(' before 'unsigned' make: *** [irq_tables.o] Error 1 Why does it give an error? is it due to me using gcc version 4.3.2 $ gcc --version gcc (Ubuntu 4.3.2-1ubuntu11) 4.3.2 Copyright (C) 2008 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. Lastly, keep up the good work. -- Regards, Shirish Agarwal My quotes in this email licensed under CC 3.0 http://creativecommons.org/licenses/by-nc/3.0/ http://flossexperiences.wordpress.com 065C 6D79 A68C E7EA 52B3 8D70 950D 53FB 729A 8B17

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Typo
by Bakhtiari, Azad CTR WHS/PENREN/EMC 27 Jan '09

27 Jan '09

Hi, Just an FYI... At http://www.coreboot.org/ASUS_P2B there is a typo on the line "ECC support WIP Not yet supported by the coreboot 440BX code, but it's on out TODO list." Should be our instead of out. It's no biggie but someone might appreciate it... Regards, Oz

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Re: [coreboot] [RFC] Add Alternative Log Buffer Support for printk Messages
by Carl-Daniel Hailfinger 27 Jan '09

27 Jan '09

Hi, [Sorry for the TOFU, I wanted to make sure people from the coreboot list can join in without having to dig through the archives. The coreboot list is moderated, but your mails will get through eventually.] This is a feature which would benefit coreboot (formerly known as LinuxBIOS) as well. coreboot v3 keeps such a log buffer in RAM and we (coreboot developers) are interested in sharing that buffer with the kernel. There might be some differences in the buffer format, though. I haven't yet read the patch completely, but from what I can see struct logbuff_t differs quite a bit between coreboot and U-Boot. There are some conceptually common struct members, but each of the projects has some info in there that's missing at the other project. It would be nice if we could work out some common data structure combining the best of both worlds. Regards, Carl-Daniel On 21.01.2009 18:39, Grant Erickson wrote: > This merges support for the previously DENX-only kernel feature of > specifying an alternative, "external" buffer for kernel printk > messages and their associated metadata. In addition, this ports > architecture support for this feature from arch/ppc to arch/powerpc. > > When this option is enabled, an architecture- or machine-specific log > buffer is used for all printk messages. This allows entities such as > boot loaders (e.g. U-Boot) to place printk-compatible messages into > this buffer and for the kernel to coalesce them with its normal > messages. > > Signed-off-by: Grant Erickson <gerickson(a)nuovations.com> > --- > > The code has historically been used and proven to work on the LWMON5 > platform under arch/ppc and is now used (by me) successfully on the > AMCC Haleakala and Kilauea platforms. > > As implemented for arch/powerpc, two suboptions for the alternative > log buffer are supported. The buffer may be contiguous with the > metadata and message data colocated or the metadata and message > storage may be in discontiguous regions of memory (e.g. a set of > scratch registers and an SRAM buffer). On Kilauea and Haleakala, I > have used the former; whereas LWMON5 has traditionally used the latter. > > The code here is, more or less, as-is from the DENX GIT tree. Comments > welcome. Some prior discussion from the linuxppc-dev mailing list is at > http://ozlabs.org/pipermail/linuxppc-dev/2008-November/065589.html. > > arch/powerpc/kernel/prom.c | 93 +++++++++++++++++++++++++++ > include/linux/logbuff.h | 56 ++++++++++++++++ > init/Kconfig | 25 +++++++ > init/main.c | 4 + > kernel/printk.c | 149 +++++++++++++++++++++++++++++++++++++++++++- > 5 files changed, 324 insertions(+), 3 deletions(-) > create mode 100644 include/linux/logbuff.h > > diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c > index 3a2dc7e..60282f1 100644 > --- a/arch/powerpc/kernel/prom.c > +++ b/arch/powerpc/kernel/prom.c > @@ -32,6 +32,7 @@ > #include <linux/debugfs.h> > #include <linux/irq.h> > #include <linux/lmb.h> > +#include <linux/logbuff.h> > > #include <asm/prom.h> > #include <asm/rtas.h> > @@ -61,6 +62,15 @@ > #define DBG(fmt...) > #endif > > +#ifdef CONFIG_LOGBUFFER > +#ifdef CONFIG_ALT_LB_LOCATION > +# if !defined(BOARD_ALT_LH_ADDR) || !defined(BOARD_ALT_LB_ADDR) > +# error "Please specify BOARD_ALT_LH_ADDR & BOARD_ALT_LB_ADDR." > +# endif > +#else /* !CONFIG_ALT_LB_LOCATION */ > +static phys_addr_t ext_logbuff; > +#endif /* CONFIG_ALT_LB_LOCATION */ > +#endif /* CONFIG_LOGBUFFER */ > > static int __initdata dt_root_addr_cells; > static int __initdata dt_root_size_cells; > @@ -1018,6 +1028,85 @@ static int __init early_init_dt_scan_memory(unsigned long node, > return 0; > } > > +#ifdef CONFIG_LOGBUFFER > +#ifdef CONFIG_ALT_LB_LOCATION > +/* Alternative external log buffer mapping: log metadata header & the > + * character buffer are separated and allocated not in RAM but in some > + * other memory-mapped I/O region (e.g. log head in unused registers, > + * and log buffer in OCM memory) > + */ > +int __init setup_ext_logbuff_mem(volatile logbuff_t **lhead, char **lbuf) > +{ > + void *h, *b; > + > + if (unlikely(!lhead) || unlikely(!lbuf)) > + return -EINVAL; > + > + /* map log head */ > + h = ioremap(BOARD_ALT_LH_ADDR, sizeof(logbuff_t)); > + if (unlikely(!h)) > + return -EFAULT; > + > + /* map log buffer */ > + b = ioremap(BOARD_ALT_LB_ADDR, LOGBUFF_LEN); > + if (unlikely(!b)) { > + iounmap(h); > + return -EFAULT; > + } > + > + *lhead = h; > + *lbuf = b; > + > + return 0; > +} > +#else /* !CONFIG_ALT_LB_LOCATION */ > +/* Usual external log-buffer mapping: log metadata header & the character > + * buffer are both contiguous in system RAM. > + */ > +int __init setup_ext_logbuff_mem(logbuff_t **lhead, char **lbuf) > +{ > + void *p; > + > + if (unlikely(!lhead) || unlikely(!lbuf)) > + return -EINVAL; > + > + if (unlikely(!ext_logbuff) || !lmb_is_reserved(ext_logbuff)) > + return -EFAULT; > + > + p = ioremap(ext_logbuff, LOGBUFF_RESERVE); > + > + if (unlikely(!p)) > + return -EFAULT; > + > + *lhead = (logbuff_t *)(p + LOGBUFF_OVERHEAD - > + sizeof(logbuff_t) + > + sizeof(((logbuff_t *)0)->buf)); > + *lbuf = (*lhead)->buf; > + > + return 0; > +} > + > +/* When the external log buffer configuration is used with the > + * non-alternate location, the log head metadata and character buffer > + * lie in the LOGBUFF_RESERVE bytes at the end of system RAM. Add this > + * block of memory to the reserved memory pool so that it is not > + * allocated for other purposes. > + */ > +static void __init reserve_ext_logbuff_mem(void) > +{ > + phys_addr_t top = lmb_end_of_DRAM(); > + phys_addr_t size = LOGBUFF_RESERVE; > + phys_addr_t base = top - size; > + > + if (top > base) { > + ext_logbuff = base; > + DBG("reserving: %x -> %x\n", base, size); > + lmb_reserve(base, size); > + } > +} > +#endif /* CONFIG_ALT_LB_LOCATION */ > +#endif /* CONFIG_LOGBUFFER */ > + > static void __init early_reserve_mem(void) > { > u64 base, size; > @@ -1033,6 +1122,10 @@ static void __init early_reserve_mem(void) > self_size = initial_boot_params->totalsize; > lmb_reserve(self_base, self_size); > > +#if defined(CONFIG_LOGBUFFER) && !defined(CONFIG_ALT_LB_LOCATION) > + reserve_ext_logbuff_mem(); > +#endif /* defined(CONFIG_LOGBUFFER) && !defined(CONFIG_ALT_LB_LOCATION) */ > + > #ifdef CONFIG_BLK_DEV_INITRD > /* then reserve the initrd, if any */ > if (initrd_start && (initrd_end > initrd_start)) > diff --git a/include/linux/logbuff.h b/include/linux/logbuff.h > new file mode 100644 > index 0000000..22a51c0 > --- /dev/null > +++ b/include/linux/logbuff.h > @@ -0,0 +1,56 @@ > +/* > + * (C) Copyright 2007 > + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > + * MA 02111-1307 USA > + */ > +#ifndef _LOGBUFF_H_ > +#define _LOGBUFF_H_ > + > +#ifdef CONFIG_LOGBUFFER > + > +#define LOGBUFF_MAGIC 0xc0de4ced > +#define LOGBUFF_LEN 16384 > +#define LOGBUFF_OVERHEAD 4096 > +#define LOGBUFF_RESERVE (LOGBUFF_LEN + LOGBUFF_OVERHEAD) > + > +/* The mapping used here has to be the same as in logbuff_init_ptrs () > + in u-boot/common/cmd_log.c */ > + > +typedef struct { > + unsigned long tag; > + unsigned long start; > + unsigned long con; /* next char to be sent to consoles */ > + unsigned long end; > + unsigned long chars; > + unsigned char buf[0]; > +} logbuff_t; > + > +#ifdef CONFIG_ALT_LB_LOCATION > +# define LOGBUFF_VOLATILE volatile > +#else > +# define LOGBUFF_VOLATILE > +#endif /* defined(CONFIG_ALT_LB_LOCATION) */ > + > +extern void setup_ext_logbuff(void); > +/* arch specific */ > +extern int setup_ext_logbuff_mem(LOGBUFF_VOLATILE logbuff_t **lhead, char **lbuf); > + > +#endif /* CONFIG_LOGBUFFER */ > +#endif /* _LOGBUFF_H_ */ > diff --git a/init/Kconfig b/init/Kconfig > index f763762..e1a1b59 100644 > --- a/init/Kconfig > +++ b/init/Kconfig > @@ -619,6 +619,31 @@ config PRINTK > very difficult to diagnose system problems, saying N here is > strongly discouraged. > > +config LOGBUFFER > + bool "External logbuffer" if PRINTK > + default n > + help > + This option enables support for an alternative, "external" > + printk log buffer. When enabled, an architecture- or machine- > + specific log buffer is used for all printk messages. This > + allows entities such as boot loaders to place printk-compatible > + messages into this buffer and for the kernel to coalesce them > + with its normal messages. > + > +config ALT_LB_LOCATION > + bool "Alternative logbuffer" if LOGBUFFER > + default n > + help > + When using an alternative, "external" printk log buffer, an > + architecture- or machine-specific log buffer with contiguous > + metadata and message storage is used. This option enables > + support for discontiguous metadata and message storage > + memory (e.g. a set of scratch registers and an SRAM > + buffer). By saying Y here, you must also ensure your > + architecture- or machine-code specify BOARD_ALT_LH_ADDR and > + BOARD_ALT_LB_ADDR, for the metadata and message memory, > + respectively. > + > config BUG > bool "BUG() support" if EMBEDDED > default y > diff --git a/init/main.c b/init/main.c > index 7e117a2..5687b98 100644 > --- a/init/main.c > +++ b/init/main.c > @@ -61,6 +61,7 @@ > #include <linux/kthread.h> > #include <linux/sched.h> > #include <linux/signal.h> > +#include <linux/logbuff.h> > #include <linux/idr.h> > #include <linux/ftrace.h> > > @@ -563,6 +564,9 @@ asmlinkage void __init start_kernel(void) > * Interrupts are still disabled. Do necessary setups, then > * enable them > */ > +#ifdef CONFIG_LOGBUFFER > + setup_ext_logbuff(); > +#endif > lock_kernel(); > tick_init(); > boot_cpu_init(); > diff --git a/kernel/printk.c b/kernel/printk.c > index f492f15..59884e2 100644 > --- a/kernel/printk.c > +++ b/kernel/printk.c > @@ -32,6 +32,7 @@ > #include <linux/security.h> > #include <linux/bootmem.h> > #include <linux/syscalls.h> > +#include <linux/logbuff.h> > > #include <asm/uaccess.h> > > @@ -101,9 +102,39 @@ static DEFINE_SPINLOCK(logbuf_lock); > * The indices into log_buf are not constrained to log_buf_len - they > * must be masked before subscripting > */ > +#ifdef CONFIG_LOGBUFFER > +/* Indexes to the local log buffer */ > +static unsigned long _log_start; > +static unsigned long _con_start; > +static unsigned long _log_end; > +static unsigned long _logged_chars; > +/* These will be switched to the external log buffer */ > +#ifndef CONFIG_ALT_LB_LOCATION > +/* usual logbuffer location */ > +static unsigned long *ext_log_start = &_log_start; > +static unsigned long *ext_con_start = &_con_start; > +static unsigned long *ext_log_end = &_log_end; > +static unsigned long *ext_logged_chars = &_logged_chars; > +#define log_start (*ext_log_start) > +#define con_start (*ext_con_start) > +#define log_end (*ext_log_end) > +#define logged_chars (*ext_logged_chars) > +#else /* defined(CONFIG_ALT_LB_LOCATION) */ > +/* alternative logbuffer location */ > +static volatile unsigned long *ext_log_start = &_log_start; > +static volatile unsigned long *ext_con_start = &_con_start; > +static volatile unsigned long *ext_log_end = &_log_end; > +static volatile unsigned long *ext_logged_chars = &_logged_chars; > +#define log_start (*((volatile u32 *)ext_log_start)) > +#define con_start (*((volatile u32 *)ext_con_start)) > +#define log_end (*((volatile u32 *)ext_log_end)) > +#define logged_chars (*((volatile u32 *)ext_logged_chars)) > +#endif /* !defined(CONFIG_ALT_LB_LOCATION) */ > +#else /* !defined(CONFIG_LOGBUFFER) */ > static unsigned log_start; /* Index into log_buf: next char to be read by syslog() */ > static unsigned con_start; /* Index into log_buf: next char to be sent to consoles */ > static unsigned log_end; /* Index into log_buf: most-recently-written-char + 1 */ > +#endif /* CONFIG_LOGBUFFER */ > > /* > * Array of consoles built from command line options (console=) > @@ -134,10 +165,121 @@ static int console_may_schedule; > static char __log_buf[__LOG_BUF_LEN]; > static char *log_buf = __log_buf; > static int log_buf_len = __LOG_BUF_LEN; > +#ifndef CONFIG_LOGBUFFER > static unsigned logged_chars; /* Number of chars produced since last read+clear operation */ > +#endif /* !defined(CONFIG_LOGBUFFER) */ > +#ifdef CONFIG_LOGBUFFER > +/* Sanity check the external log buffer metadata. When an the external > + * log buffer is enabled, the log metadata is effectively non-volatile > + * in that the values are preserved from reboot to reboot (until/unless > + * the system loses power). > + */ > +static void __init logbuff_check_metadata(LOGBUFF_VOLATILE logbuff_t *log) > +{ > + unsigned long chars; > + > + /* Sanity check the producer and consumer indices. */ > + > + if (log->end - log->start > LOGBUFF_LEN) > + log->start = log->end - LOGBUFF_LEN; > + > + if (log->end - log->con > LOGBUFF_LEN) > + log->con = log->end - LOGBUFF_LEN; > + > + /* Occasionally, particularly following a reboot, the start > + * consumer index is not properly caught up to the console > + * consumer index. If this is the case, catch it up so that > + * the log buffer doesn't start with, for example, > + * "<0>Restarting system.\n" followed by the 'real' start of > + * the log. > + */ > + > + if (log->con > log->start) > + log->start = log->con; > + > + /* Ensure that the number of characters logged reflects the > + * characters actually logged based on the producer and > + * consumer indices rather than all characters cumulatively > + * logged across all reboots since a power-loss event. > + */ > + > + chars = log->end - log->start; > + > + if (log->chars > chars) > + log->chars = chars; > +} > + > +/* Coalesce the current log bounded buffer and the external log > + * bounded buffer by appending the former to the latter. Precedence is > + * given to the external log buffer when there is more data to be > + * appended than space exists, so the current log buffer is truncated > + * instead of overwritting the external buffer. > + */ > +static void __init logbuff_coalesce_buffers(LOGBUFF_VOLATILE logbuff_t *log) > +{ > + unsigned long dspace, ssize, len; > + > + dspace = LOGBUFF_LEN - (log->end - log->start); > + ssize = log_end - log_start; > + len = min(dspace, ssize); > + > + while (len-- > 0) { > + log->buf[log->end++ & (LOGBUFF_LEN-1)] = LOG_BUF(log_start++); > + log->chars++; > + } > +} > > +void __init setup_ext_logbuff(void) > +{ > + LOGBUFF_VOLATILE logbuff_t *log; > + char *ext_log_buf = NULL; > + unsigned long flags; > + > + if (setup_ext_logbuff_mem(&log, &ext_log_buf) < 0) { > + printk(KERN_WARNING > + "Failed to setup external logbuffer - ignoring it\n"); > + return; > + } > + > + /* When no properly setup buffer is found, reset pointers */ > + if (log->tag != LOGBUFF_MAGIC) { > + printk(KERN_WARNING > + "Unexpected external log buffer magic number. " > + "Got %08lx, expected %08x. Resetting pointers and using " > + "the buffer anyway.\n", > + log->tag, LOGBUFF_MAGIC); > + log->tag = LOGBUFF_MAGIC; > + log->start = log->end = log->con = log->chars = 0; > + } > + > + spin_lock_irqsave(&logbuf_lock, flags); > + > + logbuff_check_metadata(log); > + logbuff_coalesce_buffers(log); > + > + /* Switch to the external log buffer */ > + ext_log_start = &log->start; > + ext_con_start = &log->con; > + ext_log_end = &log->end; > + ext_logged_chars = &log->chars; > + > + log_buf = ext_log_buf; > + log_buf_len = LOGBUFF_LEN; > + > + spin_unlock_irqrestore(&logbuf_lock, flags); > + > + printk(KERN_NOTICE "log_buf=%p\n", log_buf); > +} > +#endif /* CONFIG_LOGBUFFER */ > static int __init log_buf_len_setup(char *str) > { > +#ifdef CONFIG_LOGBUFFER > + /* Log buffer size is LOGBUFF_LEN bytes */ > + printk(KERN_NOTICE > + "External log buffer configured; " > + "ignoring log_buf_len param.\n"); > + return 1; > +#else > unsigned size = memparse(str, &str); > unsigned long flags; > > @@ -173,6 +315,7 @@ static int __init log_buf_len_setup(char *str) > } > out: > return 1; > +#endif /* CONFIG_LOGBUFFER */ > } > > __setup("log_buf_len=", log_buf_len_setup); > @@ -230,7 +373,7 @@ static void boot_delay_msec(void) > static inline void boot_delay_msec(void) > { > } > -#endif > +#endif /* CONFIG_BOOT_PRINTK_DELAY */ > > /* > * Commands to do_syslog: > @@ -740,7 +883,7 @@ out_restore_irqs: > EXPORT_SYMBOL(printk); > EXPORT_SYMBOL(vprintk); > > -#else > +#else /* !CONFIG_PRINTK */ > > asmlinkage long sys_syslog(int type, char __user *buf, int len) > { > @@ -751,7 +894,7 @@ static void call_console_drivers(unsigned start, unsigned end) > { > } > > -#endif > +#endif /* CONFIG_PRINTK */ > > static int __add_preferred_console(char *name, int idx, char *options, > char *brl_options) > -- http://www.hailfinger.org/

1 0

SB600 HDA can't find codec fix
by Dan Lykowski 26 Jan '09

26 Jan '09

These changes allow the SB600 HDA to detect the codec correctly. I haven't had time to test the sound output, but Linux now detects it correctly. I don't see why it wouldn't work. Feel free to give it a whirl and let me know if more work is needed. Signed-off-by: Dan Lykowski<lykowdk(a)gmail.com>

2 1

Intel i5000 Port
by Sven Schnelle 26 Jan '09

26 Jan '09

Hi List, i've started a port of coreboot to the Intel i5000 Chipset (http://www.intel.com/products/server/chipsets/5000p/5000p-overview.htm) last week. The board i'm developing is a Supermicro X7DB8, with one QuadCore E5335 Xeon. There's not much working right now, with exception of the SuperIO chip, and basic CPU CAR setup (i'm using the Core2Duo code at the moment). Currently work is going on at the FBDIMM setup and Memory Controller initialization. I'm attaching the current diff, but you should consider that as non-working code. I wouldn't send it to the list, if not Carl Daniel would have requested me to do so :) Index: southbridge/intel/i63xx/i63xx.c =================================================================== --- southbridge/intel/i63xx/i63xx.c (revision 0) +++ southbridge/intel/i63xx/i63xx.c (revision 0) @@ -0,0 +1 @@ +#include<irq_tables.h> Index: southbridge/intel/i63xx/Makefile =================================================================== --- southbridge/intel/i63xx/Makefile (revision 0) +++ southbridge/intel/i63xx/Makefile (revision 0) @@ -0,0 +1,28 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Sven Schnelle <svens(a)stackframe.org> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_63XX),y) + +STAGE2_CHIPSET_SRC += $(src)/southbridge/intel/i63xx/common.c + +STAGE0_CHIPSET_SRC += + + +endif Index: Kconfig =================================================================== --- Kconfig (revision 1123) +++ Kconfig (working copy) @@ -117,6 +117,8 @@ boolean config NORTHBRIDGE_INTEL_I945 boolean +config NORTHBRIDGE_INTEL_I5000 + boolean # Southbridges: config SOUTHBRIDGE_AMD_CS5536 @@ -148,6 +150,8 @@ boolean config SOUTHBRIDGE_INTEL_I82801GX boolean +config SOUTHBRIDGE_INTEL_I5000 + boolean # Super I/Os: config SUPERIO_WINBOND_W83627HF Index: mainboard/Kconfig =================================================================== --- mainboard/Kconfig (revision 1123) +++ mainboard/Kconfig (working copy) @@ -43,6 +43,11 @@ help Select this option for various systems from AMP. +config VENDOR_SUPERMICRO + bool "Supermicro" + help + Select this option for various systems from Supermicro. + config VENDOR_ARTECGROUP bool "Artec Group" help @@ -90,6 +95,7 @@ source "mainboard/kontron/Kconfig" source "mainboard/pcengines/Kconfig" source "mainboard/via/Kconfig" +source "mainboard/supermicro/Kconfig" choice prompt "ROM chip size" Index: mainboard/supermicro/Kconfig =================================================================== --- mainboard/supermicro/Kconfig (revision 0) +++ mainboard/supermicro/Kconfig (revision 0) @@ -0,0 +1,40 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Sven Schnelle <svens(a)stackframe.org> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +choice + prompt "Mainboard model" + depends on VENDOR_SUPERMICRO + +config BOARD_SUPERMICRO_X7DB8 + bool "X7DB8" + select ARCH_X86 + select CPU_INTEL_CORE2 + select NORTHBRIDGE_INTEL_I5000 + select SOUTHBRIDGE_INTEL_I5000 + select SUPERIO_WINBOND_W83627HF + help + Supermicro X7DV8 Dual Xeon (Socket 771) Board + +endchoice + +config MAINBOARD_DIR + string + default supermicro/x7db8 + depends BOARD_SUPERMICRO_X7DB8 Index: mainboard/supermicro/x7db8/initram.c =================================================================== --- mainboard/supermicro/x7db8/initram.c (revision 0) +++ mainboard/supermicro/x7db8/initram.c (revision 0) @@ -0,0 +1,335 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define _MAINOBJECT + +#include <types.h> +#include <lib.h> +#include <console.h> +#include <device/device.h> +#include <device/pci.h> +#include <string.h> +#include <msr.h> +#include <io.h> +#include <superio/winbond/w83627hf/w83627hf.h> +#include <i5000_mch.h> + +#define SERIAL_DEV W83627HF_SP1 +#define SERIAL_IOBASE 0x3f8 + +static u8 spd_banks[] = { 4, 8, 16, 32 }; +static u8 spd_cas[8] = { 9, 10, 11, 0, 0, 0, 0, 0 }; +static u8 spd_ras[8] = { 12, 13, 14, 15, 16, 17, 18, 19 }; +static u8 spd_width[8] = { 4, 8, 16, 32, 0, 0, 0, 0 }; +static u8 spd_ranks[8] = { 0, 1, 2, 0, 0, 0, 0, 0 }; + +static u8 const gpiodata[] = { + 0xcf, 0x79, 0x0c, 0xff, 0xff, 0xff, 0x00, 0xe7, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xbf, 0x65, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x8a, 0x71, 0x00, 0x00, + 0x06, 0x01, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, + 0x01, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, +}; + +static int crc16 (u8 *ptr, int count) +{ + int crc, i; + crc = 0; + while (--count >= 0) { + crc = crc ^ (int)*ptr++ << 8; + for (i = 0; i < 8; ++i) + if (crc & 0x8000) + crc = crc << 1 ^ 0x1021; + else + crc = crc << 1; + } + return (crc & 0xFFFF); +} + +static int spd_read_byte(const int branch, const int channel, + const int dimm, const u8 addr, u8 *val) +{ + u16 status; + const int dev = branch ? 22 : 21; + + pci_conf1_write_config32(PCI_BDF(0, dev, 0), + channel ? I5000_MCH_SPDCMD1 : I5000_MCH_SPDCMD0, + 0xa8000000 | (dimm & 0x03) << 24 | addr << 16); + + for(;;) { + status = pci_conf1_read_config16( + PCI_BDF(0, dev, 0), + channel ? I5000_MCH_SPD1 : I5000_MCH_SPD0); + + if (status & I5000_MCH_SPD_SBE) + break; + + if (status & I5000_MCH_SPD_BUSY) + continue; + + if (status & I5000_MCH_SPD_RDO) { + *val = status & 0xff; + return 0; + } + } + return -1; +} + +static void i5000_reset_fbdimm(void) +{ + /* Branch1 reset follows Branch0 */ + pci_conf1_write_config8(PCI_BDF(0, 22, 0), I5000_MCH_FBDRST0, 4); + /* Assert SOFTCORERESET# and CORERESET# */ + pci_conf1_write_config8(PCI_BDF(0, 21, 0), I5000_MCH_FBDRST0, 0); + /* Deassert SOFTCORERESET */ + pci_conf1_write_config8(PCI_BDF(0, 21, 0), I5000_MCH_FBDRST0, 1); + /* Assert SOFTCORERESET# and CORERESET# */ + pci_conf1_write_config8(PCI_BDF(0, 21, 0), I5000_MCH_FBDRST0, 0); + /* Deassert both lines */ + pci_conf1_write_config8(PCI_BDF(0, 21, 0), I5000_MCH_FBDRST0, 3); +} + +static void i5000_setup_rcba(void) +{ + u32 gcs; + + pci_conf1_write_config32(PCI_BDF(0, 31, 0), 0xf0, + I5000_RCBA_BASE | I5000_RCBA_ENABLE); + + gcs = *(u32 *)(I5000_RCBA(I5000_GCS)); + gcs |= 1; /* Prevent BUC.TS from beeing changed */ + gcs &= 0xfb; /* Forward BIOS Cycles to LPC */ + *(u32 *)(I5000_RCBA(I5000_GCS)) = gcs; +} + +static void i5000_setup_io(void) +{ + u16 tmp; + + pci_conf1_write_config32(PCI_BDF(0, 30, 0), I5000_MCH_IOBASE_LIMIT, 0x10); + + /* Enable PCI I/O */ + tmp = pci_conf1_read_config16(PCI_BDF(0, 30, 0), 0x04); + tmp |= 0x01; + pci_conf1_write_config32(PCI_BDF(0, 30, 0), 0x04, tmp | 0x01); +} + +static int i5000_init_amb(int branch, int channel, int dimm, int maxwait, int state) +{ + u32 pci_dev = PCI_BDF(0, branch ? 22 : 21, 0); + u32 fbdists, fbicmd; + + if (channel) { + fbdists = I5000_MCH_FBDISTS1; + fbicmd = I5000_MCH_FBDICMD1; + } else { + fbdists = I5000_MCH_FBDISTS0; + fbicmd = I5000_MCH_FBDICMD0; + } + +/* printk(BIOS_DEBUG, "%s: %d/%d/%d: %02x\n", __func__, + branch, channel, dimm, state); +*/ + pci_conf1_write_config8(pci_dev, fbicmd, state); + + + while(maxwait--) + if(pci_conf1_read_config16(pci_dev, fbdists) == 0x1fff) + return 0; + + printk(BIOS_ERR, "calibration failed (branch %d, channel %d, dimm %d, res 0x%04x)\n", + branch, channel, dimm, pci_conf1_read_config16(pci_dev, fbdists)); + return -1; +} + +static void i5000_fbdimm_nextstate(const int branch, const int channel, + const int dimm, const int state) +{ + pci_conf1_write_config8(PCI_BDF(0, branch ? 22 : 21, 0), + channel ? I5000_MCH_FBDHPC0 : I5000_MCH_FBDHPC0, state); +} + +static int i5000_fbdimm_init(const int branch, const int channel, const int dimm) +{ + + i5000_fbdimm_nextstate(branch, channel, dimm, 0x00); + i5000_fbdimm_nextstate(branch, channel, dimm, 0x10); + + if (i5000_init_amb(branch, channel, dimm, 0xfffff, I5000_MCH_FBDIMM_TS0) == -1) + return -1; + + if (i5000_init_amb(branch, channel, dimm, 0xfffff, I5000_MCH_FBDIMM_TS1) == -1) + return -1; + + if (i5000_init_amb(branch, channel, dimm, 0xfffff, I5000_MCH_FBDIMM_TS2) == -1) + return -1; + + if (i5000_init_amb(branch, channel, dimm, 0xfffff, I5000_MCH_FBDIMM_TS3) == -1) + return -1; + + i5000_fbdimm_nextstate(branch, channel, dimm, 0x20); + i5000_fbdimm_nextstate(branch, channel, dimm, 0x30); + + return 0; +} + +int main(void) +{ + /* [BRANCH][CHANNEL][DIMM] */ + u16 dimmsizes[2][2][4]; + int branch, channel, dimm, addr, banks, cas, ras, ranks, width; + u8 spddata[0x80]; + u16 type, vendor, device; + u32 mtr; + u16 totalmem = 0; + volatile int i; + + post_code(POST_START_OF_MAIN); + printk(BIOS_DEBUG, "Initializing memory\n"); + + if (pci_conf1_read_config16(PCI_BDF(0, 0, 0), 0) != 0x8086) { + printk(BIOS_ERR, "Unknown chipset (vendor unknown)\n"); + return -1; + } + + type = pci_conf1_read_config16(PCI_BDF(0, 0, 0), 2); + + switch(type) { + case I5000_MCH_ID_5000P: + printk(BIOS_INFO, "Intel 5000P MCH detected\n"); + break; + case I5000_MCH_ID_5000Z: + printk(BIOS_INFO, "Intel 5000Z MCH detected\n"); + break; + case I5000_MCH_ID_5000V: + printk(BIOS_INFO, "Intel 5000V MCH detected\n"); + break; + case I5000_MCH_ID_5000X: + printk(BIOS_INFO, "Intel 5000X MCH detected\n"); + break; + default: + printk(BIOS_ERR, "Unknown chipset!\n"); + return 1; + } + + i5000_setup_rcba(); + i5000_setup_io(); + + /* Set GPIOBAE to 1180 */ + pci_conf1_write_config16(PCI_BDF(0, 31, 0), 0x48, 0x1180); + /* Enable GPIO */ + pci_conf1_write_config16(PCI_BDF(0, 31, 0), 0x4c, + pci_conf1_read_config16(PCI_BDF(0, 31, 0), 0x4c) | 0x10); + + /* Write (yet unknown) GPIO data */ + for(i = 0; i < 64; i++) + outb(gpiodata[i], 0x1180+i); + + for(i = 0; i < 0x20; i++) { + vendor = pci_conf1_read_config16(PCI_BDF(0, i, 0), 0x00); + device = pci_conf1_read_config16(PCI_BDF(0, i, 0), 0x02); + + if (vendor == 0xffff || device == 0xffff) + continue; + + printk(BIOS_INFO, "%02d: %04x:%04x CMD=0x%04x STS=0x%04x\n", i, vendor, device, + pci_conf1_read_config16(PCI_BDF(0, i, 0), 0x04), + pci_conf1_read_config16(PCI_BDF(0, i, 0), 0x06)); + } + + printk(BIOS_INFO, "detecting Memory:\n"); + + i5000_reset_fbdimm(); + + for(branch = 0; branch < 2; branch++) { + for(channel = 0; channel < 2; channel++) { + for(dimm = 0; dimm < 4; dimm++) { + for(addr = 0; addr < 0x80; addr++) + if (spd_read_byte(branch, channel, dimm, addr, spddata + addr) == -1) + break; + + if (addr != 0x80) + break; + + if (crc16(spddata, spddata[0] & 0x80 ? 117 : 126) != (spddata[127] << 8 | spddata[126])) { + printk(BIOS_INFO, "*** SPD has invalid checksum ***"); + continue; + } + + banks = spd_banks[spddata[4] & 0x03]; + ras = spd_ras[(spddata[4] >> 5) & 0x07]; + cas = spd_cas[(spddata[4] >> 2) & 0x07]; + width = spd_width[spddata[7] & 0x07]; + ranks = spd_ranks[(spddata[7] >> 3) & 0x07]; + + printk(BIOS_DEBUG, "Branch %d, Channel %d, DIMM %d: %d MB (RAS:%d CAS:%d BANKS:%d WIDTH:%d RANKS:%d)", + branch, channel, dimm, + (1 << (ras + cas + banks + ranks) >> 20), ras, cas, banks, width, ranks); + + totalmem += (1 << (ras + cas + banks + ranks) >> 20); + + mtr = ranks == 2 ? (1 << 4) : 0; + mtr |= banks == 8 ? (1 << 5) : 0; + mtr |= width == 8 ? (1 << 6) : 0; + mtr |= 0x100; /* We assume the DIMMs are compatible for now */ + + switch(ras) { + case 13: + break; + case 14: + mtr |= (1 << 2); + break; + case 15: + mtr |= (1 << 3); + break; + default: + printk(BIOS_ERR, "RAS %d not supported\n", ras); + break; + } + + switch(cas) { + case 10: + break; + case 11: + mtr |= 1; + break; + case 12: + mtr |= (1 << 1); + break; + default: + printk(BIOS_ERR, "CAS %d not supported\n", ras); + break; + } + + pci_conf1_write_config16(PCI_BDF(0, branch ? 22 : 21, 0), 0x80 | (dimm << 2), mtr); +// printk(BIOS_DEBUG, "Vendor/Dev: 0x%08x ", *(u32 *)0xfe000000); + + if (i5000_fbdimm_init(branch, channel, dimm) == -1) { + } + printk(BIOS_INFO, "\n"); + } + } + } + printk(BIOS_INFO, "Total Memory detected: %d MB\n", totalmem); + return 0; +} Index: mainboard/supermicro/x7db8/stage1.c =================================================================== --- mainboard/supermicro/x7db8/stage1.c (revision 0) +++ mainboard/supermicro/x7db8/stage1.c (revision 0) @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <lib.h> +#include <console.h> +#include <device/device.h> +#include <device/pci.h> +#include <string.h> +#include <msr.h> +#include <io.h> +#include <superio/winbond/w83627hf/w83627hf.h> +#include <i63xx.h> + +#define SERIAL_DEV W83627HF_SP1 +#define SERIAL_IOBASE 0x3f8 + +void hardware_stage1(void) +{ + post_code(POST_STAGE1_MAIN); + /* Enable LPC decoding for: Super I/O and COM1 */ + pci_conf1_write_config16(PCI_BDF(0, 0x1f, 0), I63XX_LPC_EN, + I63XX_LPC_EN_CNF1 | I63XX_LPC_EN_COMA); + void w83627hf_enable_serial(u8 dev, u8 serial, u16 iobase); + w83627hf_enable_serial(0x2e, SERIAL_DEV, SERIAL_IOBASE); +} + +void mainboard_pre_payload(void) +{ +} Index: mainboard/supermicro/x7db8/i63xx.h =================================================================== --- mainboard/supermicro/x7db8/i63xx.h (revision 0) +++ mainboard/supermicro/x7db8/i63xx.h (revision 0) @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef INTEL_63XX_H +#define INTEL_63XX_H + +#define I63XX_LPC_EN 0x82 + +#define I63XX_LPC_EN_CNF1 0x1000 +#define I63XX_LPC_EN_MC 0x0800 +#define I63XX_LPC_EN_KBC 0x0400 +#define I63XX_LPC_EN_GAMEH 0x0200 +#define I63XX_LPC_EN_GAMEL 0x0100 +#define I63XX_LPC_EN_FDD 0x0008 +#define I63XX_LPC_EN_LPT 0x0004 +#define I63XX_LPC_EN_COMB 0x0002 +#define I63XX_LPC_EN_COMA 0x0001 + +#define I63XX_LPC_GPIOBASE 0x48 + +#endif Index: mainboard/supermicro/x7db8/dts =================================================================== --- mainboard/supermicro/x7db8/dts (revision 0) +++ mainboard/supermicro/x7db8/dts (revision 0) @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/{ + mainboard_vendor = "Supermicro"; + mainboard_name = "X7DB8"; + cpus { }; + + domain@0 { + /config/("northbridge/intel/i5000/domain"); + pci@1f,0 { + /config/("southbridge/intel/i5000/i5000_lpc.dts"); + ioport@2e { + /config/("superio/winbond/w83627hf/dts"); + com1enable = "1"; + com1address = "0x3f8"; + com1irq = "4"; + }; + }; + }; +}; + Index: mainboard/supermicro/x7db8/i5000_mch.h =================================================================== --- mainboard/supermicro/x7db8/i5000_mch.h (revision 0) +++ mainboard/supermicro/x7db8/i5000_mch.h (revision 0) @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef INTEL_5000_MCH_H +#define INTEL_5000_MCH_H + +#define I5000_MCH_FBDICMD0 0x46 +#define I5000_MCH_FBDICMD1 0x47 +#define I5000_MCH_FBDST 0x4b +#define I5000_MCH_FBDHPC0 0x4f +#define I5000_MCH_FBDRST0 0x53 +#define I5000_MCH_FBDISTS0 0x58 +#define I5000_MCH_FBDISTS1 0x5a +#define I5000_MCH_AMBPRESENT 0x64 +#define I5000_MCH_MTR00 0x80 +#define I5000_MCH_MTR01 0x84 +#define I5000_MCH_MTR02 0x88 +#define I5000_MCH_MTR03 0x8c + +#define I5000_MCH_MC 0x40 + + +#define I5000_MCH_ID_5000P 0x25c8 +#define I5000_MCH_ID_5000Z 0x25d0 +#define I5000_MCH_ID_5000V 0x25d4 +#define I5000_MCH_ID_5000X 0x25d8 + +#define I5000_MCH_SPD0 0x74 +#define I5000_MCH_SPD1 0x76 + + +#define I5000_MCH_SPD_RDO 0x8000 +#define I5000_MCH_SPD_WOD 0x4000 +#define I5000_MCH_SPD_SBE 0x2000 +#define I5000_MCH_SPD_BUSY 0x1000 + +#define I5000_MCH_SPDCMD0 0x78 +#define I5000_MCH_SPDCMD1 0x7c + +#define I5000_MCH_MCA 0x58 +#define I5000_MCH_MCA_SCHDIMM 0x4000 + +#define I5000_MCH_DDRFREQ 0x56 +#define I5000_MCH_DDRFREQ_11 0x00 +#define I5000_MCH_DDRFREQ_45 0x02 +#define I5000_MCH_DDRFREQ_54 0x03 + +#define I5000_MCH_AMBSELECT 0x54 +#define I5000_MCH_MAXCH 0x56 +#define I5000_MCH_MAXDIMMPERCH 0x57 + +#define I5000_RCBA_BASE 0xfed1c000 +#define I5000_RCBA_ENABLE 0x00000001 + +#define I5000_RCBA(x) (I5000_RCBA_BASE | (x)) +#define I5000_GCS 0x3410 + +#define I5000_MCH_IOBASE_LIMIT 0x1c + +#define I5000_MCH_FBDIMM_TS0 0x00 +#define I5000_MCH_FBDIMM_TS1 0x10 +#define I5000_MCH_FBDIMM_TS2 0x20 +#define I5000_MCH_FBDIMM_TS3 0x30 +#define I5000_MCH_FBDIMM_TS4 0x00 +#endif Index: mainboard/supermicro/x7db8/irq_tables.h =================================================================== --- mainboard/supermicro/x7db8/irq_tables.h (revision 0) +++ mainboard/supermicro/x7db8/irq_tables.h (revision 0) @@ -0,0 +1,74 @@ +/* This file was generated by getpir.c, do not modify! + * (but if you do, please run checkpir on it to verify) + * + * Contains the IRQ Routing Table dumped directly from your + * memory, which BIOS sets up. + * + * Documentation at: http://www.microsoft.com/whdc/archive/pciirq.mspx + */ + +#ifdef GETPIR +#include "pirq_routing.h" +#else +#include <arch/x86/pirq_routing.h> +#endif + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32+16*31, /* There can be total 31 devices on the bus */ + 0x00, /* Where the interrupt router lies (bus) */ + (0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x122e, /* Device */ + 0, /* Miniport */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0xc0, /* u8 checksum. This has to be set to some + value that would give 0 after the sum of all + bytes for this structure (including checksum) */ + { + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00,(0x00<<3)|0x0, {{0x60, 0x1ef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, + {0x00,(0x02<<3)|0x0, {{0x60, 0x1ef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, + {0x01,(0x00<<3)|0x0, {{0x60, 0x1ef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, + {0x02,(0x00<<3)|0x0, {{0x60, 0x1ef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, + {0x03,(0x00<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, + {0x04,(0x01<<3)|0x0, {{0x60, 0x1ef8}, {0x61, 0x1ef8}, {0x60, 0x1ef8}, {0x61, 0x1ef8}}, 0x1, 0x0}, + {0x04,(0x02<<3)|0x0, {{0x60, 0x1ef8}, {0x61, 0x1ef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x7, 0x0}, + {0x03,(0x00<<3)|0x2, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, + {0x05,(0x01<<3)|0x0, {{0x60, 0x1ef8}, {0x61, 0x1ef8}, {0x62, 0x1ef8}, {0x63, 0x1ef8}}, 0x2, 0x0}, + {0x02,(0x02<<3)|0x0, {{0x62, 0x1ef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, + {0x06,(0x00<<3)|0x0, {{0x62, 0x1ef8}, {0x63, 0x1ef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x8, 0x0}, + {0x06,(0x00<<3)|0x1, {{0x00, 0xdef8}, {0x63, 0x1ef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x8, 0x0}, + {0x01,(0x00<<3)|0x3, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, + {0x07,(0x01<<3)|0x0, {{0x60, 0x1ef8}, {0x61, 0x1ef8}, {0x62, 0x1ef8}, {0x63, 0x1ef8}}, 0x3, 0x0}, + {0x00,(0x04<<3)|0x0, {{0x60, 0x1ef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, + {0x08,(0x00<<3)|0x0, {{0x60, 0x1ef8}, {0x61, 0x1ef8}, {0x62, 0x1ef8}, {0x63, 0x1ef8}}, 0x6, 0x0}, + {0x00,(0x06<<3)|0x0, {{0x60, 0x1ef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, + {0x09,(0x00<<3)|0x0, {{0x62, 0x1ef8}, {0x63, 0x1ef8}, {0x60, 0x1ef8}, {0x61, 0x1ef8}}, 0x5, 0x0}, + {0x00,(0x08<<3)|0x0, {{0x60, 0x1ef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, + {0x00,(0x10<<3)|0x0, {{0x60, 0x1ef8}, {0x61, 0x1ef8}, {0x62, 0x1ef8}, {0x63, 0x1ef8}}, 0x0, 0x0}, + {0x00,(0x11<<3)|0x0, {{0x60, 0x1ef8}, {0x61, 0x1ef8}, {0x62, 0x1ef8}, {0x63, 0x1ef8}}, 0x0, 0x0}, + {0x00,(0x13<<3)|0x0, {{0x60, 0x1ef8}, {0x61, 0x1ef8}, {0x62, 0x1ef8}, {0x63, 0x1ef8}}, 0x0, 0x0}, + {0x00,(0x15<<3)|0x0, {{0x60, 0x1ef8}, {0x61, 0x1ef8}, {0x62, 0x1ef8}, {0x63, 0x1ef8}}, 0x0, 0x0}, + {0x00,(0x16<<3)|0x0, {{0x60, 0x1ef8}, {0x61, 0x1ef8}, {0x62, 0x1ef8}, {0x63, 0x1ef8}}, 0x0, 0x0}, + {0x00,(0x1c<<3)|0x0, {{0x61, 0x1ef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, + {0x0a,(0x00<<3)|0x0, {{0x60, 0x1ef8}, {0x61, 0x1ef8}, {0x62, 0x1ef8}, {0x63, 0x1ef8}}, 0x4, 0x0}, + {0x00,(0x1d<<3)|0x0, {{0x61, 0x1ef8}, {0x63, 0x1ef8}, {0x62, 0x1ef8}, {0x60, 0x1ef8}}, 0x0, 0x0}, + {0x00,(0x1e<<3)|0x0, {{0x61, 0x1ef8}, {0x68, 0x1ef8}, {0x62, 0x1ef8}, {0x63, 0x1ef8}}, 0x0, 0x0}, + {0x0b,(0x02<<3)|0x0, {{0x60, 0x1ef8}, {0x61, 0x1ef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x9, 0x0}, + {0x0b,(0x01<<3)|0x0, {{0x62, 0x1ef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, + {0x00,(0x1f<<3)|0x0, {{0x62, 0x1ef8}, {0x63, 0x1ef8}, {0x62, 0x1ef8}, {0x60, 0x1ef8}}, 0x0, 0x0}, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} + +unsigned long stage0_copy_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} Index: mainboard/supermicro/x7db8/Makefile =================================================================== --- mainboard/supermicro/x7db8/Makefile (revision 0) +++ mainboard/supermicro/x7db8/Makefile (revision 0) @@ -0,0 +1,30 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Sven Schnelle <svens(a)stackframe.org> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +STAGE0_MAINBOARD_SRC := $(src)/mainboard/$(MAINBOARDDIR)/stage1.c + +INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c + +STAGE2_MAINBOARD_SRC = + +$(obj)/coreboot.vpd: + $(Q)printf " BUILD DUMMY VPD\n" + $(Q)dd if=/dev/zero of=$(obj)/coreboot.vpd bs=256 count=1 $(SILENT) + Index: mainboard/supermicro/x7db8/cmos.layout =================================================================== --- mainboard/supermicro/x7db8/cmos.layout (revision 0) +++ mainboard/supermicro/x7db8/cmos.layout (revision 0) @@ -0,0 +1,74 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +1008 16 h 0 check_sum + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM + +checksums + +checksum 392 1007 1008 + + Index: northbridge/intel/i5000/i5000.h =================================================================== --- northbridge/intel/i5000/i5000.h (revision 0) +++ northbridge/intel/i5000/i5000.h (revision 0) @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef NORTHBRIDGE_INTEL_I5000_H +#define NORTHBRIDGE_INTEL_I5000_H + +#include <device/device.h> + +#endif Index: northbridge/intel/i5000/northbridge =================================================================== --- northbridge/intel/i5000/northbridge (revision 0) +++ northbridge/intel/i5000/northbridge (revision 0) @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +{ + device_operations = "i5000_northbridge"; +}; Index: northbridge/intel/i5000/domain =================================================================== --- northbridge/intel/i5000/domain (revision 0) +++ northbridge/intel/i5000/domain (revision 0) @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +{ + device_operations = "i5000_domain"; +}; Index: northbridge/intel/i5000/Makefile =================================================================== --- northbridge/intel/i5000/Makefile (revision 0) +++ northbridge/intel/i5000/Makefile (revision 0) @@ -0,0 +1,25 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Sven Schnelle <svens(a)stackframe.org> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I5000),y) + +STAGE2_CHIPSET_SRC += $(src)/northbridge/intel/i5000/i5000.c + +endif Index: northbridge/intel/i5000/i5000.c =================================================================== --- northbridge/intel/i5000/i5000.c (revision 0) +++ northbridge/intel/i5000/i5000.c (revision 0) @@ -0,0 +1,85 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2009 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <console.h> +#include <device/device.h> +#include <device/pci.h> +#include <string.h> +#include <io.h> +#include "i5000.h" +#include <statictree.h> + +static int inb_cmos(int port) +{ +} + +static void no_op(struct device *dev) +{ +} + +static void i5000_read_resources(struct device *dev) +{ +} + +static void i5000_ram_resources(struct device *dev) +{ +} + +static void i5000_set_resources(struct device *dev) +{ +} + +static void i5000_domain_read_resources(struct device *dev) +{ +} + +static void i5000_domain_set_resources(struct device *dev) +{ +} + +/* Here are the operations for when the northbridge is running a PCI domain. */ +/* See mainboard/emulation/qemu-x86 for an example of how these are used. */ +struct device_operations i5000_domain = { + .id = {.type = DEVICE_ID_PCI_DOMAIN, + {.pci_domain = {.vendor = 0x8086,.device = 0x7190}}}, + .constructor = default_device_constructor, + .phase3_scan = pci_domain_scan_bus, + .phase4_read_resources = i5000_domain_read_resources, + .phase4_set_resources = i5000_domain_set_resources, + .phase5_enable_resources = enable_childrens_resources, + .phase6_init = no_op, + .ops_pci_bus = &pci_cf8_conf1, + +}; + +/* Here are the operations for the northbridge. */ +struct device_operations i5000_northbridge = { + .id = {.type = DEVICE_ID_PCI, + {.pci = {.vendor = 0x8086,.device = 0x1237}}}, + .constructor = default_device_constructor, + .phase3_scan = NULL, + .phase4_read_resources = i5000_read_resources, + .phase4_set_resources = i5000_set_resources, + .phase5_enable_resources = no_op, + .phase6_init = no_op, + .ops_pci_bus = &pci_cf8_conf1, + +};

2 1

[PATCH] flahsrom: fix off-by-one error in erase
by Jody McIntyre 26 Jan '09

26 Jan '09

There appears to be an off-by-one error when using flashrom's erase: # flashrom -E Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel 631xESB/632xESB/3100", enabling flash write... OK. Found chip "SST SST49LF008A" (1024 KB) at physical address 0xfff00000. Erasing flash chip... FAILED! ERROR at 0x00100000: Expected=0xff, Read=0x00 Index: flashrom.c =================================================================== --- flashrom.c (revision 3882) +++ flashrom.c (working copy) @@ -592,7 +592,7 @@ memcpy(buf, (const char *)flash->virtual_memory, size); else flash->read(flash, buf); - for (erasedbytes = 0; erasedbytes <= size; erasedbytes++) + for (erasedbytes = 0; erasedbytes < size; erasedbytes++) if (0xff != buf[erasedbytes]) { printf("FAILED!\n"); fprintf(stderr, "ERROR at 0x%08x: Expected=0xff, Read=0x%02x\n",

3 5

r3921 - trunk/util/msrtool
by svn＠coreboot.org 26 Jan '09

26 Jan '09

Author: stuge Date: 2009-01-26 18:18:31 +0100 (Mon, 26 Jan 2009) New Revision: 3921 Modified: trunk/util/msrtool/msrtool.c trunk/util/msrtool/msrtool.h trunk/util/msrtool/msrutils.c Log: msrtool: Allow MSR symbols (names) to also be used as addresses. Thanks for the idea Mart! Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/util/msrtool/msrtool.c =================================================================== --- trunk/util/msrtool/msrtool.c 2009-01-26 17:03:05 UTC (rev 3920) +++ trunk/util/msrtool/msrtool.c 2009-01-26 17:18:31 UTC (rev 3921) @@ -278,7 +278,7 @@ break; case 'i': input = 1; - addr = strtoul(optarg, NULL, 16); + addr = msraddrbyname(optarg); optarg = strchr(optarg, '='); if (NULL == optarg) { fprintf(stderr, "missing value in -i argument!\n"); @@ -398,7 +398,7 @@ } for (; optind < argc; optind++) { - addr = strtoul(argv[optind], NULL, 16); + addr = msraddrbyname(argv[optind]); if (!sys->rdmsr(cpu, addr, &msrval)) break; decodemsr(cpu, addr, msrval); Modified: trunk/util/msrtool/msrtool.h =================================================================== --- trunk/util/msrtool/msrtool.h 2009-01-26 17:03:05 UTC (rev 3920) +++ trunk/util/msrtool/msrtool.h 2009-01-26 17:18:31 UTC (rev 3921) @@ -157,6 +157,7 @@ struct msr msr_shr(const struct msr a, const uint8_t bits); void msr_and(struct msr *a, const struct msr b); const struct msrdef *findmsrdef(const uint32_t addr); +const uint32_t msraddrbyname(const char *name); void dumpmsrdefs(const struct targetdef *t); int dumpmsrdefsvals(FILE *f, const struct targetdef *t, const uint8_t cpu); uint8_t str2msr(char *str, struct msr *msr); Modified: trunk/util/msrtool/msrutils.c =================================================================== --- trunk/util/msrtool/msrutils.c 2009-01-26 17:03:05 UTC (rev 3920) +++ trunk/util/msrtool/msrutils.c 2009-01-26 17:18:31 UTC (rev 3921) @@ -137,6 +137,22 @@ return NULL; } +const uint32_t msraddrbyname(const char *name) { + uint8_t t; + const uint32_t addr = strtoul(name, NULL, 16); + const struct msrdef *m; + if (!targets) + return 0; + for (t = 0; t < targets_found; t++) + for (m = targets[t]->msrs; !MSR_ISEOT(*m); m++) { + if (addr == m->addr) + return m->addr; + if (!strcasecmp(name, m->symbol)) + return m->addr; + } + return 0; +} + void dumpmsrdefs(const struct targetdef *t) { const struct msrdef *m; const struct msrbits *mb;

1 0

r3920 - trunk/util/msrtool
by svn＠coreboot.org 26 Jan '09

26 Jan '09

Author: stuge Date: 2009-01-26 18:03:05 +0100 (Mon, 26 Jan 2009) New Revision: 3920 Modified: trunk/util/msrtool/linux.c Log: msrtool: Linux /dev/cpu/*/msr returns the low 32 bits before the high 32 bits. Thanks to Mart for spotting this! Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/util/msrtool/linux.c =================================================================== --- trunk/util/msrtool/linux.c 2009-01-26 15:29:27 UTC (rev 3919) +++ trunk/util/msrtool/linux.c 2009-01-26 17:03:05 UTC (rev 3920) @@ -76,13 +76,16 @@ } int linux_rdmsr(uint8_t cpu, uint32_t addr, struct msr *val) { + struct msr tmp; if (lseek(msr_fd[cpu], addr, SEEK_SET) == -1) { SYSERROR(lseek, addr); return 0; } - if (read(msr_fd[cpu], val, 8) != 8) { + if (read(msr_fd[cpu], &tmp, 8) != 8) { SYSERROR(read, addr); return 0; } + val->hi = tmp.lo; + val->lo = tmp.hi; return 1; }

1 0

r3919 - trunk/util/flashrom
by svn＠coreboot.org 26 Jan '09

26 Jan '09

Author: stuge Date: 2009-01-26 16:29:27 +0100 (Mon, 26 Jan 2009) New Revision: 3919 Modified: trunk/util/flashrom/chipset_enable.c Log: flashrom: Add VT8237A PCI ID Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/util/flashrom/chipset_enable.c =================================================================== --- trunk/util/flashrom/chipset_enable.c 2009-01-26 15:19:43 UTC (rev 3918) +++ trunk/util/flashrom/chipset_enable.c 2009-01-26 15:29:27 UTC (rev 3919) @@ -898,6 +898,7 @@ {0x1106, 0x8231, "VIA VT8231", enable_flash_vt823x}, {0x1106, 0x3177, "VIA VT8235", enable_flash_vt823x}, {0x1106, 0x3227, "VIA VT8237", enable_flash_vt823x}, + {0x1106, 0x3337, "VIA VT8237A", enable_flash_vt823x}, {0x1106, 0x3372, "VIA VT8237S", enable_flash_vt8237s_spi}, {0x1106, 0x8324, "VIA CX700", enable_flash_vt823x}, {0x1106, 0x0586, "VIA VT82C586A/B", enable_flash_amd8111},

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coreboot January 2009