coreboot January 2009

coreboot@coreboot.org

66 participants
320 discussions

Re: [coreboot] SB600 HDA can't find codec fix
by Dan Lykowski 01 Feb '09

01 Feb '09

Diff was being silly and I wanted to get the patch posted before I left work for the day. I've cleaned up the patch and included it. I wasn't able to find where INTA was used so I used what the RPR lists as default. INTG. After looking at the mptable, I agree INTA is the correct answer. I've corrected it. I used dev_find_slot because I copied from the SATA driver. I've added the comment just like the SATA driver has. I don't know what the difference is, or why the SATA driver did this. The reordering was based on what order things happen in the BIOS Developers guide, RPR, and SATA driver. I fixed the order of the devices that didn't matter to clean up the change log. 1. Enable the Chip 2. Setup the SMBus registers 3. Setup the Device Registers 4. Look for Codec 5. Init Codec The codec init was changed to match the description in the RRG pg 235. Mem Reg: Base + 08h Bit 0. There were unneeded things happening. So here is the second try. Thanks, Dan Lykowski Signed-off-by: Dan Lykowski <lykowdk(a)gmail.com>

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Hi everyone!
by N. Pattakos 31 Jan '09

31 Jan '09

Hi, everyone! I am pleased to join this list as I am very excited about this project. Most likely I will ask for some information, but I will also try to help. For now I would like to inform you that yahoo mail, which I use, "sees" mails from coreboot.org as spam mails. have a nice afternoon. -- -------------------------------------------------------------- Nicholas Pattakos -------------------------------------------------------------- No more "iPhone" please ... http://www.freeyourphone.org --------------------------------------------------------------

1 0

test
by Carl-Daniel Hailfinger 30 Jan '09

30 Jan '09

Somehow my mail from a few hours ago didn't get through, although I'm getting newer mails from the list. We'll see if this one works out. Regards, Carl-Daniel

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r3924 - in trunk/coreboot-v2/src/northbridge/amd: amdfam10 amdk8
by svn＠coreboot.org 30 Jan '09

30 Jan '09

Author: hailfinger Date: 2009-01-30 03:05:20 +0100 (Fri, 30 Jan 2009) New Revision: 3924 Modified: trunk/coreboot-v2/src/northbridge/amd/amdfam10/amdfam10_acpi.c trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_acpi.c Log: Bring AMD K8 ACPI mangling more in line with Fam10 ACPI mangling. No functional changes, only a little bit of (mostly formatting) cleanup to make merging easier. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/coreboot-v2/src/northbridge/amd/amdfam10/amdfam10_acpi.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdfam10/amdfam10_acpi.c 2009-01-28 00:27:54 UTC (rev 3923) +++ trunk/coreboot-v2/src/northbridge/amd/amdfam10/amdfam10_acpi.c 2009-01-30 02:05:20 UTC (rev 3924) @@ -66,7 +66,6 @@ return current; } - unsigned long acpi_create_srat_lapics(unsigned long current) { device_t cpu; @@ -98,7 +97,6 @@ return resultk; } - struct acpi_srat_mem_state { unsigned long current; }; @@ -113,10 +111,10 @@ printk_debug("set_srat_mem: dev %s, res->index=%04x startk=%08x, sizek=%08x\n", dev_path(dev), res->index, basek, sizek); /* - 0-640K must be on node 0 - next range is from 1M--- - So will cut off before 1M in the mem range - */ + * 0-640K must be on node 0 + * next range is from 1M--- + * So will cut off before 1M in the mem range + */ if((basek+sizek)<1024) return; if(basek<1024) { @@ -128,7 +126,6 @@ state->current += acpi_create_srat_mem((acpi_srat_mem_t *)state->current, (res->index & 0xf), basek, sizek, 1); } - unsigned long acpi_fill_srat(unsigned long current) { struct acpi_srat_mem_state srat_mem_state; @@ -184,7 +181,6 @@ return current; } - // moved from mb acpi_tables.c static void intx_to_stream(u32 val, u32 len, u8 *dest) { @@ -194,13 +190,11 @@ } } - static void int_to_stream(u32 val, u8 *dest) { return intx_to_stream(val, 4, dest); } - // used by acpi_tables.h void update_ssdt(void *ssdt) { @@ -293,7 +287,6 @@ } - void update_sspr(void *sspr, u32 nodeid, u32 cpuindex) { u8 *CPU; Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_acpi.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_acpi.c 2009-01-28 00:27:54 UTC (rev 3923) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/amdk8_acpi.c 2009-01-30 02:05:20 UTC (rev 3924) @@ -45,7 +45,7 @@ #include <cpu/amd/mtrr.h> #include <cpu/amd/amdk8_sysconf.h> -//it seems these function can be moved arch/i386/boot/acpi.c +//it seems some functions can be moved arch/i386/boot/acpi.c unsigned long acpi_create_madt_lapics(unsigned long current) { @@ -54,8 +54,7 @@ for(cpu = all_devices; cpu; cpu = cpu->next) { if ((cpu->path.type != DEVICE_PATH_APIC) || - (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) - { + (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) { continue; } if (!cpu->enabled) { @@ -63,9 +62,7 @@ } current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, cpu_index, cpu->path.u.apic.apic_id); cpu_index++; - } - return current; } @@ -76,8 +73,7 @@ for(cpu = all_devices; cpu; cpu = cpu->next) { if ((cpu->path.type != DEVICE_PATH_APIC) || - (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) - { + (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) { continue; } if (!cpu->enabled) { @@ -85,9 +81,7 @@ } current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, cpu_index, flags, lint); cpu_index++; - } - return current; } @@ -98,8 +92,7 @@ for(cpu = all_devices; cpu; cpu = cpu->next) { if ((cpu->path.type != DEVICE_PATH_APIC) || - (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) - { + (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) { continue; } if (!cpu->enabled) { @@ -108,9 +101,7 @@ printk_debug("SRAT: lapic cpu_index=%02x, node_id=%02x, apic_id=%02x\n", cpu_index, cpu->path.u.apic.node_id, cpu->path.u.apic.apic_id); current += acpi_create_srat_lapic((acpi_srat_lapic_t *)current, cpu->path.u.apic.node_id, cpu->path.u.apic.apic_id); cpu_index++; - } - return current; } @@ -119,8 +110,7 @@ unsigned long resultk; if (value < (1ULL << 42)) { resultk = value >> 10; - } - else { + } else { resultk = 0xffffffff; } return resultk; @@ -140,10 +130,10 @@ printk_debug("set_srat_mem: dev %s, res->index=%04x startk=%08x, sizek=%08x\n", dev_path(dev), res->index, basek, sizek); /* - 0-640K must be on node 0 - next range is from 1M--- - So will cut off before 1M in the mem range - */ + * 0-640K must be on node 0 + * next range is from 1M--- + * So will cut off before 1M in the mem range + */ if((basek+sizek)<1024) return; if(basek<1024) { @@ -151,7 +141,8 @@ basek = 1024; } - state->current += acpi_create_srat_mem((acpi_srat_mem_t *)state->current, (res->index & 0xf), basek, sizek, 1); // need to figure out NV + // need to figure out NV + state->current += acpi_create_srat_mem((acpi_srat_mem_t *)state->current, (res->index & 0xf), basek, sizek, 1); } unsigned long acpi_fill_srat(unsigned long current) @@ -172,11 +163,9 @@ set_srat_mem, &srat_mem_state); current = srat_mem_state.current; - return current; } - unsigned long acpi_fill_slit(unsigned long current) { /* need to find out the node num at first */ @@ -184,7 +173,7 @@ /* fill the next num*num byte with distance, local is 10, 1 hop mean 20, and 2 hop with 30.... */ /* because We has assume that we know the topology of the HT connection, So we can have set if we know the node_num */ - static uint8_t hops_8[] = { 0, 1, 1, 2, 2, 3, 3, 4, + static u8 hops_8[] = { 0, 1, 1, 2, 2, 3, 3, 4, 1, 0, 2, 1, 3, 2, 4, 3, 1, 2, 0, 1, 1, 2, 2, 3, 2, 1, 1, 0, 2, 1, 3, 2, @@ -193,14 +182,14 @@ 3, 4, 2, 3, 1, 2, 0, 1, 4, 4, 3, 2, 2, 1, 1, 0 }; -// uint8_t outer_node[8]; +// u8 outer_node[8]; - uint8_t *p = (uint8_t *)current; + u8 *p = (u8 *)current; int nodes = sysconf.nodes; int i,j; memset(p, 0, 8+nodes*nodes); -// memset((uint8_t *)outer_node, 0, 8); - *p = (uint8_t) nodes; +// memset((u8 *)outer_node, 0, 8); + *p = (u8) nodes; p += 8; #if 0 @@ -212,11 +201,12 @@ for(i=0;i<nodes;i++) { for(j=0;j<nodes; j++) { - if(i==j) { p[i*nodes+j] = 10; } - else { + if(i==j) { + p[i*nodes+j] = 10; + } else { #if 0 int k; - uint8_t latency_factor = 0; + u8 latency_factor = 0; int k_start, k_end; if(i<j) { k_start = i; @@ -246,37 +236,36 @@ return current; } - -//end - - // moved from mb acpi_tables.c -static void int_to_stream(uint32_t val, uint8_t *dest) +static void intx_to_stream(u32 val, u32 len, u8 *dest) { int i; - for(i=0;i<4;i++) { + for(i=0;i<len;i++) { *(dest+i) = (val >> (8*i)) & 0xff; } } +static void int_to_stream(u32 val, u8 *dest) +{ + return intx_to_stream(val, 4, dest); +} // used by acpi_tables.h - void update_ssdt(void *ssdt) { - uint8_t *BUSN; - uint8_t *MMIO; - uint8_t *PCIO; - uint8_t *SBLK; - uint8_t *TOM1; - uint8_t *SBDN; - uint8_t *HCLK; - uint8_t *HCDN; - uint8_t *CBST; + u8 *BUSN; + u8 *MMIO; + u8 *PCIO; + u8 *SBLK; + u8 *TOM1; + u8 *SBDN; + u8 *HCLK; + u8 *HCDN; + u8 *CBST; int i; device_t dev; - uint32_t dword; + u32 dword; msr_t msr; BUSN = ssdt+0x3a; //+5 will be next BUSN @@ -303,7 +292,7 @@ int_to_stream(dword, PCIO+i*5); } - *SBLK = (uint8_t)(sysconf.sblk); + *SBLK = (u8)(sysconf.sblk); msr = rdmsr(TOP_MEM); int_to_stream(msr.lo, TOM1); @@ -320,10 +309,10 @@ int_to_stream(sysconf.sbdn, SBDN); if((sysconf.pci1234[0] >> 12) & 0xff) { //sb chain on other than bus 0 - *CBST = (uint8_t) (0x0f); + *CBST = (u8) (0x0f); } else { - *CBST = (uint8_t) (0x00); + *CBST = (u8) (0x00); } }

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Re: [coreboot] SeaBIOS on DBE63 not functional
by Kevin O'Connor 30 Jan '09

30 Jan '09

On Wed, Jan 28, 2009 at 05:43:31PM +0200, Mart Raudsepp wrote: > Ühel kenal päeval, K, 2009-01-28 kell 10:28, kirjutas Kevin O'Connor: > > On Wed, Jan 28, 2009 at 04:25:56AM +0200, Mart Raudsepp wrote: > > > On T, 2009-01-27 at 20:02 -0500, Kevin O'Connor wrote: > > > > > The log output at default loglevel of 1 is attached. At higher log > > > > > levels the last dump seems to come from a different place. Should I > > > > > gather such logs with a larger loglevel or does this say something > > > > > revealing already? Anything else I can provide here? > > > > Those messages aren't reporting a problem - I see them on my epia-cn > > > > and on qemu. You'll need to increase the debugging level to see if > > > > something else is seen before a failure. I'm CC'ing the coreboot list again. > I think loglevel 20 went into an infinite loop (just this time maybe?), > and I see a lot of these blocks, with either three or four entries: > > handle_1c That's the user timer irq handler. > enter handle_16: > a=00000100 b=00000049 c=00008e26 d=00000000 si=00000010 di=00000044 > ds=00000000 es=00000000 ip=00008e55 cs=00000000 f=00000246 r=00001fd2 That's grub asking if there is keyboard input. > handle_08 That's the timer irq handler. So, you're getting interrupts, and it appears grub is running (or at least responding to irqs). BTW, what are you using for a vgabios? I thought geode didn't have a vga bios available. -Kevin

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Re: [coreboot] [OpenBIOS] OpenBIOS SVN r416 breaks coreboot-v3
by Myles Watson 29 Jan '09

29 Jan '09

> > What version of qemu are you using? I tried building my own image, > > and I don't see the failure. I'm using Coreboot v3 1123 like you are, > > OpenBIOS 428, and qemu 0.9.1-5ubuntu3. I'm attaching my log. I guess > > it could be a difference in the configuration of OpenBIOS too. > > I think I mentioned in my original email that I was using SVN pulls of > all 3 of openbios, coreboot and qemu. In fact a quick check here shows: Sorry I forgot that. > coreboot-v3: r1123 > openbios: r428 > qemu: r6466 > > It looks as if you may have found part of the problem with regard to the > qemu version; I've just compiled up qemu 0.9.1 from source and tried it > with the same bios.bin generated from coreboot-v3/openbios above - and > it boots! So perhaps qemu is involved in this somehow? Can you verify at > your end? Yes. qemu 0.9.1 works with v2+OpenBIOS and v3+OpenBIOS, but the latest qemu doesn't. The latest qemu works with v2 or v3 +OpenBIOS r186, so it looks like an interaction between OpenBIOS and qemu. HTH, Myles

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[FYI] flashrom SST SST49LF003A/B reading results.
by Peter Lemenkov 29 Jan '09

29 Jan '09

Hello All! [petro@host-12-116 flashrom]$ sudo ./flashrom -v -r ~/bios.bin Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel ICH6/ICH6R", enabling flash write... OK. Found chip "SST SST49LF003A/B" (384 KB) at physical address 0xfffa0000. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE Please email a report to flashrom(a)coreboot.org if any of the above operations work correctly for you with this flash part. Please include the full output from the program, including chipset found. Thank you for your help! === Reading flash... done. Verifying flash... VERIFIED. [petro@host-12-116 flashrom]$ -- With best regards!

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MTRR setup strategy
by Carl-Daniel Hailfinger 29 Jan '09

29 Jan '09

Hi, the problems Jason is seeing with slow boot can be explained with our incomplete and less than efficient MTRR setup. We never use subtractive MTRRs, so if a range is not power-of-two sized, we try to combine it from subranges which are power-of-two sized. For large ranges which are a little smaller than a power of two, we waste MTRRs and in some cases even run out of MTRRs. That's not something to be proud of. Example: We want to cache 0MB - (2G-64M-64k). Current setup: reg00: base=0x00000000 ( 0MB), size=1024MB: write-back, count=1 reg01: base=0x40000000 (1024MB), size= 512MB: write-back, count=1 reg02: base=0x60000000 (1536MB), size= 256MB: write-back, count=1 reg03: base=0x70000000 (1792MB), size= 128MB: write-back, count=1 reg04: base=0x78000000 (1920MB), size= 32MB: write-back, count=1 reg05: base=0x7a000000 (1952MB), size= 16MB: write-back, count=1 reg06: base=0x7b000000 (1968MB), size= 8MB: write-back, count=1 reg07: base=0x7b800000 (1976MB), size= 4MB: write-back, count=1 --Here we run out of MTRRs, additionally needed MTRRs follow-- reg08: base=0x7bc00000 (1980MB), size= 2048kB: write-back, count=1 reg09: base=0x7be00000 (1982MB), size= 1024kB: write-back, count=1 reg10: base=0x7bf00000 (1983MB), size= 512kB: write-back, count=1 reg11: base=0x7bf80000 (1983MB), size= 256kB: write-back, count=1 reg12: base=0x7bfc0000 (1983MB), size= 128kB: write-back, count=1 reg13: base=0x7bfe0000 (1983MB), size= 64kB: write-back, count=1 We could achieve the same effect with a subtractive setup: reg00: base=0x00000000 ( 0MB), size=2048MB: write-back, count=1 reg01: base=0x7c000000 (1984MB), size=64MB: uncached, count=1 reg02: base=0x7bff0000 (1983MB), size=64kB: uncached, count=1 However, a subtractive setup is not always more efficient. That means we have to select the best setup type. I devised a slightly tricky algorithm to do that: 1. Check if there are multiple disjoint cached areas in a given power-of-two sized area. 1a. If no, go to step 2 1b. If yes, stop here. Need advanced setup not described here. 2. additive_count=bitcount(top_cached_addr+1) 3. subtractive_count=bitcount(rounduptonextpowerof2(top_cached_addr)-(top_cached_addr+1)) 4. if (additive_count>subtractive_count) go to subtractive_method else go to additive_method Regards, Carl-Daniel -- http://www.hailfinger.org/

6 19

Will coreboot run on my acer aspire L5100 machine?
by Gal Frishman 29 Jan '09

29 Jan '09

Hi all, I'm sending this mail as instructed by the FAQ. I want to know if coreboot would run on my pc because original bios doesn't enable amd virtualization which is supported by cpu... *relevant output of lshw:* product: Aspire L5100 vendor: Acer version: R01-B0 width: 64 bits capabilities: smbios-2.5 dmi-2.5 vsyscall64 vsyscall32 configuration: boot=normal chassis=desktop uuid=001C2589-1139-2008-0305-133923000000 *-core description: Motherboard product: FRS690L vendor: Acer physical id: 0 *-firmware description: BIOS vendor: Phoenix Technologies, LTD physical id: 0 version: R01-B0 (01/29/2008) size: 128KiB capacity: 448KiB capabilities: isa pci pnp apm upgrade shadowing cdboot bootselect socketedrom edd int13floppy360 int13floppy1200 int13floppy720 int13floppy2880 int5printscreen int9keyboard int14serial int17printer int10video acpi usb agp ls120boot zipboot biosbootspecification *-cpu description: CPU product: AMD Athlon(tm) 64 X2 Dual Core Processor 4400+ vendor: Advanced Micro Devices [AMD] physical id: 4 bus info: cpu@0 version: AMD Athlon(tm) 64 X2 Dual Core Processor 4400+ slot: Socket AM2 size: 2300MHz capacity: 3GHz width: 64 bits clock: 199MHz capabilities: fpu fpu_exception wp vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt rdtscp x86-64 3dnowext 3dnow rep_good nopl pni cx16 lahf_lm cmp_legacy svm extapic cr8_legacy 3dnowprefetch cpufreq *-cache:0 description: L1 cache physical id: 8 slot: Internal Cache size: 128KiB capacity: 128KiB capabilities: synchronous internal write-back *-cache:1 description: L2 cache physical id: 9 slot: External Cache size: 512KiB capacity: 512KiB capabilities: synchronous internal write-back *-memory description: System Memory physical id: 1f slot: System board or motherboard size: 2GiB *-bank:0 description: DIMM 667 MHz (1.5 ns) physical id: 0 slot: A0 size: 1GiB width: 64 bits clock: 667MHz (1.5ns) *-bank:1 description: DIMM 667 MHz (1.5 ns) physical id: 1 slot: A2 size: 1GiB width: 64 bits clock: 667MHz (1.5ns) *-pci:0 description: Host bridge product: RS690 Host Bridge vendor: ATI Technologies Inc physical id: 100 bus info: pci@0000:00:00.0 version: 00 width: 32 bits clock: 66MHz configuration: latency=64 *-pci:0 description: PCI bridge product: RS690 PCI to PCI Bridge (Internal gfx) vendor: ATI Technologies Inc physical id: 1 bus info: pci@0000:00:01.0 version: 00 width: 32 bits clock: 66MHz capabilities: pci ht bus_master cap_list bus info: pci@0000:01:05.0 version: 00 width: 64 bits clock: 33MHz capabilities: pm msi bus_master cap_list configuration: driver=fglrx_pci latency=64 module=fglrx *-multimedia description: Audio device product: Radeon X1200 Series Audio Controller vendor: ATI Technologies Inc physical id: 5.2 bus info: pci@0000:01:05.2 version: 00 width: 64 bits clock: 33MHz capabilities: pm msi bus_master cap_list configuration: driver=HDA Intel latency=64 module=snd_hda_intel *-pci:1 description: PCI bridge product: RS690 PCI to PCI Bridge (PCI Express Port 3) vendor: ATI Technologies Inc physical id: 7 bus info: pci@0000:00:07.0 version: 00 width: 32 bits clock: 33MHz capabilities: pci pm pciexpress msi ht bus_master cap_list configuration: driver=pcieport-driver *-network description: Ethernet interface product: RTL8111/8168B PCI Express Gigabit Ethernet controller00:00.0 Host bridge: ATI Technologies Inc RS690 Host Bridge vendor: Realtek Semiconductor Co., Ltd. physical id: 0 bus info: pci@0000:02:00.0 bus info: pci@0000 :00:12.0 logical name: scsi2 version: 00 width: 32 bits clock: 66MHz capabilities: storage pm bus_master cap_list emulated configuration: driver=ahci latency=64 module=ahci *output of lspci:* 00:01.0 PCI bridge: ATI Technologies Inc RS690 PCI to PCI Bridge (Internal gfx) 00:07.0 PCI bridge: ATI Technologies Inc RS690 PCI to PCI Bridge (PCI Express Port 3) 00:12.0 SATA controller: ATI Technologies Inc SB600 Non-Raid-5 SATA 00:13.0 USB Controller: ATI Technologies Inc SB600 USB (OHCI0) 00:13.1 USB Controller: ATI Technologies Inc SB600 USB (OHCI1) 00:13.2 USB Controller: ATI Technologies Inc SB600 USB (OHCI2) 00:13.3 USB Controller: ATI Technologies Inc SB600 USB (OHCI3) 00:13.4 USB Controller: ATI Technologies Inc SB600 USB (OHCI4) 00:13.5 USB Controller: ATI Technologies Inc SB600 USB Controller (EHCI) 00:14.0 SMBus: ATI Technologies Inc SBx00 SMBus Controller (rev 14) 00:14.1 IDE interface: ATI Technologies Inc SB600 IDE 00:14.2 Audio device: ATI Technologies Inc SBx00 Azalia (Intel HDA) 00:14.3 ISA bridge: ATI Technologies Inc SB600 PCI to LPC Bridge 00:14.4 PCI bridge: ATI Technologies Inc SBx00 PCI to PCI Bridge 00:18.0 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration 00:18.1 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map 00:18.2 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller 00:18.3 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control 01:05.0 VGA compatible controller: ATI Technologies Inc RS690 [Radeon X1200 Series] 01:05.2 Audio device: ATI Technologies Inc Radeon X1200 Series Audio Controller 02:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller (rev 01) 03:06.0 FireWire (IEEE 1394): Texas Instruments TSB43AB23 IEEE-1394a-2000 Controller (PHY/Link) *and link for acer's specs:* http://www.acer.co.il/public/page9.do?sp=page4&dau34.oid=36408&UserCtxParam… Thank you.

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Acer L320 based BIOS
by Pál Dorogi 29 Jan '09

29 Jan '09

Hi All, I'm trying to build a coreboot-v3 ROM for an Acer L320 (ViiV) box based on Uwe's Kontron sources. Finally it's been built due some modifications on the sources (new target /w different superio etc.). But, unfortunately I'm a littlebit confused as the kontron's ROM is based on Core 2 Duo (C2D) CPU, but mine board just has 1 Core Duo (CD). An other thing I haven't created a proper static device tree for that config, so I have some more tasks left on this too. As I newbie I would like ask you guys what's the next step(s) to get it work. Unfortunately, that board doesn't have any serial port but USB, but the USB debug cable is a littlebit expensive for me. So,I want to be sure that the ROM should come up at least to drive the on-board VGA for debug output. The brief details of the board:) ================================= CPU ================================= Socket: LGA 775 Supported CPUs (hopefully): Pentium 4, Pentium, D 820/920, Core Duo, Core 2 Duo Hyper-Threading ----------------------------------------------------------------- | 533/800 Mhz FSB | ================================= MCH Intel 946GZ ================================= 1 Analog VGA (Intel GMA 3000) 1 SDVO: Not Used (ADD2) 2 of 2 dual channel memory (DDR2) CHA & CHB 0 of 1 PCIex16 for graphics ----------------------------------------------------------------- | DMI (Direct Media Interface) | ================================= ICH (I/O Controller HUB) 82801DGH I/O Controller (ICH7) ================================= 1 x PCI Bus 1 x Ethernet LAN (82573L PRO PM (Vidalia) 10/100/1000) on the one PCI-ex1 Rev 1.0a or 1.1 6 of 8 USB 2 1 of 4 SATA 1 SMBUS 2.0/I2C 1 Power Mgmt (ACPI 2.0/1.1) 1 IDE (CD/DVD ROM) 1 AC'97 Audio 1 Intel HD Audio ----------------------------------------------------------------- | LPC Interface | ================================= Superio and FWH/LPC ================================= ITE8217F superio PLCC32 512KB flash ----------------------------------------------------------------- Cheers, Pal

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coreboot January 2009