coreboot January 2009

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commercially available 690 mainboards
by ron minnich 28 Jan '09

28 Jan '09

Anybody got a 690 mainboard we could buy today that is supported? ron

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Re: [coreboot] [OpenBIOS] OpenBIOS SVN r416 breaks coreboot-v3
by Aurelien Jarno 28 Jan '09

28 Jan '09

Mark Cave-Ayland a écrit : > Hi everyone, > > Whilst playing around with openbios to try and understand how it works > on different platforms, I found that using coreboot-v3 with openbios SVN > causes openbios to panic on boot under qemu SVN. The trace can be found > here: > > http://pastebin.siriusit.co.uk/coreboot-v3-panic.txt > > With the help of some people on the coreboot mailing list, I've > performed an SVN bisection and found that the panic starts appearing at > r416 in openbios SVN for which the commit message can be found here: > > http://lists.openbios.org/pipermail/openbios/2009-January/003401.html > > However, I can't find any reference to the rationale behind the commit. > Can anyone explain further explain whether is commit is correct or not? The rationale is available here: http://lists.openbios.org/pipermail/openbios/2009-January/003391.html This commit fixes two different problems encountered on SPARC64 and PowerPC. First of all it makes sure that no PCI device get allocated port 0, which doesn't exists. Secondly it fixes problems with non-PCI devices that are using I/O ports at fixed location. This includes the video card, i8259, rtc, serial port, hard-disk controller, etc. Without this patch, the PCI cards are getting allocated the I/O ports of those devices, thus causing crashes. I wonder why it causes problem on x86. What is the initial value of arch->io_base? I am unable to find that looking at the code. -- .''`. Aurelien Jarno | GPG: 1024D/F1BCDB73 : :' : Debian developer | Electrical Engineer `. `' aurel32(a)debian.org | aurelien(a)aurel32.net `- people.debian.org/~aurel32 | www.aurel32.net

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Re: [coreboot] SeaBIOS on DBE63 not functional
by Kevin O'Connor 28 Jan '09

28 Jan '09

Hi - I'm CC'ing coreboot list again. On Wed, Jan 28, 2009 at 05:53:12PM +0200, Mart Raudsepp wrote: > Ühel kenal päeval, K, 2009-01-28 kell 17:43, kirjutas Mart Raudsepp: > > Ühel kenal päeval, K, 2009-01-28 kell 10:28, kirjutas Kevin O'Connor: > > > Debug level 20 tends to show all the irqs - which can adversely impact > > > the boot because of timing. So sending both the log from debug level > > > 20 and a log with debug level 8 would help. > > Trying with loglevel 8 > > Result: > > LAR: load_file: No such file 'normal/payload/segment1' > LAR: load_file_segments: All loaded, entry 0x000f7e6c > ========== mainboard_pre_payload: done > ========================================= > Start bios > init ivt > init bda > init pic > init timer > tsc calibrate start=2812945761 end=2813687197 diff=741436 > CPU Mhz=431 > math cp init > bios_table_addr: 0x000f8e30 end=0x000f9030 > Find memory size > Attempting to find coreboot table > Add to e820 map: 00000000 00000b84 2 > Add to e820 map: 00000b84 0009f47c 1 > Add to e820 map: 000f0000 000004b8 2 > Add to e820 map: 00100000 3eee0000 1 > Add to e820 map: 00000000 00004000 1 > init SMBIOS tables > SMBIOS table addr=0x000f8e30 > Add to e820 map: 000a0000 00050000 -1 > Add to e820 map: 0009fc00 00000400 2 > Add to e820 map: 000f0000 00010000 2 > Ram Size=0x3efe0000 > init PNPBIOS table > init keyboard > i8042_flush > i8042 flushed 000000ff (status=000000ff) > i8042 flushed 000000ff (status=000000ff) > i8042 flushed 000000ff (status=000000ff) > i8042 flushed 000000ff (status=000000ff) > i8042 flushed 000000ff (status=000000ff) > i8042 flushed 000000ff (status=000000ff) > i8042 flushed 000000ff (status=000000ff) > i8042 flushed 000000ff (status=000000ff) > i8042 flushed 000000ff (status=000000ff) > i8042 flushed 000000ff (status=000000ff) > i8042 flushed 000000ff (status=000000ff) > i8042 flushed 000000ff (status=000000ff) > i8042 flushed 000000ff (status=000000ff) > i8042 flushed 000000ff (status=000000ff) > i8042 flushed 000000ff (status=000000ff) > i8042 flushed 000000ff (status=000000ff) > i8042 timeout on flush You appear not to have an i8042 controller (io ports 0x60/0x64). Which means you wont be able to use the keyboard. > init lpt > init serial > e820 map has 4 items: > 0: 0000000000000000 - 000000000009fc00 = 1 > 1: 000000000009fc00 - 00000000000a0000 = 2 > 2: 00000000000f0000 - 0000000000100000 = 2 > 3: 0000000000100000 - 000000003efe0000 = 1 > final bios_table_addr: 0x000f8f3a (used 51%) > init hard drives > ATA controller 0 at 000001f0/000003f0 (dev 0000007a prog_if 00000080) > ATA controller 1 at 00000170/00000370 (dev 0000007a prog_if 00000080) > ata_detect(1) drive=0 sc=00000055 sn=000000aa > ata_reset(1) status=00000080 > ata_reset(2) status=00000050 > ata_detect(2) drive=0 sc=00000001 sn=00000001 > ata_detect(3) drive=0 sc=00000001 sn=00000001 cl=00000000 ch=00000000 > st=00000050 > ata0-0: PCHS=7866/16/63 translation=large LCHS=983/128/63 > ata0 master: APACER CF SMI222AD ATA-0 Hard-Disk (3871 MiBytes) > ata_detect(1) drive=1 sc=00000055 sn=000000aa > ata_reset(1) status=00000080 > ata_reset(2) status=00000050 > ata_detect(2) drive=1 sc=00000001 sn=00000001 > ata_detect(3) drive=1 sc=00000001 sn=00000001 cl=00000000 ch=00000000 > st=00000000 > ata0 slave: Unknown device > ata_detect(1) drive=2 sc=000000ff sn=000000ff > ata_detect(1) drive=3 sc=000000ff sn=000000ff > > init boot device ordering > Press F12 for boot menu. > > Jump to int19 > Changing serial settings was 00000003/00000002 now 00000003/00000000 > enter handle_19: > NULL > Booting from Floppy... > fail floppy_13XX:729(00000001): > a=00000201 b=00000000 c=00000001 d=00000000 si=00000000 di=00000000 > ds=00000000 es=000007c0 ip=0000e3f8 cs=0000f000 f=00000002 r=00007b5e > Boot failed: could not read the boot disk > > enter handle_18: > NULL > Booting from CD-Rom... > CDROM boot failure code : 00000002 > Boot failed: could not read the boot disk > > enter handle_18: > NULL > Booting from Hard Disk... > Booting from 00000000:00007c00 > ata_reset(1) status=00000080 > ata_reset(2) status=00000050 > enter handle_12: > a=00000000 b=00000000 c=00000000 d=00000080 si=00002118 di=000042ec > ds=00000000 es=00000000 ip=000024c1 cs=00000000 f=00000297 r=00001fd2 > ata_reset(1) status=00000080 > ata_reset(2) status=00000050 > enter handle_12: > a=00000000 b=00000000 c=00000000 d=00000580 si=00002118 di=000541ec > ds=00000000 es=00000000 ip=00008a01 cs=00000000 f=00000297 r=00001fd2 > fail get_device:644(00000001): > a=00004100 b=000055aa c=0005425c d=00054281 si=00067fc0 di=00000081 > ds=00000000 es=00000000 ip=000088b5 cs=00000000 f=00000246 r=00001fd2 > fail get_device:644(00000001): > a=00000800 b=00000000 c=0005425c d=00054281 si=00067fc0 di=00000081 > ds=00000000 es=00000000 ip=000088e9 cs=00000000 f=00000246 r=00001fd2 > fail handle_15XX:313(00000086): > a=000000c0 b=00000000 c=00054201 d=00000001 si=00067fc0 di=00000000 > ds=00000000 es=00000000 ip=00008ab6 cs=00000000 f=00000246 r=00001fd2 > > > ... silence or hang Everything else looks okay. What is shown (if anything) on the screen at this point? -Kevin

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SeaBIOS on DBE63 not functional
by Mart Raudsepp 28 Jan '09

28 Jan '09

Hello, Kevin asked to handle this via e-mail, so here we go. I tried booting with SeaBIOS on DBE63 for some fun and profit, but it unfortunately stalls with some register dumps. I haven't been able to really play with SeaBIOS before, as it can't boot from NAND flash that is on DBE61 and DBE62, but now with the DBE63 prototype on my table I can boot from IDE CompactFlash. On a slightly related note, does SeaBIOS really need to do the bootloader job - could I have it just provide the 16bit services or do we need to implement a geode NAND flash driver in it to have it work for those devces? The log output at default loglevel of 1 is attached. At higher log levels the last dump seems to come from a different place. Should I gather such logs with a larger loglevel or does this say something revealing already? Anything else I can provide here? The device boots the GRUB on that CompactFlash fine with legacy BIOS. SeaBIOS gives a similar output when trying a CF with XPe on it. Regards, Mart Raudsepp

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SVN Coreboot-v3 with SVN OpenBIOS payload panics on boot with qemu
by Mark Cave-Ayland 28 Jan '09

28 Jan '09

Hi everyone, I'm been trying the latest SVN versions of coreboot-v3, OpenBIOS and Qemu together and I am experiencing a panic on boot when launching qemu-system-x86_64. I can see some hardware enumeration but before the OpenBIOS prompt appears, qemu puts out the following message on the console: qemu: hardware error: register_ioport_write: invalid opaque As far as I can tell, I don't think that it's a qemu issue since qemu SVN successfully boots with the pre-built coreboot-v3/OpenBIOS image found at http://www.coreboot.org/QEMU#coreboot_v3_.2B_OpenBIOS, which suggests that the bug lies somewhere between OpenBIOS and coreboot. I've uploaded the full console output to http://pastebin.siriusit.co.uk/coreboot-v3-panic.txt in case other people may find it useful. ATB, Mark. -- Mark Cave-Ayland Sirius Corporation - The Open Source Experts http://www.siriusit.co.uk T: +44 870 608 0063

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coreboot on Dell c600
by palito＠o2.pl 28 Jan '09

28 Jan '09

I am thinking about implanting coreboot on my c600 laptop. Would it be possible?

3 2

r3923 - trunk/util/flashrom
by svn＠coreboot.org 28 Jan '09

28 Jan '09

Author: hailfinger Date: 2009-01-28 01:27:54 +0100 (Wed, 28 Jan 2009) New Revision: 3923 Modified: trunk/util/flashrom/flashrom.c Log: Factor out read and erase functions from flashrom main(). Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/util/flashrom/flashrom.c =================================================================== --- trunk/util/flashrom/flashrom.c 2009-01-28 00:19:49 UTC (rev 3922) +++ trunk/util/flashrom/flashrom.c 2009-01-28 00:27:54 UTC (rev 3923) @@ -187,6 +187,61 @@ return 0; } +int read_flash(struct flashchip *flash, char *filename, unsigned int exclude_start_position, unsigned int exclude_end_position) +{ + unsigned long numbytes; + FILE *image; + unsigned long size = flash->total_size * 1024; + unsigned char *buf = calloc(size, sizeof(char)); + if ((image = fopen(filename, "w")) == NULL) { + perror(filename); + exit(1); + } + printf("Reading flash... "); + if (flash->read == NULL) + memcpy(buf, (const char *)flash->virtual_memory, size); + else + flash->read(flash, buf); + + if (exclude_end_position - exclude_start_position > 0) + memset(buf + exclude_start_position, 0, + exclude_end_position - exclude_start_position); + + numbytes = fwrite(buf, 1, size, image); + fclose(image); + printf("%s.\n", numbytes == size ? "done" : "FAILED"); + if (numbytes != size) + return 1; + return 0; +} + +int erase_flash(struct flashchip *flash) +{ + uint32_t erasedbytes; + unsigned long size = flash->total_size * 1024; + unsigned char *buf = calloc(size, sizeof(char)); + printf("Erasing flash chip... "); + if (NULL == flash->erase) { + printf("FAILED!\n"); + fprintf(stderr, "ERROR: flashrom has no erase function for this flash chip.\n"); + return 1; + } + flash->erase(flash); + if (NULL == flash->read) + memcpy(buf, (const char *)flash->virtual_memory, size); + else + flash->read(flash, buf); + for (erasedbytes = 0; erasedbytes < size; erasedbytes++) + if (0xff != buf[erasedbytes]) { + printf("FAILED!\n"); + fprintf(stderr, "ERROR at 0x%08x: Expected=0xff, Read=0x%02x\n", + erasedbytes, buf[erasedbytes]); + return 1; + } + printf("SUCCESS.\n"); + return 0; +} + #define MAX(a, b) ((a) > (b) ? (a) : (b)) #define POS_PRINT(x) do { pos += strlen(x); printf(x); } while (0) @@ -279,7 +334,6 @@ { uint8_t *buf; unsigned long size, numbytes; - uint32_t erasedbytes; FILE *image; /* Probe for up to three flash chips. */ struct flashchip *flash, *flashes[3]; @@ -555,45 +609,10 @@ buf = (uint8_t *) calloc(size, sizeof(char)); if (erase_it) { - printf("Erasing flash chip... "); - if (NULL == flash->erase) { - printf("FAILED!\n"); - fprintf(stderr, "ERROR: flashrom has no erase function for this flash chip.\n"); + if (erase_flash(flash)) return 1; - } - flash->erase(flash); - if (NULL == flash->read) - memcpy(buf, (const char *)flash->virtual_memory, size); - else - flash->read(flash, buf); - for (erasedbytes = 0; erasedbytes < size; erasedbytes++) - if (0xff != buf[erasedbytes]) { - printf("FAILED!\n"); - fprintf(stderr, "ERROR at 0x%08x: Expected=0xff, Read=0x%02x\n", - erasedbytes, buf[erasedbytes]); - return 1; - } - printf("SUCCESS.\n"); - return 0; } else if (read_it) { - if ((image = fopen(filename, "w")) == NULL) { - perror(filename); - exit(1); - } - printf("Reading flash... "); - if (flash->read == NULL) - memcpy(buf, (const char *)flash->virtual_memory, size); - else - flash->read(flash, buf); - - if (exclude_end_position - exclude_start_position > 0) - memset(buf + exclude_start_position, 0, - exclude_end_position - exclude_start_position); - - numbytes = fwrite(buf, 1, size, image); - fclose(image); - printf("%s.\n", numbytes == size ? "done" : "FAILED"); - if (numbytes != size) + if (read_flash(flash, filename, exclude_start_position, exclude_end_position)) return 1; } else { struct stat image_stat;

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r3922 - in trunk/coreboot-v2/src/mainboard/amd: dbm690t pistachio
by svn＠coreboot.org 28 Jan '09

28 Jan '09

Author: hailfinger Date: 2009-01-28 01:19:49 +0100 (Wed, 28 Jan 2009) New Revision: 3922 Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi_tables.c trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi_tables.c Log: Correct FDAT->FADT typo. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi_tables.c 2009-01-26 17:18:31 UTC (rev 3921) +++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/acpi_tables.c 2009-01-28 00:19:49 UTC (rev 3922) @@ -727,7 +727,7 @@ current += dsdt->length; printk_debug("ACPI: * DSDT @ %08x Length %x\n", dsdt, dsdt->length); - /* FDAT */ + /* FADT */ printk_debug("ACPI: * FADT\n"); fadt = (acpi_fadt_t *) current; current += sizeof(acpi_fadt_t); Modified: trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi_tables.c 2009-01-26 17:18:31 UTC (rev 3921) +++ trunk/coreboot-v2/src/mainboard/amd/pistachio/acpi_tables.c 2009-01-28 00:19:49 UTC (rev 3922) @@ -727,7 +727,7 @@ current += dsdt->length; printk_debug("ACPI: * DSDT @ %08x Length %x\n", dsdt, dsdt->length); - /* FDAT */ + /* FADT */ printk_debug("ACPI: * FADT\n"); fadt = (acpi_fadt_t *) current; current += sizeof(acpi_fadt_t);

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Intel Doc reveals ACPI Laptop graphic functions
by Joseph Smith 28 Jan '09

28 Jan '09

Hello, Anyone interested in the quest for coreboot on a Intel Laptop may be interested in this doc. http://intellinuxgraphics.org/ACPI_IGD_OpRegion_%20Spec.pdf It tells how to control laptop lids and blacklight control through ACPI as well as other Intel graphics mysteries including the VBT, LVDS, tv-out, etc. Just thought anyone looking to implement coreboot on an Intel Laptop this would be a key tool. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

1 0

Re: [coreboot] Typo
by Paul Menzel 27 Jan '09

27 Jan '09

Dear Azad, Am Dienstag, den 27.01.2009, 11:21 -0500 schrieb Bakhtiari, Azad CTR WHS/PENREN/EMC: > At http://www.coreboot.org/ASUS_P2B there is a typo on the line > “ECC support WIP Not yet supported by the coreboot 440BX code, but > it's on out TODO list.” > > Should be our instead of out. > > It’s no biggie but someone might appreciate it… Fixed. Thanks for your report, Paul

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coreboot January 2009