coreboot January 2009

coreboot@coreboot.org

66 participants
320 discussions

Problems about booting windows xp
by Wang, Qingpei 10 Mar '09

10 Mar '09

Hi, I am trying to boot windows xp with my dbm690t which has S1G1 CPU, sb600 and rs690 chipset. Now, It still soft reset after loading several files. The serial debug message says: "fail handle_1ab1:154 Fail handle_1aXX:274 Fail get_device:608(00000001) Fail handle_15XX:308(00000086)" Do you have any advice for that or give me and ideas to debug? Thanks Jason Wang BeiJing Technology Development Center Advanced Micro Devices (AMD)

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Coreboot patches for v2 with SeaBIOS
by Myles Watson 05 Mar '09

05 Mar '09

Does anyone have an updated HOWTO for booting XP with SeaBIOS? I'm specifically wondering if there's an option we should add to v2 which relocates BIOS tables so that SeaBIOS doesn't overwrite them, or if we should add that to buildrom. Thanks, Myles

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#105: flashrom: add documentation files (ChangeLog etc) that need to be in the release
by coreboot 16 Feb '09

16 Feb '09

#105: flashrom: add documentation files (ChangeLog etc) that need to be in the release ---------------------------------+------------------------------------------ Reporter: stuge | Owner: somebody Type: enhancement | Status: new Priority: blocker | Milestone: flashrom v1.0 Component: flashrom | Version: Keywords: documentation | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/105> coreboot <http://www.coreboot.org/>

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5536 GPIO
by Peter Stuge 16 Feb '09

16 Feb '09

Hi, Ward and I looked into DIVIL_LBAR_GPIO a little just now. http://pastebin.ca/1315990 (this is msrtool trunk + http://stuge.se/mt.cs5536_pic_divil.patch) The LED driver using the ioport has a hardcoded base address of 0x6100 because that is documented by the vendor. Changing the driver to use 0x1c00 under coreboot works. But looking at the 5536 data book we do not really see how these register values will work. Page 104 describes the operation. IO_BASE=6 BASE_ADDR=0xf0 but: Rule. When a mask bit is cleared, the associated bit in the base address must also be cleared. That rule can not hold true for the values read after tinybios setup. Also the data book does not really explain how the base ioport is 0x6100. Please help? Want to send patch to kernel to read correct ioport from MSR. //Peter

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Geode LX GPL VSA source and binary
by Marc Jones 11 Feb '09

11 Feb '09

This is a tarball and binary of working AMD LX GPL VSA code with the addition on a fix to the flash header for a NAND MMIO BAR (thanks Mart). Their are two reasons that I am sending this to the list. 1. The git repository on laptop.org was not current and luckily some folks at AMD hooked me up with the good source again. With the problems at OLPC I am not sure what will happen with laptop.org. Maybe it is time to find a new home for the code. 2. The binaries were posted on the AMD embedded Linux support page and I don't think that AMD is that interested in maintaining VSA and the binaries any longer. We could probably get them to post this one but that seems like more work than it is worth. So, we need another place to put the binary. Once we have a location, buildrom needs to be updated to get it from the new location. Marc

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[PATCH] Fix bayou payload execution
by Ulf Jordan 10 Feb '09

10 Feb '09

Bayou svn HEAD cannot execute its payloads correctly, due to payloads overwriting bayou in memory. This is in turn due to the lpgcc link run trying to apply both libpayload's and bayou's ldscripts. The two attached patches a) makes lpgcc's choice of ldscript overridable and b) adjusts bayou's ldscript to work with the recent MB changes in libpayload. Compile and runtime tested with bayou, coreinfo and coreboot-v3 in QEMU. /ulf

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Bridge Mem Window/Prefetch Window
by Dan Lykowski 05 Feb '09

05 Feb '09

Can anyone point me in the right direction as to where the Bridge Mem Window/Prefetch Window PCI configurations are defined/setup/used/etc. Coreboot does not set these correctly in my case. ( As compared to the standard BIOS ) Thanks, Dan Lykowski

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Re: [coreboot] generic cpu detection proposal
by Holger Hesselbarth 02 Feb '09

02 Feb '09

sorry for this rather long post. it's an update on the generic cpu detection and initialization source. this update makes it a lot easier to understand what i'm trying to achive (hello Stefan ;)). there are still some essential things missing but that's merely due to unavailable information. if there are questions left don't bother asking! microcode loading could be nicely inserted into the switch-statement in configure_cpu() in config_intel.c this is where model-specific things should go, too. next thing i'm going to write is the L2 cache initalization. to understand the idea of my L2 cache initialization routine take a look at Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide, Part 2 page B.155ff for reference. i'll be calling the registers by the names given in the reference. according to my understanding the following steps have to be taken for a generic P6 L2 cache algorithm: 1. read IA32_PLATFORM_ID to obtain L2 Cache Latency and Clock Frequency Ratio (we can save Platform Id, too. we'll need it for the microcode update!) 2. read BBL_CR_CTL3 and check L2 Hardware Disable. if set the L2 cache is hardware disabled. nothing we can do about that, so just exit the routine. 3. set L2 Physical Address Range, L2 Enabled, L2 Cache Latency; clear L2 Configured and write BBL_CR_CTL3 back 4. fill the L2 cache with 0 and mark the whole cache invalid by using BBL_CR_ADDR, BBL_CR_D[0:3], BBL_CR_CTL and the table pointer(s) from query_cache_size() 5. read BBL_CR_CTL3, set L2 Configured and write BBL_CR_CTL3 back 6. done :) unanswered questions: - what happens if there's more than one L2 cache type found? shouldn't happen on the P6 architecture, but what about Core/Core2/Nehalem? - L2 cache pointer array in cpu.h has a fixed size of 8. on the P6 architecture we would only need one pointer because they only have one L2 cache array per core. not sure what we need for Core/Core2/Nehalem. the routines writing to the array (in query_cache_size()) don't check for any boundaries. this is potentially dangerous. is there a need to care about this? - is there a default value for L2 Physical Address Range? 4GB? - what about L2 ECC? i've no idea how it's intended to work. - some intel cpus support verbose processor identification strings (like Intel(R) Pentium(R) 4 CPU 1500MHz) others use a brand index table from which a verbose identification string can be build. do we need this? we could also display family, model, stepping and some additional information (cache size, cache speed and cpu core speed). should we display anything at all? - is there a need to know the cpu core multiplier and the system bus frequency? they are on EBL_CR_POWERON. - what about L1 cache? do we need to know its size to display it? what about L3 cache? i've currently no information on configuring L3 cache. what i currently need: - values of msr IA32_PLATFORM_ID, EBL_CR_POWERON and BBL_CR_CTL3 when booted with coreboot (e.g. untouched). does inteltool support dumping msrs? Uwe, can you report back with those values? anyone with L2/L3 cache register information on anything newer than the intel P6 architecture? i guess there's a document on L2/L3 cache detection and init available from intel. at least if you are AWARD/Phoenix or AMI. /* * (C) 2009 Holger Hesselbarth */ #include <config_intel.h> #include <identify_cpu.h> #include <msr.h> #include <cpu.h> static struct _cache_entry L2_cache_table[] = { { 0x21, 256, 8, 64, 1}, { 0x41, 128, 4, 32, 1}, { 0x42, 256, 4, 32, 1}, { 0x43, 512, 4, 32, 1}, { 0x44, 1024, 4, 32, 1}, { 0x45, 2048, 4, 32, 1}, { 0x48, 3072, 12, 64, 1}, { 0x49, 4096, 16, 64, 1}, /* L3 cache for Intel Xeon MP (family 0Fh, model 06h) */ { 0x4E, 6144, 24, 64, 1}, { 0x78, 1024, 4, 64, 1}, { 0x79, 128, 8, 64, 2}, { 0x7A, 256, 8, 64, 2}, { 0x7B, 512, 8, 64, 2}, { 0x7C, 1024, 8, 64, 2}, { 0x7D, 2048, 8, 64, 1}, { 0x7F, 512, 2, 64, 1}, { 0x80, 512, 8, 64, 1}, { 0x82, 256, 8, 32, 1}, { 0x83, 512, 8, 64, 1}, { 0x84, 1024, 8, 64, 1}, { 0x85, 2048, 8, 64, 1}, { 0x86, 512, 4, 64, 1}, { 0x87, 1024, 8, 64, 1}, { 0, 0, 0, 0, 0 } }; static void configure_cpu(struct cpu_data *cpu) { switch(cpu->family) { /** * Pentium * Pentium MMX * Pentium Mobile * Pentium MMX Mobile (Tillamook) */ case 0x05 : break; case 0x06 : /* get cache types and sizes */ query_cache_size(cpu); /* everything before Core technology */ if(cpu->efamily == 0) { /* do model specific initialization */ switch(cpu->model) { /** * Pentium Pro */ case 0x00 : case 0x01 : /* omitted break intended */ /** * Pentium II (Klamath) */ case 0x03 : /* omitted break intended */ /** * Pentium II (Deschutes) * Pentium II Xeon (Drake) * Mobile Pentium II (Dixon) * Celeron (Covington) */ case 0x05 : /* omitted break intended */ /** * Mobile Pentium II * Celeron (Mendochino) * Mobile Celeron (Mendochino) */ case 0x06 : /* omitted break intended */ /** * Pentium III (Katmai) * Pentium III Xeon (Tanner) */ case 0x07 : /* omitted break intended */ /** * Pentium III (Coppermine) * Pentium III-M (Coppermine) * Pentium III Xeon (Coppermine) * Mobile Pentium III * Celeron (Coppermine) */ case 0x08 : /* initialize L2 cache */ if(cpu->L2[0]->descriptor != 0) { initialize_P6_L2_cache(cpu); } break; /** * Pentium M (Banias) * Celeron M (Banias) */ case 0x09 : /* initialize_M_L2_cache */ break; /** * Pentium III Xeon (Cascades) */ case 0x0A : /* omitted break intended */ /** * Pentium III (Tualatin) * Pentium III-S (Tualatin) * Mobile Pentium III (Tualatin) * Celeron (Tualatin) */ case 0x0B : /* initialize L2 cache */ if(cpu->L2[0]->descriptor != 0) { initialize_P6_L2_cache(cpu); } break; /** * Pentium M (Dothan) * Celeron M (Dothan) */ case 0x0D : /* initialize_M_L2_cache */ break; /** * Unknown model */ default : break; } } /* everything based on Core technology and later */ else { /* do model specific initialization */ switch(((cpu->emodel << 4) & cpu->model)) { /** * Core Solo * Core Duo */ case 0x0E : /* initialize_Core_L2_cache */ break; /** * Xeon Processor 3000, 3200, 5100, 5300, 7300 * Core 2 Quad * Core 2 Extreme * Core 2 Duo * Pentium dual-core */ case 0x0F : /* initialize_Core2_L2_cache */ break; /** * Xeon Processor 5200, 5400 * Core 2 Quad Q9650 */ case 0x17 : /* initialize_Core_L2_cache */ break; /** * Core i7 */ case 0x1A : /* initialize_Nehalem_L2_cache */ break; /** * Atom */ case 0x1C : /* initialize_Atom_L2_cache */ break; /** * Xeon Processor MP 7400 */ case 0x1D : /* initialize_???_L2_cache */ break; /** * Unknown model */ default : break; } } break; /** * Itanium */ case 0x07 : break; /** * all processors base on the Pentium 4 core */ case 0x0F : break; /* Unknown cpu family */ default : break; } return; }; static void query_cache_size(struct cpu_data *cpu) { unsigned char i, j, k, m; unsigned int reg[4]; unsigned char iterations; unsigned char cache_id; /* get cache and tlb information */ if(cpu->maxbi >= 2) { cpuid(CPU_CACHE_INF, &reg[0], &reg[1], &reg[2], &reg[3]); /* extract how often to call cpuid with CPU_CACHE_INF */ iterations = (unsigned char)(reg[0] & 0xFF); m = 0; for(i=0; i < iterations; i++) { cpuid(CPU_CACHE_INF, &reg[0], &reg[1], &reg[2], &reg[3]); /* bit 31 set means invalid register */ for(j=0; j<3; j++) { if(reg[j] & 0x80000000) { /* clear invalid register */ reg[j] = 0; } } /* iterate through all cache identifiers */ for(j=1; j<16; j++) { cache_id = (reg[j / 4] >> (unsigned int)(8 * (j % 4))); if(cache_id != 0) { k = 0; /* L2 cache */ while(L2_cache_table[k].descriptor != 0) { if(L2_cache_table[k].descriptor == cache_id) { cpu->L2[m] = &L2_cache_table[k]; m++; } k++; } } } } } return; }; static void initialize_P6_L2_cache(struct cpu_data *cpu) { unsigned char L2_cache_latency; }; /* * (C) 2001 Dave Jones. * 2009 adapted for coreboot by Holger Hesselbarth * * Licensed under the terms of the GNU GPL License version 2. */ static int flag_is_changeable_p(unsigned long flag) { unsigned long f1, f2; __asm__ volatile("pushf\n\t" "pushf\n\t" "pop %0\n\t" "mov %0,%1\n\t" "xor %2,%0\n\t" "push %0\n\t" "popf\n\t" "pushf\n\t" "pop %0\n\t" "popf\n\t" : "=&r" (f1), "=&r" (f2) : "ir" (flag)); return ((f1^f2) & flag) != 0; } int check_cpuid(void) { return flag_is_changeable_p(0x200000); } /* * (C) 2009 Holger Hesselbarth */ #include <cpu.h> #include <identify_cpu.h> static void identify_cpu(struct cpu_data *cpu) { /* check if cpuid is supported */ if((check_cpuid()) == 0) { // TODO : check if this is a Cyrix cpu with cpuid disabled return; } /* gather basic cpu information */ get_basic_cpu_information(cpu); /* gather extended cpu information */ get_extended_cpu_information(cpu); return; }; static void get_basic_cpu_information(struct cpu_data *cpu) { unsigned int maxbi, vendor; unsigned int eax, ebx, ecx, edx; /* get basic cpu information */ cpuid(CPU_BASIC_INF, &maxbi, &vendor, NULL, NULL); cpu->maxbi = (maxbi & 0x0000FFFF ); /* high-order word is non-zero on some Cyrix cpus */ if(cpu->maxbi < 1) { return; } /* get family, model, stepping and feature flags */ cpuid((CPU_BASIC_INF + 1), &eax, &ebx, &ecx, &edx); cpu->stepping = (eax & 0x0F); cpu->model = ((eax >> 4) & 0x0F); cpu->family = ((eax >> 8) & 0x0F); cpu->ecx_bi_flags = ecx; cpu->edx_bi_flags = edx; /* get more basic cpu information based on vendor */ switch(vendor) { // TODO : could also be GenuineTMx86 for Transmeta CPUs case 0x756e6547 : /* uneG */ cpu->vendor = X86_VENDOR_INTEL; cpu->type = ((eax >> 12) & 0x03); if(cpu->family == (unsigned int)0x0F) { cpu->emodel = ((eax >> 16) & 0x0F); cpu->efamily = ((eax >> 20) & 0xFF); } else if(cpu->family == (unsigned int)0x06) { cpu->emodel = ((eax >> 16) & 0x0F); } cpu->brand = (ebx & 0xFF); cpu->clflush = ((ebx >> 8) & 0xFF); cpu->apicid = ((ebx >> 24) & 0xFF); break; case 0x68747541 : /* thuA */ cpu->vendor = X86_VENDOR_AMD; // TODO : check for extended family & model break; case 0x69727943 : /* iryC */ cpu->vendor = X86_VENDOR_CYRIX; break; case 0x746e6543 : /* tneC */ cpu->vendor = X86_VENDOR_CENTAUR; break; // TODO : add more cpu makers default : cpu->vendor = X86_VENDOR_UNKNOWN; break; } return; }; static void get_extended_cpu_information(struct cpu_data *cpu) { /* get extended cpu information * the IDT WinChip C6 needs a special treatment */ if((cpu->vendor == X86_VENDOR_CENTAUR) && (cpu->model == 4)) { cpuid(CPU_C6_EXT_INF, &(cpu->maxei), NULL, NULL, NULL); } else { cpuid(CPU_EXT_INF, &(cpu->maxei), NULL, NULL, NULL); } return; }; #ifndef CPU_CPU_H #define CPU_CPU_H //#include <arch/cpu.h> #define CPU_NAME_LEN 80 #define L2_CACHE_ENTRIES 8 struct _cache_entry { unsigned char descriptor; unsigned int size; unsigned char associativity; unsigned int line_size; unsigned char lines_per_sector; }; struct cpu_data { struct cpudata *next; unsigned char number; unsigned char vendor; unsigned char family; unsigned char model; unsigned char type; unsigned char stepping; unsigned char efamily; unsigned char emodel; unsigned char platform_id; unsigned char maxbi; unsigned int maxei; unsigned int ecx_bi_flags; unsigned int edx_bi_flags; struct _cache_entry *L2[L2_CACHE_ENTRIES]; unsigned int cachesize_L1_I; unsigned int cachesize_L1_D; unsigned int cachesize_L2; unsigned int cachesize_L3; unsigned int cachesize_trace; char name[CPU_NAME_LEN]; unsigned int nr_cores; unsigned int nr_logical; /* Intel specific bits */ unsigned char brand; unsigned char clflush; unsigned char apicid; /* Intel Pentium III serial number (PSN) */ unsigned int serialno[2]; }; struct device; struct bus; void cpu_initialize(void); void initialize_cpus(struct bus *cpu_bus); #define __cpu_driver __attribute__ ((used,__section__(".rodata.cpu_driver"))) /** start of compile time generated pci driver array */ extern struct cpu_driver cpu_drivers[]; /** end of compile time generated pci driver array */ extern struct cpu_driver ecpu_drivers[]; #endif /* CPU_CPU_H */ #ifndef CPU_X86_CONFIG_INTEL_H #define CPU_X86_CONFIG_INTEL_H #include <cpu.h> #define CPU_CACHE_INF 0x00000002 #define IA32_PLATFORM_ID 0x00000017 #define EBL_CR_POWERON 0x0000002A #define BBL_CR_D0 0x00000088 #define BBL_CR_D1 0x00000089 #define BBL_CR_D2 0x0000008A #define BBL_CR_D3 0x0000008B #define BBL_CR_ADDR 0x00000116 #define BBL_CR_CTL 0x00000119 #define BBL_CR_TRIG 0x0000011A #define BBL_CR_BUSY 0x0000011B #define BBL_CR_CTL3 0x0000011E static void configure_cpu(struct cpu_data *cpu); static void initialize_P6_L2_cache(struct cpu_data *cpu); static void query_cache_size(struct cpu_data *cpu); #endif /* CPU_X86_CONFIG_INTEL_H */ #ifndef CPU_X86_IDENTIFY_CPU_H #define CPU_X86_IDENTIFY_CPU_H #include <cpu.h> #define CPU_BASIC_INF 0x00000000 #define CPU_EXT_INF 0x80000000 #define CPU_C6_EXT_INF 0xC0000000 extern int check_cpuid(void); static void identify_cpu(struct cpu_data *cpu); static void get_basic_cpu_information(struct cpu_data *cpu); static void get_extended_cpu_information(struct cpu_data *cpu); #endif /* CPU_X86_IDENTIFY_CPU_H */

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flashrom on intel dg33tl
by Andriy Gapon 02 Feb '09

02 Feb '09

Below is output of flashrom -V. It couldn't find the flash chip. This is ICH9 (G33) chipset. There is one WARNING and one FAILED messages. Calibrating delay loop... 257M loops per second, 100 myus = 196 us. OK. No coreboot table found. Found chipset "Intel ICH9R", enabling flash write... BIOS Lock Enable: enabled, BIOS Write Enable: disabled, BIOS_CNTL is 0xa tried to set 0xdc to 0xb on Intel ICH9R failed (WARNING ONLY) Root Complex Register Block address = 0xfed1c000 GCS = 0xc01444: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x1 (SPI) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3800 0x00: 0x0035 (HSFS) FLOCKDN 1, FDV 1, FDOPSS 0, SCIP 0, BERASE 0, AEL 0, FCERR 0, FDONE 0 0x50: 0x00000a0b (FRAP) BMWAG 0, BMRAG 0, BRWA 10, BRRA 11 0x54: 0x00000000 (FREG0) 0x58: 0x00ff0035 (FREG1) 0x5C: 0x00340003 (FREG2) 0x60: 0x00020001 (FREG3) 0x64: 0x00000fff (FREG4) 0x74: 0x00000000 (PR0) 0x78: 0x00000000 (PR1) 0x7C: 0x00000000 (PR2) 0x80: 0x00000000 (PR3) 0x84: 0x00000000 (PR4) 0xB0: 0x00000000 (FDOC) SPI Read Configuration: prefetching enabled, caching enabled, FAILED! Probing for AMD Am29F002(N)BB, 256 KB: probe_jedec: id1 0xf9, id2 0x63, id1 parity violation Probing for AMD Am29F002(N)BT, 256 KB: probe_jedec: id1 0xf9, id2 0x63, id1 parity violation Probing for AMD Am29F016D, 2048 KB: probe_29f040b: id1 0xff, id2 0xff Probing for AMD Am29F040B, 512 KB: probe_29f040b: id1 0x3, id2 0x55 Probing for AMD Am29LV040B, 512 KB: probe_29f040b: id1 0x3, id2 0x55 Probing for ASD AE49F2008, 256 KB: probe_jedec: id1 0xf9, id2 0x63, id1 parity violation Probing for Atmel AT29C020, 256 KB: probe_jedec: id1 0xf9, id2 0x63, id1 parity violation Probing for Atmel AT29C040A, 512 KB: probe_jedec: id1 0x3, id2 0x55, id1 parity violation Probing for Atmel AT49F002(N), 256 KB: probe_jedec: id1 0xf9, id2 0x63, id1 parity violation Probing for Atmel AT49F002(N)T, 256 KB: probe_jedec: id1 0xf9, id2 0x63, id1 parity violation Probing for Atmel AT25DF321, 4096 KB: Programming OPCODES... done RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for AMIC A25L40P, 512 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for AMIC A29002B, 256 KB: probe_29f002: id1 0xf9, id2 0x63 Probing for AMIC A29002T, 256 KB: probe_29f002: id1 0xf9, id2 0x63 Probing for AMIC A29040B, 512 KB: probe_29f040b: id1 0x3, id2 0x55 Probing for AMIC A49LF040A, 512 KB: probe_jedec: id1 0x3, id2 0x55, id1 parity violation Probing for EMST F49B002UA, 256 KB: probe_jedec: id1 0xf9, id2 0x63, id1 parity violation Probing for EON EN29F002(A)(N)B, 256 KB: probe_jedec: id1 0xf9, id2 0x63, id1 parity violation Probing for EON EN29F002(A)(N)T, 256 KB: probe_jedec: id1 0xf9, id2 0x63, id1 parity violation Probing for Fujitsu MBM29F004BC, 512 KB: probe_jedec: id1 0x3, id2 0x55, id1 parity violation Probing for Fujitsu MBM29F004TC, 512 KB: probe_jedec: id1 0x3, id2 0x55, id1 parity violation Probing for Fujitsu MBM29F400BC, 512 KB: probe_m29f400bt: id1 0x3, id2 0x75 Probing for Fujitsu MBM29F400TC, 512 KB: probe_m29f400bt: id1 0x3, id2 0x75 Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0x3, id2 0x55 Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for Macronix MX25L512, 64 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Macronix MX25L1005, 128 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Macronix MX25L2005, 256 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Macronix MX25L4005, 512 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Macronix MX25L8005, 1024 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Macronix MX25L1605, 2048 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Macronix MX25L3205, 4096 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Macronix MX25L6405, 8192 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Macronix MX29F002B, 256 KB: probe_29f002: id1 0xf9, id2 0x63 Probing for Macronix MX29F002T, 256 KB: probe_29f002: id1 0xf9, id2 0x63 Probing for Numonyx M25PE10, 128 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Numonyx M25PE20, 256 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Numonyx M25PE40, 256 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Numonyx M25PE80, 1024 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Numonyx M25PE16, 2048 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for PMC Pm25LV010, 128 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for PMC Pm25LV016B, 2048 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for PMC Pm25LV020, 256 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for PMC Pm25LV040, 512 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for PMC Pm25LV080B, 1024 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for PMC Pm25LV512, 64 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for PMC Pm49FL002, 256 KB: probe_jedec: id1 0xf9, id2 0x63, id1 parity violation Probing for PMC Pm49FL004, 512 KB: probe_jedec: id1 0x3, id2 0x55, id1 parity violation Probing for Sharp LHF00L04, 1024 KB: probe_lhf00l04: id1 0xff, id2 0xff Probing for Spansion S25FL016A, 2048 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for SST SST25VF016B, 2048 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for SST SST25VF040B, 512 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for SST SST28SF040A, 512 KB: probe_28sf040: id1 0x3, id2 0x55 Probing for SST SST29EE010, 128 KB: probe_jedec: id1 0x32, id2 0x0 Probing for SST SST29LE010, 128 KB: probe_jedec: id1 0x32, id2 0x0 Probing for SST SST29EE020A, 256 KB: probe_jedec: id1 0xf9, id2 0x63, id1 parity violation Probing for SST SST29LE020, 256 KB: probe_jedec: id1 0xf9, id2 0x63, id1 parity violation Probing for SST SST39SF010A, 128 KB: probe_jedec: id1 0x32, id2 0x0 Probing for SST SST39SF020A, 256 KB: probe_jedec: id1 0xf9, id2 0x63, id1 parity violation Probing for SST SST39SF040, 512 KB: probe_jedec: id1 0x3, id2 0x55, id1 parity violation Probing for SST SST39VF512, 64 KB: probe_jedec: id1 0xeb, id2 0xce, id1 parity violation Probing for SST SST39VF010, 128 KB: probe_jedec: id1 0x32, id2 0x0 Probing for SST SST39VF020, 256 KB: probe_jedec: id1 0xf9, id2 0x63, id1 parity violation Probing for SST SST39VF040, 512 KB: probe_jedec: id1 0x3, id2 0x55, id1 parity violation Probing for SST SST49LF002A/B, 256 KB: probe_jedec: id1 0xf9, id2 0x63, id1 parity violation Probing for SST SST49LF003A/B, 384 KB: probe_jedec: id1 0x81, id2 0x7c, id1 parity violation Probing for SST SST49LF004A/B, 512 KB: probe_jedec: id1 0x3, id2 0x55, id1 parity violation Probing for SST SST49LF004C, 512 KB: probe_49lfxxxc: id1 0x3, id2 0x55 Probing for SST SST49LF008A, 1024 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for SST SST49LF008C, 1024 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST SST49LF016C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST SST49LF020A, 256 KB: probe_jedec: id1 0xf9, id2 0x63, id1 parity violation Probing for SST SST49LF040, 512 KB: probe_jedec: id1 0x3, id2 0x55, id1 parity violation Probing for SST SST49LF040B, 512 KB: probe_jedec: id1 0x3, id2 0x55, id1 parity violation Probing for SST SST49LF080A, 1024 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for SST SST49LF160C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for ST M25P05-A, 64 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for ST M25P10-A, 128 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for ST M25P20, 256 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for ST M25P40, 512 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for ST M25P40-old, 512 KB: RDID returned 1f 45 01. Probing for ST M25P80, 1024 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for ST M25P16, 2048 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for ST M25P32, 4096 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for ST M25P64, 8192 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for ST M25P128, 16384 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for ST M29F002B, 256 KB: probe_jedec: id1 0xf9, id2 0x63, id1 parity violation Probing for ST M29F002T/NT, 256 KB: probe_jedec: id1 0xf9, id2 0x63, id1 parity violation Probing for ST M29F040B, 512 KB: probe_29f040b: id1 0x3, id2 0x55 Probing for ST M29F400BT, 512 KB: probe_m29f400bt: id1 0x3, id2 0x75 Probing for ST M29W010B, 128 KB: probe_jedec: id1 0x32, id2 0x0 Probing for ST M29W040B, 512 KB: probe_jedec: id1 0x3, id2 0x55, id1 parity violation Probing for ST M50FLW040A, 512 KB: probe_stm50flw0x0x: id1 0x3, id2 0x55 Probing for ST M50FLW040B, 512 KB: probe_stm50flw0x0x: id1 0x3, id2 0x55 Probing for ST M50FLW080A, 1024 KB: probe_stm50flw0x0x: id1 0xff, id2 0xff Probing for ST M50FLW080B, 1024 KB: probe_stm50flw0x0x: id1 0xff, id2 0xff Probing for ST M50FW002, 256 KB: probe_49lfxxxc: id1 0xf9, id2 0x63 Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0x3, id2 0x55 Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50LPW116, 2048 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for SyncMOS S29C31004T, 512 KB: probe_jedec: id1 0x3, id2 0x55, id1 parity violation Probing for SyncMOS S29C51001T, 128 KB: probe_jedec: id1 0x32, id2 0x0 Probing for SyncMOS S29C51002T, 256 KB: probe_jedec: id1 0xf9, id2 0x63, id1 parity violation Probing for SyncMOS S29C51004T, 512 KB: probe_jedec: id1 0x3, id2 0x55, id1 parity violation Probing for Winbond W25x10, 128 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Winbond W25x20, 256 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Winbond W25x40, 512 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Winbond W25x80, 1024 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Winbond W29C011, 128 KB: probe_jedec: id1 0x32, id2 0x0 Probing for Winbond W29C020C, 256 KB: probe_jedec: id1 0xf9, id2 0x63, id1 parity violation Probing for Winbond W29C040P, 512 KB: probe_jedec: id1 0x3, id2 0x55, id1 parity violation Probing for Winbond W29EE011, 128 KB: === Probing disabled for Winbond W29EE011 because the probing sequence puts the AMIC A49LF040A in a funky state. Use 'flashrom -c W29EE011' if you have a board with this chip. === Probing for Winbond W39V040A, 512 KB: probe_jedec: id1 0x3, id2 0x55, id1 parity violation Probing for Winbond W39V040B, 512 KB: probe_jedec: id1 0x3, id2 0x55, id1 parity violation Probing for Winbond W39V040C, 512 KB: probe_w39v040c: id1 0x3, id2 0x55, id1 parity violation Probing for Winbond W39V040FA, 512 KB: probe_jedec: id1 0x3, id2 0x55, id1 parity violation Probing for Winbond W39V080A, 1024 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for Winbond W49F002U, 256 KB: probe_jedec: id1 0xf9, id2 0x63, id1 parity violation Probing for Winbond W49V002A, 256 KB: probe_jedec: id1 0xf9, id2 0x63, id1 parity violation Probing for Winbond W49V002FA, 256 KB: probe_jedec: id1 0xf9, id2 0x63, id1 parity violation Probing for Winbond W39V080FA, 1024 KB: probe_winbond_fwhub: vid 0xff, did 0xff Probing for Winbond W39V080FA (dual mode), 512 KB: probe_winbond_fwhub: vid 0x3, did 0x55 Probing for EON unknown EON SPI chip, 0 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Macronix unknown Macronix SPI chip, 0 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for PMC unknown PMC SPI chip, 0 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for SST unknown SST SPI chip, 0 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for ST unknown ST SPI chip, 0 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 No EEPROM/flash device found. If you know which flash chip you have, and if this version of flashrom supports a similar flash chip, you can try to force read your chip. Run: flashrom -f -r -c similar_supported_flash_chip filename Note: flashrom can never write when the flash chip isn't found automatically. -- Andriy Gapon

5 10

[PATCH] Fix flashrom init for VT8237S
by Rudolf Marek 01 Feb '09

01 Feb '09

Hello, Following patch fixes VIA SPI (VT8237S). It needs to have opcodes initialized same way as ICH7. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Oh btw there is some logic problem with the flashrom -E. The spi_chip_erase_c7 gets called for mine chip: result = spi_disable_blockprotect(); if (result) { printf_debug("spi_disable_blockprotect failed\n"); return result; } result = spi_write_enable(); if (result) { printf_debug("spi_write_enable failed\n"); return result; } But it will fail sending spi_write_enable() because: int spi_write_enable() { const unsigned char cmd[JEDEC_WREN_OUTSIZE] = { JEDEC_WREN }; /* Send WREN (Write Enable) */ return spi_command(sizeof(cmd), 0, cmd, NULL); } And final fail: /* unknown / not programmed command */ if (opcode_index == -1) { printf_debug("Invalid OPCODE 0x%02x\n", cmd); return 1; } Because its just a prefix opcode. And prefix opcodes are not checked. Question is now what to do. Silently complete command the spi_write_enable, when we find the opcode in prefix opcode? The prefix opcode should get executed with the prefix automatically. Rudolf

3 6

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coreboot January 2009