coreboot September 2008

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[FILO] #8: 'terminal console serial' says VGA console is disabled, but it's not.
by FILO 30 Sep '08

30 Sep '08

#8: 'terminal console serial' says VGA console is disabled, but it's not. ------------------------------------+--------------------------------------- Reporter: hawke(a)hawkesnest.net | Owner: somebody Type: defect | Status: new Priority: trivial | Milestone: Component: FILO | Version: Keywords: | Dependencies: Patchstatus: there is no patch | ------------------------------------+--------------------------------------- Running the filo command 'terminal console serial' will print: Serial console terminal enabled. VGA console terminal disabled. Flags: But the VGA console still works. It should probably not print anything, or indicate any changes from the previous status. -- Ticket URL: <http://tracker.coreboot.org/trac/filo/ticket/8> FILO <http://www.coreboot.org/FILO>

1 2

r3622 - in trunk/coreboot-v2: src/mainboard/asus/a8n_e targets/asus/a8n_e
by svn＠coreboot.org 30 Sep '08

30 Sep '08

Author: uwe Date: 2008-09-30 17:02:40 +0200 (Tue, 30 Sep 2008) New Revision: 3622 Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/Config.lb trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb trunk/coreboot-v2/src/mainboard/asus/a8n_e/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/asus/a8n_e/get_bus_conf.c trunk/coreboot-v2/src/mainboard/asus/a8n_e/irq_tables.c trunk/coreboot-v2/src/mainboard/asus/a8n_e/mptable.c trunk/coreboot-v2/targets/asus/a8n_e/Config.lb Log: Coding-style fixes and simplifications for the ASUS A8N-E (trivial). The only non-cosmetic change is s/A8NE/A8N-E/ for the board name. This is build-tested by me. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8n_e/Config.lb 2008-09-30 06:13:54 UTC (rev 3621) +++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/Config.lb 2008-09-30 15:02:40 UTC (rev 3622) @@ -21,10 +21,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## if USE_FAILOVER_IMAGE default ROM_SECTION_SIZE = FAILOVER_SIZE default ROM_SECTION_OFFSET = (ROM_SIZE - FAILOVER_SIZE) @@ -37,27 +33,12 @@ default ROM_SECTION_OFFSET = 0 end end - -## -## Compute the start location and size size of the coreboot bootloader. -## default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot ROM. -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can be cached to speed up coreboot -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2 (here 64 Kbyte) -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE = (64 * 1024) - +default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) +# XIP_ROM_SIZE must be a power of 2. +# XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE. +default XIP_ROM_SIZE = 64 * 1024 if USE_FAILOVER_IMAGE default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) else @@ -67,28 +48,12 @@ default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) end end - arch i386 end - -## -## Build the objects we have code for in this directory. -## - driver mainboard.o - -#dir /drivers/ati/ragexl - # Needed by irq_tables and mptable and acpi_tables. object get_bus_conf.o - -if HAVE_MP_TABLE - object mptable.o -end - -if HAVE_PIRQ_TABLE - object irq_tables.o -end - +if HAVE_MP_TABLE object mptable.o end +if HAVE_PIRQ_TABLE object irq_tables.o end if USE_DCACHE_RAM if CONFIG_USE_INIT makerule ./auto.o @@ -104,10 +69,6 @@ end end end - -## -## Build our 16 bit and 32 bit coreboot entry code. -## if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/entry16.inc @@ -119,19 +80,13 @@ ldscript /cpu/x86/16bit/entry16.lds end end - mainboardinit cpu/x86/32bit/entry32.inc - if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds ldscript /cpu/amd/car/cache_as_ram.lds end end - -## -## Build our reset vector (this is where coreboot is entered). -## if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -149,22 +104,14 @@ ldscript /cpu/x86/32bit/reset32.lds end end - if USE_DCACHE_RAM else - ### Should this be in the northbridge code? mainboardinit arch/i386/lib/cpu_reset.inc end - -## -## Include an ID string (for safe flashing). -## +# Include an ID string (for safe flashing). mainboardinit southbridge/nvidia/ck804/id.inc ldscript /southbridge/nvidia/ck804/id.lds - -## -## ROMSTRAP table for CK804 -## +# ROMSTRAP table for CK804. if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE mainboardinit southbridge/nvidia/ck804/romstrap.inc @@ -176,20 +123,9 @@ ldscript /southbridge/nvidia/ck804/romstrap.lds end end - if USE_DCACHE_RAM - ## - ## Setup Cache-As-Ram - ## mainboardinit cpu/amd/car/cache_as_ram.inc end - - -### -### This is the early phase of coreboot startup. -### Things are delicate and we test to see if we should -### failover to another image. -### if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE if USE_DCACHE_RAM @@ -203,14 +139,6 @@ end end end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## if USE_DCACHE_RAM if CONFIG_USE_INIT initobject auto.o @@ -218,10 +146,6 @@ mainboardinit ./auto.inc end end - -## -## Include the secondary configuration files -## if CONFIG_CHIP_NAME config chip.h end Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb 2008-09-30 06:13:54 UTC (rev 3621) +++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb 2008-09-30 15:02:40 UTC (rev 3622) @@ -80,7 +80,6 @@ uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses HW_MEM_HOLE_SIZEK - uses USE_DCACHE_RAM uses DCACHE_RAM_BASE uses DCACHE_RAM_SIZE @@ -89,233 +88,81 @@ uses CONFIG_AP_CODE_IN_CAR uses MEM_TRAIN_SEQ uses WAIT_BEFORE_CPUS_INIT - uses ENABLE_APIC_EXT_ID uses APIC_ID_OFFSET uses LIFT_BSP_APIC_ID - uses CONFIG_PCI_64BIT_PREF_MEM - uses HT_CHAIN_UNITID_BASE uses HT_CHAIN_END_UNITID_BASE uses SB_HT_CHAIN_ON_BUS0 uses SB_HT_CHAIN_UNITID_OFFSET_ONLY - uses CONFIG_LB_MEM_TOPK - -## ROM_SIZE is the size of boot ROM that this board will use. -## ---> 512 Kbytes -default ROM_SIZE=(512*1024) - -## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use -## -default FALLBACK_SIZE=(252*1024) - -#FAILOVER: 4K -default FAILOVER_SIZE=(4*1024) - -### -### Build options -### - -## -## Build code for the fallback boot -## -default HAVE_FALLBACK_BOOT=1 -default HAVE_FAILOVER_BOOT=1 - -## -## Build code to reset the motherboard from coreboot -## -default HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=13 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default HAVE_MP_TABLE=1 - -## -## Build code to export a CMOS option table -## -default HAVE_OPTION_TABLE=1 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=2 -default CONFIG_MAX_PHYSICAL_CPUS=1 -default CONFIG_LOGICAL_CPUS=1 - -#1G memory hole -default HW_MEM_HOLE_SIZEK=0x100000 - -##HT Unit ID offset, default is 1, the typical one -default HT_CHAIN_UNITID_BASE=0 - -##real SB Unit ID, default is 0x20, mean dont touch it at last -#default HT_CHAIN_END_UNITID_BASE=0x10 - -#make the SB HT chain on bus 0, default is not (0) -default SB_HT_CHAIN_ON_BUS0=2 - -##only offset for SB chain?, default is yes(1) -default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 - -#BTEXT Console -#default CONFIG_CONSOLE_BTEXT=1 - -#VGA Console -default CONFIG_CONSOLE_VGA=1 -default CONFIG_PCI_ROM_RUN=1 - -## -## enable CACHE_AS_RAM specifics -## -default USE_DCACHE_RAM=1 -#default DCACHE_RAM_BASE=0xcf000 -#default DCACHE_RAM_SIZE=0x1000 -default DCACHE_RAM_BASE=0xc8000 -default DCACHE_RAM_SIZE=0x08000 -default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 -default CONFIG_USE_INIT=0 - -default CONFIG_AP_CODE_IN_CAR=0 -default MEM_TRAIN_SEQ=2 -default WAIT_BEFORE_CPUS_INIT=0 - -## APIC stuff -#default ENABLE_APIC_EXT_ID=0 -#default APIC_ID_OFFSET=0x10 -#default LIFT_BSP_APIC_ID=0 - - -#default CONFIG_PCI_64BIT_PREF_MEM=1 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default MAINBOARD_PART_NUMBER="A8NE" -default MAINBOARD_VENDOR="ASUS" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2891 - -### -### coreboot layout values -### - -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = (64*1024) -#65536 - -## -## Use a small 8K stack -## -default STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -#efault USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE ) - -## -## Coreboot C code runs at this location in RAM -## -default _RAMBASE=0x00004000 - -## -## Load the payload from the ROM -## +default ROM_SIZE = 512 * 1024 +default ROM_IMAGE_SIZE = 64 * 1024 +default FALLBACK_SIZE = 252 * 1024 +default FAILOVER_SIZE = 4 * 1024 +default HAVE_FALLBACK_BOOT = 1 +default HAVE_FAILOVER_BOOT = 1 +default HAVE_HARD_RESET = 1 +default HAVE_PIRQ_TABLE = 1 +default IRQ_SLOT_COUNT = 13 +default HAVE_MP_TABLE = 1 +default HAVE_OPTION_TABLE = 1 +# Move the default coreboot CMOS range off of AMD RTC registers. +default LB_CKS_RANGE_START = 49 +default LB_CKS_RANGE_END = 122 +default LB_CKS_LOC = 123 +# SMP support (only worry about 2 micro processors). +default CONFIG_SMP = 1 +default CONFIG_MAX_CPUS = 2 +default CONFIG_MAX_PHYSICAL_CPUS = 1 +default CONFIG_LOGICAL_CPUS = 1 +# 1G memory hole. +default HW_MEM_HOLE_SIZEK = 0x100000 +# HT Unit ID offset, default is 1, the typical one. +default HT_CHAIN_UNITID_BASE = 0 +# Real SB Unit ID, default is 0x20, mean don't touch it at last. +# default HT_CHAIN_END_UNITID_BASE = 0x10 +# Make the SB HT chain on bus 0, default is not (0). +default SB_HT_CHAIN_ON_BUS0 = 2 +# Only offset for SB chain?, default is yes(1). +default SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0 +# default CONFIG_CONSOLE_BTEXT = 1 # BTEXT console +default CONFIG_CONSOLE_VGA = 1 # For VGA console +default CONFIG_PCI_ROM_RUN = 1 # For VGA console +default USE_DCACHE_RAM = 1 +default DCACHE_RAM_BASE = 0xc8000 +default DCACHE_RAM_SIZE = 32 * 1024 +default DCACHE_RAM_GLOBAL_VAR_SIZE = 4 * 1024 +default CONFIG_USE_INIT = 0 +default CONFIG_AP_CODE_IN_CAR = 0 +default MEM_TRAIN_SEQ = 2 +default WAIT_BEFORE_CPUS_INIT = 0 +# default ENABLE_APIC_EXT_ID = 0 +# default APIC_ID_OFFSET = 0x10 +# default LIFT_BSP_APIC_ID = 0 +# default CONFIG_PCI_64BIT_PREF_MEM = 1 +default CONFIG_IOAPIC = 1 +default MAINBOARD_PART_NUMBER = "A8N-E" +default MAINBOARD_VENDOR = "ASUS" +default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x10f1 +default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x2891 +default STACK_SIZE = 8 * 1024 +default HEAP_SIZE = 16 * 1024 +# Only use the option table in a normal image. +default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE) +default _RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 +default CC = "$(CROSS_COMPILE)gcc -m32" +default HOSTCC = "gcc" +default CONFIG_GDB_STUB = 0 +default CONFIG_CONSOLE_SERIAL8250 = 1 +default TTYS0_BAUD = 115200 +default TTYS0_BASE = 0x3f8 +default TTYS0_LCS = 0x3 +default DEFAULT_CONSOLE_LOGLEVEL = 8 +default MAXIMUM_CONSOLE_LOGLEVEL = 8 +default MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON" -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 - -# Select the serial console base port -default TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -### End Options.lb end Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8n_e/cache_as_ram_auto.c 2008-09-30 06:13:54 UTC (rev 3621) +++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/cache_as_ram_auto.c 2008-09-30 15:02:40 UTC (rev 3622) @@ -76,17 +76,17 @@ static void memreset_setup(void) { - /* FIXME: Nothing to do? */ + /* Nothing to do. */ } static void memreset(int controllers, const struct mem_controller *ctrl) { - /* FIXME: Nothing to do? */ + /* Nothing to do. */ } static inline void activate_spd_rom(const struct mem_controller *ctrl) { - /* FIXME: Nothing to do? */ + /* Nothing to do. */ } static inline int spd_read_byte(unsigned device, unsigned address) @@ -123,8 +123,7 @@ /* LPC Positive Decode 0 */ dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0); - /* Serial 0, Serial 1 */ - dword |= (1 << 0) | (1 << 1); + dword |= (1 << 0) | (1 << 1); /* Serial 0, Serial 1 */ pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0, dword); } @@ -212,14 +211,11 @@ }; int needs_reset; - unsigned bsp_apicid = 0; - + unsigned nodes, bsp_apicid = 0; struct mem_controller ctrl[8]; - unsigned nodes; - if (bist == 0) { + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx); - } it8712f_24mhz_clkin(); it8712f_enable_serial(SERIAL_DEV, TTYS0_BASE); @@ -237,13 +233,12 @@ wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS==1 - // It is said that we should start core1 after all core0 launched + /* It is said that we should start core1 after all core0 launched. */ start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif needs_reset |= ht_setup_chains_x(); - needs_reset |= ck804_early_setup_x(); if (needs_reset) { @@ -254,7 +249,7 @@ allow_all_aps_stop(bsp_apicid); nodes = get_nodes(); - //It's the time to set ctrl now; + /* It's the time to set ctrl now. */ fill_mem_ctrl(nodes, ctrl, spd_addr); enable_smbus(); Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/get_bus_conf.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8n_e/get_bus_conf.c 2008-09-30 06:13:54 UTC (rev 3621) +++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/get_bus_conf.c 2008-09-30 15:02:40 UTC (rev 3622) @@ -26,13 +26,14 @@ #include <device/pci_ids.h> #include <string.h> #include <stdint.h> +#include <stdlib.h> #if CONFIG_LOGICAL_CPUS == 1 #include <cpu/amd/dualcore.h> #endif - #include <cpu/amd/amdk8_sysconf.h> -/* Global variables for MB layouts and these will be shared by irqtable, +/* + * Global variables for MB layouts and these will be shared by irqtable, * mptable and acpi_tables. */ /* busnum is default */ @@ -40,13 +41,23 @@ unsigned char bus_ck804[6]; unsigned apicid_ck804; -unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not - //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail - 0x0000ff0, //no HTIO for a8n_e +/* + * Here you only need to set value in pci1234 for HT-IO that could be installed + * or not. You may need to preset pci1234 for HT-IO board, please refer to + * src/northbridge/amd/amdk8/get_sblk_pci1234.c for details. + */ +unsigned pci1234x[] = { + 0x0000ff0, /* No HTIO for A8N-E */ }; -unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most - 0x20202020, //a8n_e has only one ht-chain + +/* + * HT Chain device num, actually it is unit id base of every ht device in + * chain, assume every chain only have 4 ht device at most. + */ +unsigned hcdnx[] = { + 0x20202020, /* A8N-E has only one ht-chain */ }; + unsigned bus_type[256]; extern void get_sblk_pci1234(void); @@ -55,19 +66,18 @@ void get_bus_conf(void) { - unsigned apicid_base; - + unsigned apicid_base, sbdn; device_t dev; - unsigned sbdn; int i, j; if (get_bus_conf_done == 1) - return; //do it only once + return; /* Do it only once. */ get_bus_conf_done = 1; - sysconf.hc_possible_num = sizeof(pci1234x) / sizeof(pci1234x[0]); - sysconf.hc_possible_num = sizeof(pci1234x) / sizeof(pci1234x[0]); + /* FIXME: Is this really needed twice? */ + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); for (i = 0; i < sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; @@ -75,18 +85,15 @@ get_sblk_pci1234(); - sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain + sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain sbdn = sysconf.sbdn; - for (i = 0; i < 6; i++) { + for (i = 0; i < 6; i++) bus_ck804[i] = 0; - } - - for (i = 0; i < 256; i++) { + for (i = 0; i < 256; i++) bus_type[i] = 0; - } - bus_type[0] = 1; //pci + bus_type[0] = 1; /* PCI */ bus_ck804[0] = (sysconf.pci1234[0] >> 16) & 0xff; @@ -107,9 +114,8 @@ } for (i = 2; i < 6; i++) { - dev = - dev_find_slot(bus_ck804[0], - PCI_DEVFN(sbdn + 0x0b + i - 2, 0)); + dev = dev_find_slot(bus_ck804[0], + PCI_DEVFN(sbdn + 0x0b + i - 2, 0)); if (dev) { bus_ck804[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); @@ -117,14 +123,12 @@ for (j = bus_ck804[i]; j < bus_isa; j++) bus_type[j] = 1; } else { - printk_debug - ("ERROR - could not find PCI %02x:%02x.0, using defaults\n", + printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804[0], sbdn + 0x0b + i - 2); bus_isa = bus_ck804[i - 1] + 1; } } -/*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS==1 apicid_base = get_apicid_base(3); #else Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/irq_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8n_e/irq_tables.c 2008-09-30 06:13:54 UTC (rev 3621) +++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/irq_tables.c 2008-09-30 15:02:40 UTC (rev 3622) @@ -21,8 +21,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* Documentation at: http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM */ - #include <console/console.h> #include <device/pci.h> #include <string.h> @@ -63,18 +61,14 @@ */ unsigned long write_pirq_routing_table(unsigned long addr) { - struct irq_routing_table *pirq; struct irq_info *pirq_info; - unsigned slot_num; - uint8_t *v; - - uint8_t sum = 0; + unsigned slot_num, sbdn; + uint8_t *v, sum = 0; int i; - unsigned sbdn; - /* get_bus_conf() will find out all bus num and apic that share with - * mptable.c and mptable.c + /* get_bus_conf() will find out all bus num and APIC that share with + * mptable.c and mptable.c. */ get_bus_conf(); sbdn = sysconf.sbdn; @@ -83,23 +77,19 @@ addr += 15; addr &= ~15; - /* This table must be betweeen 0xf0000 & 0x100000 */ + /* This table must be betweeen 0xf0000 & 0x100000. */ printk_info("Writing IRQ routing tables to 0x%x...", addr); pirq = (void *)(addr); - v = (uint8_t *) (addr); + v = (uint8_t *)(addr); pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - pirq->rtr_bus = bus_ck804[0]; pirq->rtr_devfn = ((sbdn + 9) << 3) | 0; - pirq->exclusive_irqs = 0x828; - pirq->rtr_vendor = 0x10de; pirq->rtr_device = 0x005c; - pirq->miniport_data = 0; memset(pirq->rfu, 0, sizeof(pirq->rfu)); @@ -107,32 +97,31 @@ pirq_info = (void *)(&pirq->checksum + 1); slot_num = 0; -//Slot1 PCIE 16x + /* Slot1 PCIE 16x */ write_pirq_info(pirq_info, bus_ck804[1], (0 << 3) | 0, 0x3, 0xdeb8, 0x4, 0xdeb8, 0x1, 0xdeb8, 0x2, 0xdeb8, 4, 0); pirq_info++; slot_num++; -//Slot2 PCIE 1x + /* Slot2 PCIE 1x */ write_pirq_info(pirq_info, bus_ck804[2], (0 << 3) | 0, 0x4, 0xdeb8, 0x1, 0xdeb8, 0x2, 0xdeb8, 0x3, 0xdeb8, 5, 0); pirq_info++; slot_num++; -//Slot3 PCIE 1x + /* Slot3 PCIE 1x */ write_pirq_info(pirq_info, bus_ck804[3], (0 << 3) | 0, 0x1, 0xdeb8, 0x2, 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 6, 0); pirq_info++; slot_num++; -//Slot4 PCIE 4x - write_pirq_info(pirq_info, bus_ck804[4], (0x4 << 3) | 0, - 0x2, 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 0x1, 0xdeb8, - 7, 0); + /* Slot4 PCIE 4x */ + write_pirq_info(pirq_info, bus_ck804[4], (0x4 << 3) | 0, 0x2, + 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 0x1, 0xdeb8, 7, 0); pirq_info++; slot_num++; -//Slot5 - 7 PCI + /* Slot5 - Slot7 PCI */ for (i = 0; i < 3; i++) { write_pirq_info(pirq_info, bus_ck804[5], (0 << (6 + i)) | 0, ((i + 0) % 4) + 1, 0xdeb8, @@ -143,47 +132,50 @@ slot_num++; } -//pci bridge + /* PCI bridge */ write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 9) << 3) | 0, 0x1, 0xdeb8, 0x2, 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 0, 0); pirq_info++; slot_num++; -//smbus + /* SMBus */ write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 1) << 3) | 0, 0x2, 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0); pirq_info++; slot_num++; -//usb + /* USB */ write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 2) << 3) | 0, 0x1, 0xdeb8, 0x2, 0xdeb8, 0, 0, 0, 0, 0, 0); pirq_info++; slot_num++; -//audio + /* Audio */ write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 4) << 3) | 0, 0x1, 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0); pirq_info++; slot_num++; -//sata + + /* SATA */ write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 7) << 3) | 0, 0x1, 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0); pirq_info++; slot_num++; -//sata + + /* SATA */ write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 8) << 3) | 0, 0x1, 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0); pirq_info++; slot_num++; -//nic + + /* NIC */ write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 0xa) << 3) | 0, 0x1, 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0); pirq_info++; slot_num++; #if 0 -//firewire ?? + /* Firewire? */ write_pirq_info(pirq_info, bus_ck804_1, (0x5 << 3) | 0, 0x3, 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0); pirq_info++; @@ -196,10 +188,8 @@ sum += v[i]; sum = pirq->checksum - sum; - - if (sum != pirq->checksum) { + if (sum != pirq->checksum) pirq->checksum = sum; - } printk_info("done.\n"); Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/mptable.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8n_e/mptable.c 2008-09-30 06:13:54 UTC (rev 3621) +++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/mptable.c 2008-09-30 15:02:40 UTC (rev 3622) @@ -26,28 +26,23 @@ #include <device/pci.h> #include <string.h> #include <stdint.h> - #include <cpu/amd/amdk8_sysconf.h> extern unsigned char bus_isa; extern unsigned char bus_ck804[6]; extern unsigned apicid_ck804; - extern unsigned bus_type[256]; - extern void get_bus_conf(void); void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; static const char oem[8] = "ASUS "; - static const char productid[12] = "A8NE "; + static const char productid[12] = "A8N-E "; struct mp_config_table *mc; unsigned sbdn; + int i, bus_num; - int bus_num; - int i; - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc)); @@ -70,15 +65,15 @@ get_bus_conf(); sbdn = sysconf.sbdn; -/* Bus: Bus ID Type*/ - /* define numbers for pci and isa bus */ + /* Bus: Bus ID Type */ + /* Define numbers for PCI and ISA bus. */ for (bus_num = 0; bus_num < 256; bus_num++) { if (bus_type[bus_num]) smp_write_bus(mc, bus_num, "PCI "); - } + } smp_write_bus(mc, bus_isa, "ISA "); -/* I/O APICs: APIC ID Version State Address*/ + /* I/O APICs: APIC ID Version State Address */ { device_t dev; struct resource *res; @@ -92,7 +87,7 @@ res->base); } - /* Initialize interrupt mapping */ + /* Initialize interrupt mapping. */ dword = 0x01200000; pci_write_config32(dev, 0x7c, dword); @@ -105,7 +100,7 @@ } } -/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x0, apicid_ck804, 0x0); @@ -151,21 +146,31 @@ 0xa); // Onboard ck804 USB 1.1 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_ck804[0], ((sbdn + 2) << 2) | 0, apicid_ck804, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + bus_ck804[0], ((sbdn + 2) << 2) | 0, apicid_ck804, + 0x15); // Onboard ck804 USB 2 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_ck804[0], ((sbdn + 2) << 2) | 1, apicid_ck804, 0x14); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + bus_ck804[0], ((sbdn + 2) << 2) | 1, apicid_ck804, + 0x14); // Onboard ck804 SATA 0 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_ck804[0], ((sbdn + 7) << 2) | 0, apicid_ck804, 0x17); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + bus_ck804[0], ((sbdn + 7) << 2) | 0, apicid_ck804, + 0x17); // Onboard ck804 SATA 1 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_ck804[0], ((sbdn + 8) << 2) | 0, apicid_ck804, 0x16); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + bus_ck804[0], ((sbdn + 8) << 2) | 0, apicid_ck804, + 0x16); // Onboard ck804 NIC - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_ck804[0], ((sbdn + 10) << 2) | 0, apicid_ck804, 0x17); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + bus_ck804[0], ((sbdn + 10) << 2) | 0, apicid_ck804, + 0x17); -/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ + /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, bus_ck804[0], 0x0, MP_APIC_ALL, 0x0); @@ -175,7 +180,7 @@ /* There is no extension information... */ - /* Compute the checksums */ + /* Compute the checksums. */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); @@ -186,7 +191,6 @@ unsigned long write_smp_table(unsigned long addr) { - void *v; - v = smp_write_floating_table(addr); + void *v = smp_write_floating_table(addr); return (unsigned long)smp_write_config_table(v); } Modified: trunk/coreboot-v2/targets/asus/a8n_e/Config.lb =================================================================== --- trunk/coreboot-v2/targets/asus/a8n_e/Config.lb 2008-09-30 06:13:54 UTC (rev 3621) +++ trunk/coreboot-v2/targets/asus/a8n_e/Config.lb 2008-09-30 15:02:40 UTC (rev 3622) @@ -23,30 +23,30 @@ mainboard asus/a8n_e romimage "normal" - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x20000 - option XIP_ROM_SIZE=0x20000 - option COREBOOT_EXTRA_VERSION="_Normal" + option USE_FAILOVER_IMAGE = 0 + option USE_FALLBACK_IMAGE = 0 + option ROM_IMAGE_SIZE = 128 * 1024 + option XIP_ROM_SIZE = 128 * 1024 + option COREBOOT_EXTRA_VERSION = "_Normal" payload ../payload.elf end romimage "fallback" - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x20000 - option XIP_ROM_SIZE=0x20000 - option COREBOOT_EXTRA_VERSION="_Fallback" + option USE_FAILOVER_IMAGE = 0 + option USE_FALLBACK_IMAGE = 1 + option ROM_IMAGE_SIZE = 128 * 1024 + option XIP_ROM_SIZE = 128 * 1024 + option COREBOOT_EXTRA_VERSION = "_Fallback" payload ../payload.elf end romimage "failover" - option USE_FAILOVER_IMAGE=1 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=FAILOVER_SIZE - option XIP_ROM_SIZE=FAILOVER_SIZE - option COREBOOT_EXTRA_VERSION="_Failover" + option USE_FAILOVER_IMAGE = 1 + option USE_FALLBACK_IMAGE = 0 + option ROM_IMAGE_SIZE = FAILOVER_SIZE + option XIP_ROM_SIZE = FAILOVER_SIZE + option COREBOOT_EXTRA_VERSION = "_Failover" end buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover" -#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +# buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"

1 0

buildrom: Automaticaly pad ROMs
by Jordan Crouse 30 Sep '08

30 Sep '08

The potential pitfalls for this patch are many, but I think the reward outweights the risk. The script will need the usual 0755 treatment. Jordan -- Jordan Crouse Systems Software Development Engineer Advanced Micro Devices, Inc.

3 4

[FILO] #12: parameterless 'configfile' should print help or prompt, not clear screen.
by FILO 30 Sep '08

30 Sep '08

#12: parameterless 'configfile' should print help or prompt, not clear screen. ------------------------------------+--------------------------------------- Reporter: hawke(a)hawkesnest.net | Owner: somebody Type: defect | Status: new Priority: minor | Milestone: Component: FILO | Version: Keywords: | Dependencies: Patchstatus: there is no patch | ------------------------------------+--------------------------------------- If the command 'configfile' is run without any parameters, it should either prompt for a config filename or display the help for it, instead of clearing the screen/resetting filo. -- Ticket URL: <http://tracker.coreboot.org/trac/filo/ticket/12> FILO <http://www.coreboot.org/FILO>

1 2

r72 - trunk/filo/main/grub
by svn＠coreboot.org 30 Sep '08

30 Sep '08

Author: oxygene Date: 2008-09-30 12:40:03 +0200 (Tue, 30 Sep 2008) New Revision: 72 Modified: trunk/filo/main/grub/builtins.c Log: fix for "configfile" without a file name. it runs "help configfile" in that case fixes #12 Modified: trunk/filo/main/grub/builtins.c =================================================================== --- trunk/filo/main/grub/builtins.c 2008-09-30 10:38:32 UTC (rev 71) +++ trunk/filo/main/grub/builtins.c 2008-09-30 10:40:03 UTC (rev 72) @@ -247,6 +247,7 @@ " \"blink-\" to FG if you want a blinking foreground color." }; +static int help_func(char *arg, int flags); /* configfile */ static int configfile_func(char *arg, int flags) { @@ -255,6 +256,9 @@ /* Check if the file ARG is present. */ temp_space[0]=0; copy_path_to_filo_bootline(arg, temp_space, 1); + if (temp_space[0]==0) { + return help_func("configfile",0); + } if (!file_open(temp_space)) { errnum = ERR_FILE_NOT_FOUND; return 1;

1 0

r71 - trunk/filo/main/grub
by svn＠coreboot.org 30 Sep '08

30 Sep '08

Author: oxygene Date: 2008-09-30 12:38:32 +0200 (Tue, 30 Sep 2008) New Revision: 71 Modified: trunk/filo/main/grub/builtins.c Log: fix "color" command fixes #15 Modified: trunk/filo/main/grub/builtins.c =================================================================== --- trunk/filo/main/grub/builtins.c 2008-09-30 09:42:37 UTC (rev 70) +++ trunk/filo/main/grub/builtins.c 2008-09-30 10:38:32 UTC (rev 71) @@ -182,12 +182,6 @@ /* Terminate the string STR. */ *ptr++ = 0; - /* If STR contains the prefix "blink-", then set the `blink' bit in COLOR. */ - if (substring("blink-", str) <= 0) { - color = 0x80; - str += 6; - } - /* Search for the color name. */ for (i = 0; i < 16; i++) if (strcmp(color_list[i], str) == 0) { @@ -202,13 +196,13 @@ nul_terminate(str); /* Search for the color name. */ - for (i = 0; i < 8; i++) + for (i = 0; i < 16; i++) if (strcmp(color_list[i], str) == 0) { color |= i; break; } - if (i == 8) + if (i == 16) return -1; return color;

1 0

[FILO] #1: ext2 won't work if FAT is enabled
by FILO 30 Sep '08

30 Sep '08

#1: ext2 won't work if FAT is enabled ------------------------------------+--------------------------------------- Reporter: hawke(a)hawkesnest.net | Owner: somebody Type: defect | Status: new Priority: minor | Milestone: Component: component1 | Version: Keywords: | Dependencies: Patchstatus: there is no patch | ------------------------------------+--------------------------------------- If both the FAT filesystem and the ext2 filesystem are enabled, the ext2 filesystem cannot be used because filo treats any FS as fat. This may also apply to other filesystems when there are several enabled -- Ticket URL: </trac/ticket/1> FILO <http://www.coreboot.org/FILO>

1 6

r70 - trunk/filo/fs
by svn＠coreboot.org 30 Sep '08

30 Sep '08

Author: oxygene Date: 2008-09-30 11:42:37 +0200 (Tue, 30 Sep 2008) New Revision: 70 Modified: trunk/filo/fs/fat.h trunk/filo/fs/fsys_fat.c Log: take a closer look at the filesystem before interpreting it as FAT. fixes #1 Modified: trunk/filo/fs/fat.h =================================================================== --- trunk/filo/fs/fat.h 2008-09-29 17:47:50 UTC (rev 69) +++ trunk/filo/fs/fat.h 2008-09-30 09:42:37 UTC (rev 70) @@ -1,6 +1,7 @@ /* * GRUB -- GRand Unified Bootloader * Copyright (C) 2001 Free Software Foundation, Inc. + * Copyright (C) 2008 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -30,6 +31,35 @@ typedef __signed__ int __s32; typedef unsigned int __u32; + +struct fat16_extended_bpb { + __u8 drive_number; /* Physical Drive Number */ + __u8 reserved; /* "current head" */ + __u8 boot_signature; /* Extended Boot Signature 0x28 or 0x29 */ + __u8 id[4]; /* ID (serial number) */ + __u8 volumelabel[11];/* volume label */ + __s8 type[8]; /* Padded with blanks: "FAT12", "FAT16" */ +} __attribute__((packed)); + +struct fat32_extended_bpb { + /* The following fields are only used by FAT32 */ + __u32 fat32_length; /* sectors/FAT */ + __u16 flags; /* bit 8: fat mirroring, low 4: active fat */ + __u8 version[2]; /* major, minor filesystem version */ + __u32 root_cluster; /* first cluster in root directory */ + __u16 info_sector; /* filesystem info sector */ + __u16 backup_boot; /* backup boot sector */ + __u16 reserved2[12]; /* Reserved */ + /* from here on it looks like the fat12/fat16 code */ + __u8 drive_number; /* Physical Drive Number */ + __u8 reserved; /* "current head" */ + __u8 boot_signature; /* Extended Boot Signature 0x28 or 0x29 */ + __u8 id[4]; /* ID (serial number) */ + __u8 volumelabel[11];/* volume label */ + __s8 type[8]; /* Padded with blanks: "FAT32" */ +} __attribute__((packed)); + + /* Note that some shorts are not aligned, and must therefore * be declared as array of two bytes. */ @@ -50,14 +80,10 @@ __u32 hidden; /* hidden sectors (unused) */ __u32 long_sectors; /* number of sectors (if short_sectors == 0) */ - /* The following fields are only used by FAT32 */ - __u32 fat32_length; /* sectors/FAT */ - __u16 flags; /* bit 8: fat mirroring, low 4: active fat */ - __u8 version[2]; /* major, minor filesystem version */ - __u32 root_cluster; /* first cluster in root directory */ - __u16 info_sector; /* filesystem info sector */ - __u16 backup_boot; /* backup boot sector */ - __u16 reserved2[6]; /* Unused */ + union { + struct fat16_extended_bpb fat16; + struct fat32_extended_bpb fat32; + } extended; }; #define FAT_CVT_U16(bytarr) (* (__u16*)(bytarr)) Modified: trunk/filo/fs/fsys_fat.c =================================================================== --- trunk/filo/fs/fsys_fat.c 2008-09-29 17:47:50 UTC (rev 69) +++ trunk/filo/fs/fsys_fat.c 2008-09-30 09:42:37 UTC (rev 70) @@ -83,7 +83,7 @@ /* FAT offset and length */ FAT_SUPER->fat_offset = FAT_CVT_U16 (bpb.reserved_sects); FAT_SUPER->fat_length = - bpb.fat_length ? bpb.fat_length : bpb.fat32_length; + bpb.fat_length ? bpb.fat_length : bpb.extended.fat32.fat32_length; /* Rootdir offset and length for FAT12/16 */ FAT_SUPER->root_offset = @@ -99,23 +99,31 @@ / bpb.sects_per_clust); FAT_SUPER->sects_per_clust = bpb.sects_per_clust; + if (strncmp(bpb.extended.fat16.type, "FAT12", 5) && + strncmp(bpb.extended.fat16.type, "FAT16", 5) && + strncmp(bpb.extended.fat32.type, "FAT32", 5)) + { + /* None of them matched. Bail out */ + return 0; + } + if (!bpb.fat_length) { /* This is a FAT32 */ if (FAT_CVT_U16(bpb.dir_entries)) return 0; - if (bpb.flags & 0x0080) + if (bpb.extended.fat32.flags & 0x0080) { /* FAT mirroring is disabled, get active FAT */ - int active_fat = bpb.flags & 0x000f; + int active_fat = bpb.extended.fat32.flags & 0x000f; if (active_fat >= bpb.num_fats) return 0; FAT_SUPER->fat_offset += active_fat * FAT_SUPER->fat_length; } FAT_SUPER->fat_size = 8; - FAT_SUPER->root_cluster = bpb.root_cluster; + FAT_SUPER->root_cluster = bpb.extended.fat32.root_cluster; /* Yes the following is correct. FAT32 should be called FAT28 :) */ FAT_SUPER->clust_eof_marker = 0xffffff8;

1 0

[PATCH] nvramtool: string support
by Stefan Reinauer 30 Sep '08

30 Sep '08

See patch -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 Add string support to nvramtool. To add a string to your cmos.layout, you need to specify type 's': #start len type unused name 416 512 s 0 boot_devices With this patch you can do $ nvramtool -w boot_devices="(hd0,0);(hd2,1);(hd3)" And FILO will attempt to load a menu.lst from any of these devices in that order. The patch is not exactly pretty, but a cleaner solution might have resulted in a complete rewrite of the tool, which I did not want. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Index: util/nvramtool/input_file.c =================================================================== --- util/nvramtool/input_file.c (revision 364) +++ util/nvramtool/input_file.c (working copy) @@ -1,6 +1,5 @@ /*****************************************************************************\ * input_file.c - * $Id: input_file.c 3122 2008-03-01 19:06:32Z uwe $ ***************************************************************************** * Copyright (C) 2002-2005 The Regents of the University of California. * Produced at the Lawrence Livermore National Laboratory. @@ -137,6 +136,7 @@ item->bit = e->bit; item->length = e->length; + item->config = e->config; item->value = try_prepare_cmos_write(e, value); /* Append write operation to pending write list. */ @@ -162,9 +162,13 @@ set_iopl(3); while (list != NULL) - { item = list; + { cmos_entry_t e; + item = list; + e.bit = item->bit; + e.length = item->length; + e.config = item->config; list = item->next; - cmos_write(item->bit, item->length, item->value); + cmos_write(&e, item->value); free(item); } Index: util/nvramtool/nvramtool.1 =================================================================== --- util/nvramtool/nvramtool.1 (revision 364) +++ util/nvramtool/nvramtool.1 (working copy) @@ -1,6 +1,5 @@ .\"***************************************************************************\ .\" nvramtool.1 -.\" $Id: nvramtool.1 3123 2008-03-01 19:07:46Z uwe $ .\"*************************************************************************** .\" Copyright (C) 2002, 2003 The Regents of the University of California. .\" Produced at the Lawrence Livermore National Laboratory. @@ -28,7 +27,7 @@ .\" with this program; if not, write to the Free Software Foundation, Inc., .\" 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. .\"***************************************************************************/ -.TH NVRAMTOOL 1 "January 2008" Linux +.TH NVRAMTOOL 1 "September 2008" Linux .SH NAME nvramtool \- read/write coreboot-related information .SH SYNOPSIS @@ -252,4 +251,4 @@ .SH AUTHORS David S. Peterson <dsp(a)llnl.gov> <dave_peterson(a)pobox.com> .br -Stefan Reinauer <stepan(a)openbios.org> +Stefan Reinauer <stepan(a)coresystems.de> Index: util/nvramtool/ip_checksum.h =================================================================== --- util/nvramtool/ip_checksum.h (revision 364) +++ util/nvramtool/ip_checksum.h (working copy) @@ -1,6 +1,5 @@ /*****************************************************************************\ * ip_checksum.h - * $Id: ip_checksum.h 3075 2008-01-25 15:08:37Z uwe $ \*****************************************************************************/ #ifndef IP_CHECKSUM_H Index: util/nvramtool/input_file.h =================================================================== --- util/nvramtool/input_file.h (revision 364) +++ util/nvramtool/input_file.h (working copy) @@ -1,6 +1,5 @@ /*****************************************************************************\ * input_file.h - * $Id: input_file.h 3122 2008-03-01 19:06:32Z uwe $ ***************************************************************************** * Copyright (C) 2002-2005 The Regents of the University of California. * Produced at the Lawrence Livermore National Laboratory. @@ -33,6 +32,7 @@ #define INPUT_FILE_H #include "common.h" +#include "layout.h" typedef struct cmos_write_t cmos_write_t; @@ -44,6 +44,7 @@ struct cmos_write_t { unsigned bit; unsigned length; + cmos_entry_config_t config; unsigned long long value; cmos_write_t *next; }; Index: util/nvramtool/lbtable.c =================================================================== --- util/nvramtool/lbtable.c (revision 364) +++ util/nvramtool/lbtable.c (working copy) @@ -1,6 +1,5 @@ /*****************************************************************************\ * lbtable.c - * $Id: lbtable.c 3122 2008-03-01 19:06:32Z uwe $ ***************************************************************************** * Copyright (C) 2002-2005 The Regents of the University of California. * Produced at the Lawrence Livermore National Laboratory. @@ -30,6 +29,7 @@ * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. \*****************************************************************************/ +#include <string.h> #include <sys/mman.h> #include "common.h" #include "coreboot_tables.h" @@ -556,7 +556,7 @@ for (p = first_cmos_table_enum(); p != NULL; p = next_cmos_table_enum(p)) { cmos_enum.config_id = p->config_id; cmos_enum.value = p->value; - strncpy(cmos_enum.text, p->text, CMOS_MAX_TEXT_LENGTH); + strncpy(cmos_enum.text, (char *)p->text, CMOS_MAX_TEXT_LENGTH); cmos_enum.text[CMOS_MAX_TEXT_LENGTH] = '\0'; try_add_cmos_table_enum(&cmos_enum); } @@ -581,6 +581,10 @@ cmos_entry.config = CMOS_ENTRY_RESERVED; break; + case 's': + cmos_entry.config = CMOS_ENTRY_STRING; + break; + default: fprintf(stderr, "%s: Entry in CMOS option table has unknown config " @@ -589,7 +593,7 @@ } cmos_entry.config_id = q->config_id; - strncpy(cmos_entry.name, q->name, CMOS_MAX_NAME_LENGTH); + strncpy(cmos_entry.name, (char *)q->name, CMOS_MAX_NAME_LENGTH); cmos_entry.name[CMOS_MAX_NAME_LENGTH] = '\0'; try_add_cmos_table_entry(&cmos_entry); } Index: util/nvramtool/ChangeLog =================================================================== --- util/nvramtool/ChangeLog (revision 364) +++ util/nvramtool/ChangeLog (working copy) @@ -1,3 +1,11 @@ +Tue Sep 23 19:14:27 CEST 2008 Stefan Reinauer (stepan(a)coresystems.de) + + Version 2.1 + + * Fix a number of off by one errors when accessing arrays + + * Add support for reading/writing strings from/to CMOS. + Mon Jan 23 16:00:00 PST 2006 David S. Peterson (dsp(a)llnl.gov) Version 2.0.1 Index: util/nvramtool/lbtable.h =================================================================== --- util/nvramtool/lbtable.h (revision 364) +++ util/nvramtool/lbtable.h (working copy) @@ -1,6 +1,5 @@ /*****************************************************************************\ * lbtable.h - * $Id: lbtable.h 3122 2008-03-01 19:06:32Z uwe $ ***************************************************************************** * Copyright (C) 2002-2005 The Regents of the University of California. * Produced at the Lawrence Livermore National Laboratory. Index: util/nvramtool/cmos_lowlevel.c =================================================================== --- util/nvramtool/cmos_lowlevel.c (revision 364) +++ util/nvramtool/cmos_lowlevel.c (working copy) @@ -1,6 +1,5 @@ /*****************************************************************************\ * cmos_lowlevel.c - * $Id: cmos_lowlevel.c 3122 2008-03-01 19:06:32Z uwe $ ***************************************************************************** * Copyright (C) 2002-2005 The Regents of the University of California. * Produced at the Lawrence Livermore National Laboratory. @@ -70,7 +69,7 @@ ****************************************************************************/ static inline void put_bits (unsigned char value, unsigned bit, unsigned nr_bits, unsigned long long *result) - { *result += (value & ((unsigned char) ((1 << nr_bits) - 1))) << bit; } + { *result += ((unsigned long long)(value & ((unsigned char) ((1 << nr_bits) - 1)))) << bit; } /**************************************************************************** * cmos_read @@ -79,22 +78,40 @@ * and return this value. The I/O privilege level of the currently executing * process must be set appropriately. ****************************************************************************/ -unsigned long long cmos_read (unsigned bit, unsigned length) +unsigned long long cmos_read (const cmos_entry_t *e) { cmos_bit_op_location_t where; + unsigned bit = e->bit, length=e->length; unsigned next_bit, bits_left, nr_bits; - unsigned long long result; + unsigned long long result = 0; unsigned char value; - assert(!verify_cmos_op(bit, length)); + assert(!verify_cmos_op(bit, length, e->config)); result = 0; - for (next_bit = 0, bits_left = length; - bits_left; - next_bit += nr_bits, bits_left -= nr_bits) - { nr_bits = cmos_bit_op_strategy(bit + next_bit, bits_left, &where); - value = cmos_read_bits(&where, nr_bits); - put_bits(value, next_bit, nr_bits, &result); + if (e->config == CMOS_ENTRY_STRING) + { char *newstring = malloc((length+7)/8); + unsigned usize = (8 * sizeof(unsigned long long)); + + if(!newstring) { out_of_memory(); } + + for (next_bit = 0, bits_left = length; + bits_left; + next_bit += nr_bits, bits_left -= nr_bits) + { nr_bits = cmos_bit_op_strategy(bit + next_bit, bits_left>usize?usize:bits_left, &where); + value = cmos_read_bits(&where, nr_bits); + put_bits(value, next_bit % usize, nr_bits, &((unsigned long long *)newstring)[next_bit/usize]); + result = (unsigned long)newstring; + } } + else + { for (next_bit = 0, bits_left = length; + bits_left; + next_bit += nr_bits, bits_left -= nr_bits) + { nr_bits = cmos_bit_op_strategy(bit + next_bit, bits_left, &where); + value = cmos_read_bits(&where, nr_bits); + put_bits(value, next_bit, nr_bits, &result); + } + } return result; } @@ -106,18 +123,33 @@ * The I/O privilege level of the currently executing process must be set * appropriately. ****************************************************************************/ -void cmos_write (unsigned bit, unsigned length, unsigned long long value) +void cmos_write (const cmos_entry_t *e, unsigned long long value) { cmos_bit_op_location_t where; + unsigned bit = e->bit, length=e->length; unsigned next_bit, bits_left, nr_bits; - assert(!verify_cmos_op(bit, length)); + assert(!verify_cmos_op(bit, length, e->config)); - for (next_bit = 0, bits_left = length; - bits_left; - next_bit += nr_bits, bits_left -= nr_bits) - { nr_bits = cmos_bit_op_strategy(bit + next_bit, bits_left, &where); - cmos_write_bits(&where, nr_bits, get_bits(value, next_bit, nr_bits)); + if (e->config == CMOS_ENTRY_STRING) + { unsigned long long *data = (unsigned long long *)(unsigned long)value; + unsigned usize = (8 * sizeof(unsigned long long)); + + for (next_bit = 0, bits_left = length; + bits_left; + next_bit += nr_bits, bits_left -= nr_bits) + { nr_bits = cmos_bit_op_strategy(bit + next_bit, bits_left>usize?usize:bits_left, &where); + value = data[next_bit/usize]; + cmos_write_bits(&where, nr_bits, get_bits(value, next_bit % usize, nr_bits)); + } } + else + { for (next_bit = 0, bits_left = length; + bits_left; + next_bit += nr_bits, bits_left -= nr_bits) + { nr_bits = cmos_bit_op_strategy(bit + next_bit, bits_left, &where); + cmos_write_bits(&where, nr_bits, get_bits(value, next_bit, nr_bits)); + } + } } /**************************************************************************** @@ -236,13 +268,16 @@ * wish to read or write. Perform sanity checking on 'bit' and 'length'. If * no problems were encountered, return OK. Else return an error code. ****************************************************************************/ -int verify_cmos_op (unsigned bit, unsigned length) +int verify_cmos_op (unsigned bit, unsigned length, cmos_entry_config_t config) { if ((bit >= (8 * CMOS_SIZE)) || ((bit + length) > (8 * CMOS_SIZE))) return CMOS_AREA_OUT_OF_RANGE; if (bit < (8 * CMOS_RTC_AREA_SIZE)) return CMOS_AREA_OVERLAPS_RTC; + if (config == CMOS_ENTRY_STRING) + return OK; + if (length > (8 * sizeof(unsigned long long))) return CMOS_AREA_TOO_WIDE; Index: util/nvramtool/hexdump.c =================================================================== --- util/nvramtool/hexdump.c (revision 364) +++ util/nvramtool/hexdump.c (working copy) @@ -1,6 +1,5 @@ /*****************************************************************************\ * hexdump.c - * $Id: hexdump.c 3075 2008-01-25 15:08:37Z uwe $ \*****************************************************************************/ #include "hexdump.h" Index: util/nvramtool/reg_expr.c =================================================================== --- util/nvramtool/reg_expr.c (revision 364) +++ util/nvramtool/reg_expr.c (working copy) @@ -1,6 +1,5 @@ /*****************************************************************************\ * reg_expr.c - * $Id: reg_expr.c 3122 2008-03-01 19:06:32Z uwe $ ***************************************************************************** * Copyright (C) 2002-2005 The Regents of the University of California. * Produced at the Lawrence Livermore National Laboratory. Index: util/nvramtool/layout_file.c =================================================================== --- util/nvramtool/layout_file.c (revision 364) +++ util/nvramtool/layout_file.c (working copy) @@ -1,6 +1,5 @@ /*****************************************************************************\ * layout_file.c - * $Id: layout_file.c 3122 2008-03-01 19:06:32Z uwe $ ***************************************************************************** * Copyright (C) 2002-2005 The Regents of the University of California. * Produced at the Lawrence Livermore National Laboratory. @@ -551,6 +550,10 @@ cmos_entry->config = CMOS_ENTRY_HEX; break; + case 's': + cmos_entry->config = CMOS_ENTRY_STRING; + break; + case 'r': cmos_entry->config = CMOS_ENTRY_RESERVED; break; @@ -758,6 +761,9 @@ case CMOS_ENTRY_RESERVED: return 'r'; + case CMOS_ENTRY_STRING: + return 's'; + default: BUG(); } Index: util/nvramtool/README =================================================================== --- util/nvramtool/README (revision 364) +++ util/nvramtool/README (working copy) @@ -1,5 +1,3 @@ -$Id: README 3122 2008-03-01 19:06:32Z uwe $ - Summary of Operation -------------------- nvramtool is a utility for reading/writing coreboot parameters and Index: util/nvramtool/layout.c =================================================================== --- util/nvramtool/layout.c (revision 364) +++ util/nvramtool/layout.c (working copy) @@ -1,6 +1,5 @@ /*****************************************************************************\ * layout.c - * $Id: layout.c 3122 2008-03-01 19:06:32Z uwe $ ***************************************************************************** * Copyright (C) 2002-2005 The Regents of the University of California. * Produced at the Lawrence Livermore National Laboratory. Index: util/nvramtool/cmos_lowlevel.h =================================================================== --- util/nvramtool/cmos_lowlevel.h (revision 364) +++ util/nvramtool/cmos_lowlevel.h (working copy) @@ -1,6 +1,5 @@ /*****************************************************************************\ * cmos_lowlevel.h - * $Id: cmos_lowlevel.h 3122 2008-03-01 19:06:32Z uwe $ ***************************************************************************** * Copyright (C) 2002-2005 The Regents of the University of California. * Produced at the Lawrence Livermore National Laboratory. @@ -33,19 +32,20 @@ #define NVRAMTOOL_CMOS_LOWLEVEL_H #include "common.h" +#include "layout.h" #define CMOS_AREA_OUT_OF_RANGE (CMOS_RESULT_START + 0) #define CMOS_AREA_OVERLAPS_RTC (CMOS_RESULT_START + 1) #define CMOS_AREA_TOO_WIDE (CMOS_RESULT_START + 2) -unsigned long long cmos_read (unsigned bit, unsigned length); -void cmos_write (unsigned bit, unsigned length, unsigned long long value); +unsigned long long cmos_read (const cmos_entry_t *e); +void cmos_write (const cmos_entry_t *e, unsigned long long value); unsigned char cmos_read_byte (unsigned index); void cmos_write_byte (unsigned index, unsigned char value); void cmos_read_all (unsigned char data[]); void cmos_write_all (unsigned char data[]); void set_iopl (int level); -int verify_cmos_op (unsigned bit, unsigned length); +int verify_cmos_op (unsigned bit, unsigned length, cmos_entry_config_t config); #define CMOS_SIZE 256 /* size of CMOS memory in bytes */ #define CMOS_RTC_AREA_SIZE 14 /* first 14 bytes control real time clock */ Index: util/nvramtool/hexdump.h =================================================================== --- util/nvramtool/hexdump.h (revision 364) +++ util/nvramtool/hexdump.h (working copy) @@ -1,6 +1,5 @@ /*****************************************************************************\ * hexdump.h - * $Id: hexdump.h 3075 2008-01-25 15:08:37Z uwe $ \*****************************************************************************/ #ifndef _HEXDUMP_H Index: util/nvramtool/reg_expr.h =================================================================== --- util/nvramtool/reg_expr.h (revision 364) +++ util/nvramtool/reg_expr.h (working copy) @@ -1,6 +1,5 @@ /*****************************************************************************\ * reg_expr.h - * $Id: reg_expr.h 3122 2008-03-01 19:06:32Z uwe $ ***************************************************************************** * Copyright (C) 2002-2005 The Regents of the University of California. * Produced at the Lawrence Livermore National Laboratory. Index: util/nvramtool/layout_file.h =================================================================== --- util/nvramtool/layout_file.h (revision 364) +++ util/nvramtool/layout_file.h (working copy) @@ -1,6 +1,5 @@ /*****************************************************************************\ * layout_file.h - * $Id: layout_file.h 3122 2008-03-01 19:06:32Z uwe $ ***************************************************************************** * Copyright (C) 2002-2005 The Regents of the University of California. * Produced at the Lawrence Livermore National Laboratory. Index: util/nvramtool/nvramtool.c =================================================================== --- util/nvramtool/nvramtool.c (revision 364) +++ util/nvramtool/nvramtool.c (working copy) @@ -1,6 +1,5 @@ /*****************************************************************************\ * nvramtool.c - * $Id: nvramtool.c 3123 2008-03-01 19:07:46Z uwe $ ***************************************************************************** * Copyright (C) 2002-2005 The Regents of the University of California. * Produced at the Lawrence Livermore National Laboratory. @@ -477,6 +476,11 @@ e->length); break; + case CMOS_ENTRY_STRING: + printf("Parameter %s requires a %u-byte string.\n", name, + e->length / 8); + break; + case CMOS_ENTRY_RESERVED: printf("Parameter %s is reserved.\n", name); break; @@ -570,7 +574,7 @@ /* write the value to nonvolatile RAM */ set_iopl(3); - cmos_write(e->bit, e->length, n); + cmos_write(e, n); cmos_checksum_write(cmos_checksum_compute()); set_iopl(0); return; @@ -674,7 +678,7 @@ /* read the value from CMOS */ set_iopl(3); - value = cmos_read(e->bit, e->length); + value = cmos_read(e); set_iopl(0); /* display the value */ @@ -703,6 +707,16 @@ break; + case CMOS_ENTRY_STRING: + if (show_name) + printf("%s = %s\n", e->name, (char *)(unsigned long)value); + else + printf("%s\n", (char *)(unsigned long)value); + + free((void *)(unsigned long)value); + + break; + case CMOS_ENTRY_RESERVED: default: BUG(); Index: util/nvramtool/cmos_ops.c =================================================================== --- util/nvramtool/cmos_ops.c (revision 364) +++ util/nvramtool/cmos_ops.c (working copy) @@ -1,6 +1,5 @@ /*****************************************************************************\ * cmos_ops.c - * $Id: cmos_ops.c 3122 2008-03-01 19:06:32Z uwe $ ***************************************************************************** * Copyright (C) 2002-2005 The Regents of the University of California. * Produced at the Lawrence Livermore National Laboratory. @@ -47,7 +46,7 @@ /* Access to reserved parameters is not permitted. */ return CMOS_OP_RESERVED; - if ((result = verify_cmos_op(e->bit, e->length)) != OK) + if ((result = verify_cmos_op(e->bit, e->length, e->config)) != OK) return result; assert(e->length > 0); @@ -70,6 +69,7 @@ switch (e->config) { case CMOS_ENTRY_ENUM: case CMOS_ENTRY_HEX: + case CMOS_ENTRY_STRING: break; default: @@ -92,6 +92,7 @@ { const cmos_enum_t *q; unsigned long long out; const char *p; + char *memory; int negative, result, found_one; if ((result = prepare_cmos_op_common(e)) != OK) @@ -139,6 +140,15 @@ break; + case CMOS_ENTRY_STRING: + if (e->length < (8 * strlen(value_str))) + return CMOS_OP_VALUE_TOO_WIDE; + memory = malloc(e->length / 8); + memset(memory, 0, e->length / 8); + strcpy(memory, value_str); + out = (unsigned long)memory; + break; + default: BUG(); } Index: util/nvramtool/layout.h =================================================================== --- util/nvramtool/layout.h (revision 364) +++ util/nvramtool/layout.h (working copy) @@ -1,6 +1,5 @@ /*****************************************************************************\ * layout.h - * $Id: layout.h 3122 2008-03-01 19:06:32Z uwe $ ***************************************************************************** * Copyright (C) 2002-2005 The Regents of the University of California. * Produced at the Lawrence Livermore National Laboratory. @@ -49,6 +48,7 @@ typedef enum { CMOS_ENTRY_ENUM, CMOS_ENTRY_HEX, + CMOS_ENTRY_STRING, CMOS_ENTRY_RESERVED } cmos_entry_config_t; @@ -59,7 +59,7 @@ unsigned length; cmos_entry_config_t config; unsigned config_id; - char name[CMOS_MAX_NAME_LENGTH]; + char name[CMOS_MAX_NAME_LENGTH + 1]; } cmos_entry_t; @@ -69,7 +69,7 @@ typedef struct { unsigned config_id; unsigned long long value; - char text[CMOS_MAX_TEXT_LENGTH]; + char text[CMOS_MAX_TEXT_LENGTH + 1]; } cmos_enum_t; Index: util/nvramtool/opts.c =================================================================== --- util/nvramtool/opts.c (revision 364) +++ util/nvramtool/opts.c (working copy) @@ -1,6 +1,5 @@ /*****************************************************************************\ * opts.c - * $Id: opts.c 3122 2008-03-01 19:06:32Z uwe $ ***************************************************************************** * Copyright (C) 2002-2005 The Regents of the University of California. * Produced at the Lawrence Livermore National Laboratory. Index: util/nvramtool/compute_ip_checksum.c =================================================================== --- util/nvramtool/compute_ip_checksum.c (revision 364) +++ util/nvramtool/compute_ip_checksum.c (working copy) @@ -1,6 +1,5 @@ /*****************************************************************************\ * compute_ip_checksum.c - * $Id: compute_ip_checksum.c 3075 2008-01-25 15:08:37Z uwe $ \*****************************************************************************/ #include <stdint.h> Index: util/nvramtool/cmos_ops.h =================================================================== --- util/nvramtool/cmos_ops.h (revision 364) +++ util/nvramtool/cmos_ops.h (working copy) @@ -1,6 +1,5 @@ /*****************************************************************************\ * cmos_ops.h - * $Id: cmos_ops.h 3122 2008-03-01 19:06:32Z uwe $ ***************************************************************************** * Copyright (C) 2002-2005 The Regents of the University of California. * Produced at the Lawrence Livermore National Laboratory. Index: util/nvramtool/common.c =================================================================== --- util/nvramtool/common.c (revision 364) +++ util/nvramtool/common.c (working copy) @@ -1,6 +1,5 @@ /*****************************************************************************\ * common.c - * $Id: common.c 3122 2008-03-01 19:06:32Z uwe $ ***************************************************************************** * Copyright (C) 2002-2005 The Regents of the University of California. * Produced at the Lawrence Livermore National Laboratory. @@ -35,7 +34,7 @@ const char prog_name[] = "nvramtool"; /* version of this program */ -const char prog_version[] = "2.0.1"; +const char prog_version[] = "2.1"; /**************************************************************************** * get_line_from_file Index: util/nvramtool/nvramtool.spec =================================================================== --- util/nvramtool/nvramtool.spec (revision 364) +++ util/nvramtool/nvramtool.spec (working copy) @@ -1,9 +1,7 @@ ## -# $Id: nvramtool.spec 3123 2008-03-01 19:07:46Z uwe $ -## Name: nvramtool -Version: 2.0.1 +Version: 2.1 Release: 0 Summary: coreboot utility program Index: util/nvramtool/opts.h =================================================================== --- util/nvramtool/opts.h (revision 364) +++ util/nvramtool/opts.h (working copy) @@ -1,6 +1,5 @@ /*****************************************************************************\ * opts.h - * $Id: opts.h 3122 2008-03-01 19:06:32Z uwe $ ***************************************************************************** * Copyright (C) 2002-2005 The Regents of the University of California. * Produced at the Lawrence Livermore National Laboratory. Index: util/nvramtool/DISCLAIMER =================================================================== --- util/nvramtool/DISCLAIMER (revision 364) +++ util/nvramtool/DISCLAIMER (working copy) @@ -1,8 +1,8 @@ #################################################################### -# $Id: DISCLAIMER 3122 2008-03-01 19:06:32Z uwe $ -#################################################################### Copyright (C) 2002 The Regents of the University of California. +Copyright (C) 2008 coresystems GmbH + Produced at the Lawrence Livermore National Laboratory. Written by David S. Peterson <dsp(a)llnl.gov>. UCRL-CODE-2003-012 Index: util/nvramtool/Makefile =================================================================== --- util/nvramtool/Makefile (revision 364) +++ util/nvramtool/Makefile (working copy) @@ -1,28 +1,43 @@ -# $Id: Makefile 3122 2008-03-01 19:06:32Z uwe $ +# +# Makefile for nvram utility +# +# (C) 2005-2008 coresystems GmbH +# written by Stefan Reinauer <stepan(a)coresystems.de> +# -PROJECT = nvramtool -CC = gcc -CFLAGS = -O2 -W -Wall -LDFLAGS = -OBJS = common.o compute_ip_checksum.o hexdump.o cmos_lowlevel.o \ - reg_expr.o layout.o layout_file.o lbtable.o cmos_ops.o input_file.o \ - opts.o nvramtool.o -HEADERS = common.h ip_checksum.h coreboot_tables.h hexdump.h \ - cmos_lowlevel.h reg_expr.h layout.h layout_file.h lbtable.h \ - cmos_ops.h input_file.h opts.h +PROGRAM = nvramtool -all: nvramtool man +CC = gcc +STRIP = strip +INSTALL = /usr/bin/install +PREFIX = /usr/local +CFLAGS = -O2 -g -Wall -W +#CFLAGS = -Os -Wall -nvramtool: $(OBJS) - $(CC) $(LDFLAGS) -o $@ $(OBJS) +OBJS = cmos_lowlevel.o cmos_ops.o common.o compute_ip_checksum.o \ + hexdump.o input_file.o layout.o layout_file.o lbtable.o \ + nvramtool.o opts.o reg_expr.o -man: nvramtool.1.gz +all: dep $(PROGRAM) -$(OBJS): $(HEADERS) +$(PROGRAM): $(OBJS) + $(CC) -o $(PROGRAM) $(OBJS) $(LDFLAGS) + $(STRIP) $(STRIP_ARGS) $(PROGRAM) -nvramtool.1.gz: nvramtool.1 - gzip -c --best nvramtool.1 > nvramtool.1.gz - clean: - rm -f *.o nvramtool nvramtool.1.gz + rm -f $(PROGRAM) *.o +distclean: clean + rm -f .dependencies + +dep: + @$(CC) -MM *.c > .dependencies + +install: $(PROGRAM) + $(INSTALL) $(PROGRAM) $(PREFIX)/sbin + mkdir -p $(PREFIX)/share/man/man1 + $(INSTALL) $(PROGRAM).1 $(PREFIX)/share/man/man1 + +.PHONY: all clean distclean dep + +-include .dependencies Index: util/nvramtool/common.h =================================================================== --- util/nvramtool/common.h (revision 364) +++ util/nvramtool/common.h (working copy) @@ -1,6 +1,5 @@ /*****************************************************************************\ * common.h - * $Id: common.h 3122 2008-03-01 19:06:32Z uwe $ ***************************************************************************** * Copyright (C) 2002-2005 The Regents of the University of California. * Produced at the Lawrence Livermore National Laboratory.

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by coreboot information 30 Sep '08

30 Sep '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "stuge" checked in revision 3621 to the coreboot source repository and caused the following changes: Change Log: Do not try to display non-printable characters on the bootlog and ramdump screens. This fixes unaligned display on serial console. The current isprint() implementation assumes a C locale, so also characters with the eigth bit set are supressed (they produced inconsistant results on VGA and serial anyway). Signed-off-by: Ulf Jordan <jordan(a)chalmers.se> Acked-by: Peter Stuge <peter(a)stuge.se> Build Log: Compilation of asus:m2v-mx_se is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3621&device=m2v-mx_se&vend… Compilation of jetway:j7f24 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3621&device=j7f24&vendor=j… Compilation of via:epia-cn is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3621&device=epia-cn&vendor… If something broke during this checkin please be a pain in stuge's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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coreboot September 2008