coreboot September 2008

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415 discussions

[FILO] #9: problems if VGA/serial console are different sizes
by FILO 29 Sep '08

29 Sep '08

#9: problems if VGA/serial console are different sizes ------------------------------------+--------------------------------------- Reporter: hawke(a)hawkesnest.net | Owner: somebody Type: defect | Status: new Priority: minor | Milestone: Component: FILO | Version: Keywords: | Dependencies: Patchstatus: there is no patch | ------------------------------------+--------------------------------------- If the serial console is a different size from the vga console, there are some problems with printing grub-style commandline messages. Example: hit enter until the VGA cursor is on line 24. Type 'asdf'. The serial terminal will not display the proper "Error 27: Unrecognized command" until "Enter" is pressed a second time. -- Ticket URL: <http://tracker.coreboot.org/trac/filo/ticket/9> FILO <http://www.coreboot.org/FILO>

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r3616 build service
by coreboot information 29 Sep '08

29 Sep '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "stuge" checked in revision 3616 to the coreboot source repository and caused the following changes: Change Log: flashrom: Fix typo in r3615 (TEST_PREW -> TEST_OK_PREW) Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Peter Stuge <peter(a)stuge.se> Build Log: Compilation of amd:serengeti_cheetah is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3616&device=serengeti_chee… Compilation of asus:m2v-mx_se is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3616&device=m2v-mx_se&vend… Compilation of jetway:j7f24 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3616&device=j7f24&vendor=j… Compilation of msi:ms9185 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3616&device=ms9185&vendor=… Compilation of msi:ms9282 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3616&device=ms9282&vendor=… Compilation of supermicro:h8dmr is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3616&device=h8dmr&vendor=s… Compilation of via:epia-cn is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3616&device=epia-cn&vendor… If something broke during this checkin please be a pain in stuge's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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r242 - buildrom-devel/packages/coreboot-v3
by svn＠coreboot.org 29 Sep '08

29 Sep '08

Author: jcrouse Date: 2008-09-29 23:53:20 +0200 (Mon, 29 Sep 2008) New Revision: 242 Modified: buildrom-devel/packages/coreboot-v3/coreboot-v3.mk Log: buildrom: Fix a typo Peter: Brian! There is a message in my alphabits. It says "ooooo" Brian: Peter, those are cheerios. Signed-off-by: Jordan Crouse <jordan.crouse(a)amd.com> Acked-by: Jordan Crouse <jordan.crouse(a)amd.com> Modified: buildrom-devel/packages/coreboot-v3/coreboot-v3.mk =================================================================== --- buildrom-devel/packages/coreboot-v3/coreboot-v3.mk 2008-09-29 21:15:45 UTC (rev 241) +++ buildrom-devel/packages/coreboot-v3/coreboot-v3.mk 2008-09-29 21:53:20 UTC (rev 242) @@ -40,7 +40,7 @@ # Set the cb-v3 board name to the default if not otherwise # specified -CBV3_BOARD ?= $(COREBOOOT_BOARD) +CBV3_BOARD ?= $(COREBOOT_BOARD) TARGET_ROM = $(COREBOOT_VENDOR)-$(CBV3_BOARD).rom

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Re: [coreboot] r241 - in buildrom-devel/packages: coreinfo libpayload libpayload/conf
by Jordan Crouse 29 Sep '08

29 Sep '08

On 29/09/08 23:15 +0200, svn(a)coreboot.org wrote: > Author: jcrouse > Date: 2008-09-29 23:15:45 +0200 (Mon, 29 Sep 2008) > New Revision: 241 > > Modified: > buildrom-devel/packages/coreinfo/coreinfo.mk > buildrom-devel/packages/libpayload/conf/defconfig > buildrom-devel/packages/libpayload/conf/defconfig.geode > buildrom-devel/packages/libpayload/libpayload.mk > Log: > buildrom: Update the versions for libpayload and coreinfo > > Signed-off-by: Jordan Crouse <jordan.crouse(a)amd.com> > Acked-by: Jordan Crouse <jordan.crouse(a)amd.com> > > > Modified: buildrom-devel/packages/coreinfo/coreinfo.mk > =================================================================== > --- buildrom-devel/packages/coreinfo/coreinfo.mk 2008-09-29 18:03:50 UTC (rev 240) > +++ buildrom-devel/packages/coreinfo/coreinfo.mk 2008-09-29 21:15:45 UTC (rev 241) > @@ -1,5 +1,5 @@ > COREINFO_URL=svn://coreboot.org/repos/trunk/payloads/coreinfo > -COREINFO_TAG=3561 > +COREINFO_TAG=3613 > > COREINFO_DIR=$(BUILD_DIR)/coreinfo > COREINFO_SRC_DIR=$(COREINFO_DIR)/svn > > Modified: buildrom-devel/packages/libpayload/conf/defconfig > =================================================================== > --- buildrom-devel/packages/libpayload/conf/defconfig 2008-09-29 18:03:50 UTC (rev 240) > +++ buildrom-devel/packages/libpayload/conf/defconfig 2008-09-29 21:15:45 UTC (rev 241) > @@ -1,7 +1,7 @@ > # > # Automatically generated make config: don't edit > # libpayload version: 0.1.0 > -# Wed Sep 3 15:31:17 2008 > +# Mon Sep 29 11:29:51 2008 > # > CONFIG_TARGET_I386=y > > @@ -22,6 +22,8 @@ > CONFIG_VGA_VIDEO_CONSOLE=y > # CONFIG_GEODE_VIDEO_CONSOLE is not set > CONFIG_PC_KEYBOARD=y > +CONFIG_PC_KEYBOARD_LAYOUT_US=y > +# CONFIG_PC_KEYBOARD_LAYOUT_DE is not set For posterity (lest I am accused of something), I made sure it was OK with our German developers before defaulting to use the US keyboard layout only. Jordan

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r3616 - trunk/util/flashrom
by svn＠coreboot.org 29 Sep '08

29 Sep '08

Author: stuge Date: 2008-09-29 23:21:36 +0200 (Mon, 29 Sep 2008) New Revision: 3616 Modified: trunk/util/flashrom/flashchips.c Log: flashrom: Fix typo in r3615 (TEST_PREW -> TEST_OK_PREW) Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/util/flashrom/flashchips.c =================================================================== --- trunk/util/flashrom/flashchips.c 2008-09-29 18:48:23 UTC (rev 3615) +++ trunk/util/flashrom/flashchips.c 2008-09-29 21:21:36 UTC (rev 3616) @@ -120,7 +120,7 @@ {"ST", "M50LPW116", ST_ID, ST_M50LPW116, 2048, 64 * 1024, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, {"SyncMOS", "S29C31004T", SYNCMOS_ID, S29C31004T, 512, 128, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_49f002}, {"SyncMOS", "S29C51001T", SYNCMOS_ID, S29C51001T, 128, 128, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_49f002}, - {"SyncMOS", "S29C51002T", SYNCMOS_ID, S29C51002T, 256, 128, TEST_PREW, probe_jedec, erase_chip_jedec, write_49f002}, + {"SyncMOS", "S29C51002T", SYNCMOS_ID, S29C51002T, 256, 128, TEST_OK_PREW, probe_jedec, erase_chip_jedec, write_49f002}, {"SyncMOS", "S29C51004T", SYNCMOS_ID, S29C51004T, 512, 128, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_49f002}, {"Winbond", "W25x10", WINBOND_NEX_ID, W_25X10, 128, 256, TEST_UNTESTED, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"Winbond", "W25x20", WINBOND_NEX_ID, W_25X20, 256, 256, TEST_UNTESTED, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read},

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r241 - in buildrom-devel/packages: coreinfo libpayload libpayload/conf
by svn＠coreboot.org 29 Sep '08

29 Sep '08

Author: jcrouse Date: 2008-09-29 23:15:45 +0200 (Mon, 29 Sep 2008) New Revision: 241 Modified: buildrom-devel/packages/coreinfo/coreinfo.mk buildrom-devel/packages/libpayload/conf/defconfig buildrom-devel/packages/libpayload/conf/defconfig.geode buildrom-devel/packages/libpayload/libpayload.mk Log: buildrom: Update the versions for libpayload and coreinfo Signed-off-by: Jordan Crouse <jordan.crouse(a)amd.com> Acked-by: Jordan Crouse <jordan.crouse(a)amd.com> Modified: buildrom-devel/packages/coreinfo/coreinfo.mk =================================================================== --- buildrom-devel/packages/coreinfo/coreinfo.mk 2008-09-29 18:03:50 UTC (rev 240) +++ buildrom-devel/packages/coreinfo/coreinfo.mk 2008-09-29 21:15:45 UTC (rev 241) @@ -1,5 +1,5 @@ COREINFO_URL=svn://coreboot.org/repos/trunk/payloads/coreinfo -COREINFO_TAG=3561 +COREINFO_TAG=3613 COREINFO_DIR=$(BUILD_DIR)/coreinfo COREINFO_SRC_DIR=$(COREINFO_DIR)/svn Modified: buildrom-devel/packages/libpayload/conf/defconfig =================================================================== --- buildrom-devel/packages/libpayload/conf/defconfig 2008-09-29 18:03:50 UTC (rev 240) +++ buildrom-devel/packages/libpayload/conf/defconfig 2008-09-29 21:15:45 UTC (rev 241) @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # libpayload version: 0.1.0 -# Wed Sep 3 15:31:17 2008 +# Mon Sep 29 11:29:51 2008 # CONFIG_TARGET_I386=y @@ -22,6 +22,8 @@ CONFIG_VGA_VIDEO_CONSOLE=y # CONFIG_GEODE_VIDEO_CONSOLE is not set CONFIG_PC_KEYBOARD=y +CONFIG_PC_KEYBOARD_LAYOUT_US=y +# CONFIG_PC_KEYBOARD_LAYOUT_DE is not set # # Drivers Modified: buildrom-devel/packages/libpayload/conf/defconfig.geode =================================================================== --- buildrom-devel/packages/libpayload/conf/defconfig.geode 2008-09-29 18:03:50 UTC (rev 240) +++ buildrom-devel/packages/libpayload/conf/defconfig.geode 2008-09-29 21:15:45 UTC (rev 241) @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # libpayload version: 0.1.0 -# Wed Sep 3 15:41:25 2008 +# Mon Sep 29 15:13:33 2008 # CONFIG_TARGET_I386=y @@ -22,6 +22,8 @@ # CONFIG_VGA_VIDEO_CONSOLE is not set CONFIG_GEODE_VIDEO_CONSOLE=y CONFIG_PC_KEYBOARD=y +CONFIG_PC_KEYBOARD_LAYOUT_US=y +# CONFIG_PC_KEYBOARD_LAYOUT_DE is not set # # Drivers Modified: buildrom-devel/packages/libpayload/libpayload.mk =================================================================== --- buildrom-devel/packages/libpayload/libpayload.mk 2008-09-29 18:03:50 UTC (rev 240) +++ buildrom-devel/packages/libpayload/libpayload.mk 2008-09-29 21:15:45 UTC (rev 241) @@ -1,5 +1,5 @@ LIBPAYLOAD_URL=svn://coreboot.org/repos/trunk/payloads/libpayload -LIBPAYLOAD_TAG=3583 +LIBPAYLOAD_TAG=3613 LIBPAYLOAD_DIR=$(BUILD_DIR)/libpayload LIBPAYLOAD_SRC_DIR=$(LIBPAYLOAD_DIR)/svn

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flashrom: [PATCH] Fully working EON EN29F002NT
by Mats Erik Andersson 29 Sep '08

29 Sep '08

Subsystem: coreboot-v2/util/flashrom/ Action: activating support for EN29F002(A)(N)[BT] Fully tested for Probe/Read/Erase/Write on EN29F002NT. Jedec subroutines 'probe_jedec()' and 'erase_chip_jedec()' are still in use, but a tailored 'write_en29f002a()' is needed due to a byte wise writing mechanism for this chip. Signed-off by: Mats Erik Andersson <mats.andersson(a)gisladisker.se> --- The already existing file "util/flashrom/en29f002a.c" has been activated by including the needed header files, and it has been supplemented with a routine for writing, since the standard jedec routine for writing does not function for this chip. Also the old 'probe_en29f002a()' seems defect in my testing, but is left as it was. There has formally been incorporated a routine 'erase_en29f002a()' mostly for referencing from "flash.h", but it is never used since some obscure timing condition fails, whereas 'erase_chip_jedec()' indeed does function well for this chip. Only EN29F002(A)(N)T has been marked TEST_OK_PREW in "flash.c", since I have only checked a physical chip EN29F002NT, and have no further chip in my possession. Kind regards, Mats Erik Andersson Index: util/flashrom/flash.h =================================================================== --- util/flashrom/flash.h (revision 3578) +++ util/flashrom/flash.h (arbetskopia) @@ -435,6 +435,11 @@ int erase_29f040b(struct flashchip *flash); int write_29f040b(struct flashchip *flash, uint8_t *buf); +/* en29f002a.c */ +int probe_en29f002a(struct flashchip *flash); +int erase_en29f002a(struct flashchip *flash); +int write_en29f002a(struct flashchip *flash, uint8_t *buf); + /* ichspi.c */ int ich_spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int ich_spi_read(struct flashchip *flash, uint8_t * buf); Index: util/flashrom/en29f002a.c =================================================================== --- util/flashrom/en29f002a.c (revision 3578) +++ util/flashrom/en29f002a.c (arbetskopia) @@ -25,6 +25,11 @@ EN29LV010 has 1C,6E and uses short F0 reset sequence EN29LV040(A) has 1C,4F and uses short F0 reset sequence */ + +#include <stdio.h> +#include <stdint.h> +#include "flash.h" + int probe_en29f512(struct flashchip *flash) { volatile uint8_t *bios = flash->virtual_memory; @@ -56,6 +61,8 @@ EN29F002AT has 1C,92 EN29F002AB has 1C,97 */ + /* MEA: This does not function properly for EN29F002NT */ + int probe_en29f002a(struct flashchip *flash) { volatile uint8_t *bios = flash->virtual_memory; @@ -83,3 +90,36 @@ return 0; } +/* The EN29F002 chip needs repeated single byte writing, no block writing. */ + +int write_en29f002a(struct flashchip *flash, uint8_t *buf) +{ + int i; + int total_size = flash->total_size * 1024; + volatile uint8_t *bios = flash->virtual_memory; + volatile uint8_t *dst = bios; + + // *bios = 0xF0; + myusec_delay(10); + erase_chip_jedec(flash); + + printf("Programming page: "); + for (i = 0; i < total_size; i++) { + /* write to the sector */ + if ((i & 0xfff) == 0) + printf("address: 0x%08lx", (unsigned long)i); + *(bios + 0x5555) = 0xAA; + *(bios + 0x2AAA) = 0x55; + *(bios + 0x5555) = 0xA0; + *dst++ = *buf++; + + /* wait for Toggle bit ready */ + toggle_ready_jedec(dst); + + if ((i & 0xfff) == 0) + printf("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b"); + } + + printf("\n"); + return 0; +} Index: util/flashrom/flashchips.c =================================================================== --- util/flashrom/flashchips.c (revision 3578) +++ util/flashrom/flashchips.c (arbetskopia) @@ -47,8 +47,8 @@ {"AMIC", "A29040B", AMIC_ID_NOPREFIX, AMIC_A29040B, 512, 64 * 1024, TEST_OK_PR, probe_29f040b, erase_29f040b, write_29f040b}, {"AMIC", "A49LF040A", AMIC_ID_NOPREFIX, AMIC_A49LF040A, 512, 64 * 1024, TEST_OK_PREW, probe_49fl00x, erase_49fl00x, write_49fl00x}, {"EMST", "F49B002UA", EMST_ID, EMST_F49B002UA, 256, 4096, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_49f002}, - {"EON", "EN29F002(A)(N)B", EON_ID, EN_29F002B, 256, 256, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, - {"EON", "EN29F002(A)(N)T", EON_ID, EN_29F002T, 256, 256, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, + {"EON", "EN29F002(A)(N)B", EON_ID, EN_29F002B, 256, 256, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_en29f002a}, + {"EON", "EN29F002(A)(N)T", EON_ID, EN_29F002T, 256, 256, TEST_OK_PREW, probe_jedec, erase_chip_jedec, write_en29f002a}, {"Fujitsu", "MBM29F400TC", FUJITSU_ID, MBM29F400TC_STRANGE, 512, 64 * 1024, TEST_UNTESTED, probe_m29f400bt, erase_m29f400bt, write_coreboot_m29f400bt}, {"Intel", "82802AB", INTEL_ID, 173, 512, 64 * 1024, TEST_OK_PREW, probe_82802ab, erase_82802ab, write_82802ab}, {"Intel", "82802AC", INTEL_ID, 172, 1024, 64 * 1024, TEST_OK_PREW, probe_82802ab, erase_82802ab, write_82802ab}, Index: util/flashrom/Makefile =================================================================== --- util/flashrom/Makefile (revision 3578) +++ util/flashrom/Makefile (arbetskopia) @@ -26,7 +26,7 @@ OBJS = chipset_enable.o board_enable.o udelay.o jedec.o stm50flw0x0x.o \ sst28sf040.o am29f040b.o mx29f002.o sst39sf020.o m29f400bt.o \ - w49f002u.o 82802ab.o pm49fl00x.o sst49lf040.o \ + w49f002u.o 82802ab.o pm49fl00x.o sst49lf040.o en29f002a.o \ sst49lfxxxc.o sst_fwhub.o layout.o cbtable.o flashchips.o \ flashrom.o w39v080fa.o sharplhf00l04.o w29ee011.o spi.o it87spi.o \ ichspi.o w39v040c.o

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r3615 build service
by coreboot information 29 Sep '08

29 Sep '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "uwe" checked in revision 3615 to the coreboot source repository and caused the following changes: Change Log: Mark the SyncMOS S29C51002T as working (trivial). All operations tested by me on hardware. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of amd:serengeti_cheetah is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3615&device=serengeti_chee… Compilation of asus:m2v-mx_se is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3615&device=m2v-mx_se&vend… Compilation of jetway:j7f24 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3615&device=j7f24&vendor=j… Compilation of msi:ms9185 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3615&device=ms9185&vendor=… Compilation of msi:ms9282 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3615&device=ms9282&vendor=… Compilation of supermicro:h8dmr is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3615&device=h8dmr&vendor=s… Compilation of via:epia-cn is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3615&device=epia-cn&vendor… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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libpayload
by ron minnich 29 Sep '08

29 Sep '08

r774, make menuconfig compiles like this: gcc -m32 -Wall -Werror -fno-stack-protector -nostdinc -Iinclude -Ibuild -I/usr/lib64/gcc/x86_64-caos-linux-gnu/4.3.0/include -ffreestanding -c -o /home/rminnich/i945/trunk/filo/libpayload/build/util/kconfig/lxdialog/checklist.o /home/rminnich/i945/trunk/filo/libpayload/util/kconfig/lxdialog/checklist.c -nostdinc? Fails badly on my platofrm as the includes in -I/usr/lib64/gcc/x86_64-caos-linux-gnu/4.3.0/include are pretty limited. Is caos wrong or is the build a little wrong? ron

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r3614 build service
by coreboot information 29 Sep '08

29 Sep '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "mjones" checked in revision 3614 to the coreboot source repository and caused the following changes: Change Log: This patch for the AMD K8 allows a single DIMM to be populated in the ChannelB slot. Previously a DIMM could only be populated in ChannelB if there was a DIMM already in ChannelA. This patch doesn't allow unmatched DIMMs to be populate in ChannelA and ChannelB. In an A & B configuration the DIMM must still be matched. Signed-off-by: Marc Jones <marc.jones(a)amd.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of amd:serengeti_cheetah has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3614&device=serengeti_chee… Compilation of asus:m2v-mx_se has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3614&device=m2v-mx_se&vend… Compilation of jetway:j7f24 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3614&device=j7f24&vendor=j… Compilation of msi:ms9185 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3614&device=ms9185&vendor=… Compilation of msi:ms9282 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3614&device=ms9282&vendor=… Compilation of supermicro:h8dmr is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3614&device=h8dmr&vendor=s… Compilation of via:epia-cn is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3614&device=epia-cn&vendor… If something broke during this checkin please be a pain in mjones's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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coreboot September 2008