coreboot September 2008

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415 discussions

flashrom patch: make AT49F002N(T) chip work
by Tim ter Laak 30 Sep '08

30 Sep '08

Hello all, This patch fixes support for the AT49F002N(T) chip in the flashrom tool. It replaces the write function to one based on write_byte_program_jedec() instead of write_page_write_jedec(), as this part does not support page programming. I have verified the NT variant to fully work now, and adjusted the test status accordingly. The N variant *should* also work with this patch, but remains untested. Signed-off-by: Tim ter Laak <timl(a)scintilla.utwente.nl> --- Like my previous patch, this one is also based inside the flashrom directory. Kind regards, Tim. Index: flashchips.c =================================================================== --- flashchips.c (revision 3559) +++ flashchips.c (working copy) @@ -38,8 +38,8 @@ {"ASD", "AE49F2008", ASD_ID, ASD_AE49F2008, 256, 128, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, {"Atmel", "AT29C020", ATMEL_ID, AT_29C020, 256, 256, TEST_OK_PREW, probe_jedec, erase_chip_jedec, write_jedec}, {"Atmel", "AT29C040A", ATMEL_ID, AT_29C040A, 512, 256, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, - {"Atmel", "AT49F002(N)", ATMEL_ID, AT_49F002N, 256, 256, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, - {"Atmel", "AT49F002(N)T", ATMEL_ID, AT_49F002NT, 256, 256, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, + {"Atmel", "AT49F002(N)", ATMEL_ID, AT_49F002N, 256, 256, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_49f002}, + {"Atmel", "AT49F002(N)T", ATMEL_ID, AT_49F002NT, 256, 256, TEST_OK_PREW, probe_jedec, erase_chip_jedec, write_49f002}, {"Atmel", "AT25DF321", ATMEL_ID, AT_25DF321, 4096, 256, TEST_OK_PREW, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"AMIC", "A25L40P", AMIC_ID, AMIC_A25L40P, 512, 256, TEST_OK_PREW, probe_spi_rdid4, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"AMIC", "A29002B", AMIC_ID_NOPREFIX, AMIC_A29002B, 256, 64 * 1024, TEST_UNTESTED, probe_29f002, erase_29f002, write_29f002},

2 1

r3619 - trunk/util/flashrom
by svn＠coreboot.org 30 Sep '08

30 Sep '08

Author: stuge Date: 2008-09-30 06:13:32 +0200 (Tue, 30 Sep 2008) New Revision: 3619 Modified: trunk/util/flashrom/flashchips.c Log: This patch fixes support for the AT49F002N(T) chip in the flashrom tool. It replaces the write function to one based on write_byte_program_jedec() instead of write_page_write_jedec(), as this part does not support page programming. I have verified the NT variant to fully work now, and adjusted the test status accordingly. The N variant *should* also work with this patch, but remains untested. Signed-off-by: Tim ter Laak <timl(a)scintilla.utwente.nl> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/util/flashrom/flashchips.c =================================================================== --- trunk/util/flashrom/flashchips.c 2008-09-30 04:00:23 UTC (rev 3618) +++ trunk/util/flashrom/flashchips.c 2008-09-30 04:13:32 UTC (rev 3619) @@ -38,8 +38,8 @@ {"ASD", "AE49F2008", ASD_ID, ASD_AE49F2008, 256, 128, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, {"Atmel", "AT29C020", ATMEL_ID, AT_29C020, 256, 256, TEST_OK_PREW, probe_jedec, erase_chip_jedec, write_jedec}, {"Atmel", "AT29C040A", ATMEL_ID, AT_29C040A, 512, 256, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, - {"Atmel", "AT49F002(N)", ATMEL_ID, AT_49F002N, 256, 256, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, - {"Atmel", "AT49F002(N)T", ATMEL_ID, AT_49F002NT, 256, 256, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, + {"Atmel", "AT49F002(N)", ATMEL_ID, AT_49F002N, 256, 256, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_49f002}, + {"Atmel", "AT49F002(N)T", ATMEL_ID, AT_49F002NT, 256, 256, TEST_OK_PREW, probe_jedec, erase_chip_jedec, write_49f002}, {"Atmel", "AT25DF321", ATMEL_ID, AT_25DF321, 4096, 256, TEST_OK_PREW, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"AMIC", "A25L40P", AMIC_ID, AMIC_A25L40P, 512, 256, TEST_OK_PREW, probe_spi_rdid4, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"AMIC", "A29002B", AMIC_ID_NOPREFIX, AMIC_A29002B, 256, 64 * 1024, TEST_UNTESTED, probe_29f002, erase_29f002, write_29f002},

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r3618 - trunk/util/flashrom
by svn＠coreboot.org 30 Sep '08

30 Sep '08

Author: stuge Date: 2008-09-30 06:00:23 +0200 (Tue, 30 Sep 2008) New Revision: 3618 Modified: trunk/util/flashrom/flashchips.c Log: flashrom: ST M29F040B status TEST_OK_ PROBE READ ERASE WRITE Per report from Daniel Lindenaar. Thanks! Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/util/flashrom/flashchips.c =================================================================== --- trunk/util/flashrom/flashchips.c 2008-09-29 22:59:23 UTC (rev 3617) +++ trunk/util/flashrom/flashchips.c 2008-09-30 04:00:23 UTC (rev 3618) @@ -106,7 +106,7 @@ {"ST", "M25P128", ST_ID, ST_M25P128, 16384, 256, TEST_UNTESTED, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"ST", "M29F002B", ST_ID, ST_M29F002B, 256, 64 * 1024, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, {"ST", "M29F002T/NT", ST_ID, ST_M29F002T, 256, 64 * 1024, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, - {"ST", "M29F040B", ST_ID, ST_M29F040B, 512, 64 * 1024, TEST_UNTESTED, probe_29f040b, erase_29f040b, write_29f040b}, + {"ST", "M29F040B", ST_ID, ST_M29F040B, 512, 64 * 1024, TEST_OK_PREW, probe_29f040b, erase_29f040b, write_29f040b}, {"ST", "M29F400BT", ST_ID, ST_M29F400BT, 512, 64 * 1024, TEST_UNTESTED, probe_m29f400bt, erase_m29f400bt, write_coreboot_m29f400bt}, {"ST", "M29W010B", ST_ID, ST_M29W010B, 128, 16 * 1024, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, {"ST", "M29W040B", ST_ID, ST_M29W040B, 512, 64 * 1024, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec},

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The patch of AMD DBM690T board
by Xie, Michael 30 Sep '08

30 Sep '08

Hi, The attachment is the patch for AMD DBM690T board. Signed-off-by: Michael Xie Michael.Xie(a)amd.com Reviewed-by: Marc Jones <marc.jones(a)amd.com> <<dbm690t.patch>>

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[PATCH]filo and libpayload: Support Solaris in kconfig
by Patrick Georgi 30 Sep '08

30 Sep '08

Hi, the following patch can be applied both to filo-0.6b and libpayload, and is one of several changes to make things build on solaris. The changes: 1. Preset CC to gcc in Makefile. There are some $(shell $(CC) ...) invocations with GCC specific options, so that shouldn't hurt. 2. Replace stdbool.h include in util/kconfig/expr.h by a custom implementation of booleans. This is okay as these booleans are purely internal. It's necessary because there's some disagreement between the Solaris headers and GCC on Solaris, about when stdbool.h is appropriate. 3. Remove stdbool.h include from util/kconfig/zconf.tab.c_shipped. This file includes expr.h already, so it picks up the right set of primitives, without duplicating the special case for Solaris. Comments? Patrick Georgi

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Re: [coreboot] r3616 - trunk/util/flashrom
by Uwe Hermann 30 Sep '08

30 Sep '08

On Mon, Sep 29, 2008 at 11:21:36PM +0200, svn(a)coreboot.org wrote: > flashrom: Fix typo in r3615 (TEST_PREW -> TEST_OK_PREW) > > Signed-off-by: Peter Stuge <peter(a)stuge.se> > Acked-by: Peter Stuge <peter(a)stuge.se> Oops, my fault. Thanks for fixing this. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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r3617 build service
by coreboot information 30 Sep '08

30 Sep '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "mjones" checked in revision 3617 to the coreboot source repository and caused the following changes: Change Log: AMD K8 platforms must use CAR so it makes sense to use the PRINK_IN_CAR option. This patch converts the following patches to use PRTINK_IN_CAR amd/serngeti_cheetah msi/ms9185 msi/ms9828 supermicro/h8dmr Signed-off-by: Marc Jones <marc.jones(a)amd.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Build Log: Compilation of amd:serengeti_cheetah has been fixed Compilation of asus:m2v-mx_se is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3617&device=m2v-mx_se&vend… Compilation of jetway:j7f24 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3617&device=j7f24&vendor=j… Compilation of msi:ms9185 has been fixed Compilation of msi:ms9282 has been fixed Compilation of supermicro:h8dmr has been fixed Compilation of via:epia-cn is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3617&device=epia-cn&vendor… If something broke during this checkin please be a pain in mjones's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[patch] K8 platforms should use PRINTK_IN_CAR
by Marc Jones 30 Sep '08

30 Sep '08

This fixes the four platforms that the recent K8 changes broke. Thanks, Marc -- Marc Jones Senior Firmware Engineer (970) 226-9684 Office mailto:Marc.Jones@amd.com http://www.amd.com/embeddedprocessors AMD K8 platforms must use CAR so it makes sense to use the PRINK_IN_CAR option. This patch converts the following patches to use PRTINK_IN_CAR amd/serngeti_cheetah msi/ms9185 msi/ms9828 supermicro/h8dmr Signed-off-by: Marc Jones <marc.jones(a)amd.com> Index: coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/amd/serengeti_cheetah/Options.lb 2008-09-29 16:05:06.000000000 -0600 +++ coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb 2008-09-29 15:07:22.000000000 -0600 @@ -286,7 +286,7 @@ ## ## The Serial Console ## -default CONFIG_USE_PRINTK_IN_CAR=0 +default CONFIG_USE_PRINTK_IN_CAR=1 # To Enable the Serial Console default CONFIG_CONSOLE_SERIAL8250=1 Index: coreboot-v2/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c =================================================================== --- coreboot-v2.orig/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c 2008-09-29 16:09:17.000000000 -0600 +++ coreboot-v2/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c 2008-09-29 15:15:47.000000000 -0600 @@ -33,6 +33,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" + #if 0 static void post_code(uint8_t value) { #if 1 @@ -64,11 +65,6 @@ #if CONFIG_USE_INIT == 0 #include "lib/memcpy.c" - #if CONFIG_USE_PRINTK_IN_CAR == 1 - #include "lib/uart8250.c" - #include "console/vtxprintf.c" - #include "arch/i386/lib/printk_init.c" - #endif #endif #include "northbridge/amd/amdk8/debug.c" #include "cpu/amd/mtrr/amd_earlymtrr.c" Index: coreboot-v2/src/mainboard/amd/serengeti_cheetah/apc_auto.c =================================================================== --- coreboot-v2.orig/src/mainboard/amd/serengeti_cheetah/apc_auto.c 2008-09-29 16:17:07.000000000 -0600 +++ coreboot-v2/src/mainboard/amd/serengeti_cheetah/apc_auto.c 2008-09-29 15:16:43.000000000 -0600 @@ -24,11 +24,6 @@ #if CONFIG_USE_INIT == 0 #include "lib/memcpy.c" - #if CONFIG_USE_PRINTK_IN_CAR == 1 - #include "lib/uart8250.c" - #include "console/vtxprintf.c" - #include "arch/i386/lib/printk_init.c" - #endif #endif #include "arch/i386/lib/console.c" Index: coreboot-v2/src/mainboard/msi/ms9185/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/msi/ms9185/Options.lb 2008-09-29 16:18:48.000000000 -0600 +++ coreboot-v2/src/mainboard/msi/ms9185/Options.lb 2008-09-29 15:21:44.000000000 -0600 @@ -104,7 +104,7 @@ uses CONFIG_PCI_64BIT_PREF_MEM uses CONFIG_LB_MEM_TOPK - +uses CONFIG_USE_PRINTK_IN_CAR ### ### Build options @@ -222,7 +222,7 @@ default DCACHE_RAM_BASE=0xcc000 default DCACHE_RAM_SIZE=0x04000 default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 -default CONFIG_USE_INIT=0 +default CONFIG_USE_INIT=0 ## ## Build code to setup a generic IOAPIC @@ -287,6 +287,7 @@ ## ## The Serial Console ## +default CONFIG_USE_PRINTK_IN_CAR=1 # To Enable the Serial Console default CONFIG_CONSOLE_SERIAL8250=1 Index: coreboot-v2/src/mainboard/msi/ms9282/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/msi/ms9282/Options.lb 2008-09-29 16:28:46.000000000 -0600 +++ coreboot-v2/src/mainboard/msi/ms9282/Options.lb 2008-09-29 15:22:01.000000000 -0600 @@ -100,6 +100,7 @@ uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_PRECOMPRESSED_PAYLOAD +uses CONFIG_USE_PRINTK_IN_CAR ## ROM_SIZE is the size of boot ROM that this board will use. #512K bytes @@ -203,7 +204,6 @@ default APIC_ID_OFFSET=0x10 default LIFT_BSP_APIC_ID=0 - ## ## Build code to setup a generic IOAPIC ## @@ -267,7 +267,8 @@ ## ## The Serial Console ## - +default CONFIG_USE_PRINTK_IN_CAR=1 + # To Enable the Serial Console default CONFIG_CONSOLE_SERIAL8250=1 Index: coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/supermicro/h8dmr/Options.lb 2008-09-29 16:35:16.000000000 -0600 +++ coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb 2008-09-29 15:21:14.000000000 -0600 @@ -236,7 +236,7 @@ default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 default CONFIG_USE_INIT=0 -default CONFIG_AP_CODE_IN_CAR=0 +default CONFIG_AP_CODE_IN_CAR=1 default MEM_TRAIN_SEQ=1 default WAIT_BEFORE_CPUS_INIT=1 @@ -305,7 +305,7 @@ ## ## The Serial Console ## -default CONFIG_USE_PRINTK_IN_CAR=0 +default CONFIG_USE_PRINTK_IN_CAR=1 # To Enable the Serial Console default CONFIG_CONSOLE_SERIAL8250=1 Index: coreboot-v2/targets/supermicro/h8dmr/Config-abuild.lb =================================================================== --- coreboot-v2.orig/targets/supermicro/h8dmr/Config-abuild.lb 2008-09-29 16:39:33.000000000 -0600 +++ coreboot-v2/targets/supermicro/h8dmr/Config-abuild.lb 2008-09-29 15:39:57.000000000 -0600 @@ -12,7 +12,7 @@ romimage "normal" option USE_FAILOVER_IMAGE=0 option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x18000 + option ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end @@ -20,7 +20,7 @@ romimage "fallback" option USE_FAILOVER_IMAGE=0 option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x18000 + option ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end

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r3617 - in trunk/coreboot-v2: src/mainboard/amd/serengeti_cheetah src/mainboard/msi/ms9185 src/mainboard/msi/ms9282 src/mainboard/supermicro/h8dmr targets/supermicro/h8dmr
by svn＠coreboot.org 30 Sep '08

30 Sep '08

Author: mjones Date: 2008-09-30 00:59:23 +0200 (Tue, 30 Sep 2008) New Revision: 3617 Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/apc_auto.c trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/msi/ms9185/Options.lb trunk/coreboot-v2/src/mainboard/msi/ms9282/Options.lb trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb trunk/coreboot-v2/targets/supermicro/h8dmr/Config-abuild.lb Log: AMD K8 platforms must use CAR so it makes sense to use the PRINK_IN_CAR option. This patch converts the following patches to use PRTINK_IN_CAR amd/serngeti_cheetah msi/ms9185 msi/ms9828 supermicro/h8dmr Signed-off-by: Marc Jones <marc.jones(a)amd.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb 2008-09-29 21:21:36 UTC (rev 3616) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb 2008-09-29 22:59:23 UTC (rev 3617) @@ -286,7 +286,7 @@ ## ## The Serial Console ## -default CONFIG_USE_PRINTK_IN_CAR=0 +default CONFIG_USE_PRINTK_IN_CAR=1 # To Enable the Serial Console default CONFIG_CONSOLE_SERIAL8250=1 Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/apc_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/apc_auto.c 2008-09-29 21:21:36 UTC (rev 3616) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/apc_auto.c 2008-09-29 22:59:23 UTC (rev 3617) @@ -24,11 +24,6 @@ #if CONFIG_USE_INIT == 0 #include "lib/memcpy.c" - #if CONFIG_USE_PRINTK_IN_CAR == 1 - #include "lib/uart8250.c" - #include "console/vtxprintf.c" - #include "arch/i386/lib/printk_init.c" - #endif #endif #include "arch/i386/lib/console.c" Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c 2008-09-29 21:21:36 UTC (rev 3616) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c 2008-09-29 22:59:23 UTC (rev 3617) @@ -33,6 +33,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" + #if 0 static void post_code(uint8_t value) { #if 1 @@ -64,11 +65,6 @@ #if CONFIG_USE_INIT == 0 #include "lib/memcpy.c" - #if CONFIG_USE_PRINTK_IN_CAR == 1 - #include "lib/uart8250.c" - #include "console/vtxprintf.c" - #include "arch/i386/lib/printk_init.c" - #endif #endif #include "northbridge/amd/amdk8/debug.c" #include "cpu/amd/mtrr/amd_earlymtrr.c" Modified: trunk/coreboot-v2/src/mainboard/msi/ms9185/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms9185/Options.lb 2008-09-29 21:21:36 UTC (rev 3616) +++ trunk/coreboot-v2/src/mainboard/msi/ms9185/Options.lb 2008-09-29 22:59:23 UTC (rev 3617) @@ -104,8 +104,8 @@ uses CONFIG_PCI_64BIT_PREF_MEM uses CONFIG_LB_MEM_TOPK +uses CONFIG_USE_PRINTK_IN_CAR - ### ### Build options ### @@ -222,7 +222,7 @@ default DCACHE_RAM_BASE=0xcc000 default DCACHE_RAM_SIZE=0x04000 default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 -default CONFIG_USE_INIT=0 +default CONFIG_USE_INIT=0 ## ## Build code to setup a generic IOAPIC @@ -287,6 +287,7 @@ ## ## The Serial Console ## +default CONFIG_USE_PRINTK_IN_CAR=1 # To Enable the Serial Console default CONFIG_CONSOLE_SERIAL8250=1 Modified: trunk/coreboot-v2/src/mainboard/msi/ms9282/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/msi/ms9282/Options.lb 2008-09-29 21:21:36 UTC (rev 3616) +++ trunk/coreboot-v2/src/mainboard/msi/ms9282/Options.lb 2008-09-29 22:59:23 UTC (rev 3617) @@ -100,6 +100,7 @@ uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_PRECOMPRESSED_PAYLOAD +uses CONFIG_USE_PRINTK_IN_CAR ## ROM_SIZE is the size of boot ROM that this board will use. #512K bytes @@ -203,7 +204,6 @@ default APIC_ID_OFFSET=0x10 default LIFT_BSP_APIC_ID=0 - ## ## Build code to setup a generic IOAPIC ## @@ -267,7 +267,8 @@ ## ## The Serial Console ## - +default CONFIG_USE_PRINTK_IN_CAR=1 + # To Enable the Serial Console default CONFIG_CONSOLE_SERIAL8250=1 Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb 2008-09-29 21:21:36 UTC (rev 3616) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb 2008-09-29 22:59:23 UTC (rev 3617) @@ -236,7 +236,7 @@ default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 default CONFIG_USE_INIT=0 -default CONFIG_AP_CODE_IN_CAR=0 +default CONFIG_AP_CODE_IN_CAR=1 default MEM_TRAIN_SEQ=1 default WAIT_BEFORE_CPUS_INIT=1 @@ -305,7 +305,7 @@ ## ## The Serial Console ## -default CONFIG_USE_PRINTK_IN_CAR=0 +default CONFIG_USE_PRINTK_IN_CAR=1 # To Enable the Serial Console default CONFIG_CONSOLE_SERIAL8250=1 Modified: trunk/coreboot-v2/targets/supermicro/h8dmr/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/supermicro/h8dmr/Config-abuild.lb 2008-09-29 21:21:36 UTC (rev 3616) +++ trunk/coreboot-v2/targets/supermicro/h8dmr/Config-abuild.lb 2008-09-29 22:59:23 UTC (rev 3617) @@ -12,7 +12,7 @@ romimage "normal" option USE_FAILOVER_IMAGE=0 option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x18000 + option ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-normal" payload __PAYLOAD__ end @@ -20,7 +20,7 @@ romimage "fallback" option USE_FAILOVER_IMAGE=0 option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x18000 + option ROM_IMAGE_SIZE=0x20000 option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end

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[FILO] #11: default boot parameters taken from autoboot command
by FILO 30 Sep '08

30 Sep '08

#11: default boot parameters taken from autoboot command ------------------------------------+--------------------------------------- Reporter: hawke(a)hawkesnest.net | Owner: somebody Type: defect | Status: new Priority: minor | Milestone: Component: FILO | Version: Keywords: | Dependencies: Patchstatus: there is no patch | ------------------------------------+--------------------------------------- It would be great if a 'boot' before any kernel/initrd/root commands would by default use the autoboot command compiled in to filo. those commands could override the relevant portions of the default. So if the autoboot command is 'hda1:/vmlinuz initrd=hde1:/initrd.img console=ttyS0', a 'root hde1:' followed by 'boot' would boot the commandline 'hde1:/vmlinuz initrd=hde1:/initrd.img console=ttyS0' -- Ticket URL: <http://tracker.coreboot.org/trac/filo/ticket/11> FILO <http://www.coreboot.org/FILO>

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coreboot September 2008