Author: uwe Date: 2008-09-30 17:02:40 +0200 (Tue, 30 Sep 2008) New Revision: 3622
Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/Config.lb trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb trunk/coreboot-v2/src/mainboard/asus/a8n_e/cache_as_ram_auto.c trunk/coreboot-v2/src/mainboard/asus/a8n_e/get_bus_conf.c trunk/coreboot-v2/src/mainboard/asus/a8n_e/irq_tables.c trunk/coreboot-v2/src/mainboard/asus/a8n_e/mptable.c trunk/coreboot-v2/targets/asus/a8n_e/Config.lb Log: Coding-style fixes and simplifications for the ASUS A8N-E (trivial). The only non-cosmetic change is s/A8NE/A8N-E/ for the board name. This is build-tested by me.
Signed-off-by: Uwe Hermann uwe@hermann-uwe.de Acked-by: Uwe Hermann uwe@hermann-uwe.de
Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8n_e/Config.lb 2008-09-30 06:13:54 UTC (rev 3621) +++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/Config.lb 2008-09-30 15:02:40 UTC (rev 3622) @@ -21,10 +21,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-## -## Compute the location and size of where this firmware image -## (coreboot plus bootloader) will live in the boot rom chip. -## if USE_FAILOVER_IMAGE default ROM_SECTION_SIZE = FAILOVER_SIZE default ROM_SECTION_OFFSET = (ROM_SIZE - FAILOVER_SIZE) @@ -37,27 +33,12 @@ default ROM_SECTION_OFFSET = 0 end end - -## -## Compute the start location and size size of the coreboot bootloader. -## default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) - -## -## Compute where this copy of coreboot will start in the boot ROM. -## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) - -## -## Compute a range of ROM that can be cached to speed up coreboot -## execution speed. -## -## XIP_ROM_SIZE must be a power of 2 (here 64 Kbyte) -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE -## -default XIP_ROM_SIZE = (64 * 1024) - +default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) +# XIP_ROM_SIZE must be a power of 2. +# XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE. +default XIP_ROM_SIZE = 64 * 1024 if USE_FAILOVER_IMAGE default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) else @@ -67,28 +48,12 @@ default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) end end - arch i386 end - -## -## Build the objects we have code for in this directory. -## - driver mainboard.o - -#dir /drivers/ati/ragexl - # Needed by irq_tables and mptable and acpi_tables. object get_bus_conf.o - -if HAVE_MP_TABLE - object mptable.o -end - -if HAVE_PIRQ_TABLE - object irq_tables.o -end - +if HAVE_MP_TABLE object mptable.o end +if HAVE_PIRQ_TABLE object irq_tables.o end if USE_DCACHE_RAM if CONFIG_USE_INIT makerule ./auto.o @@ -104,10 +69,6 @@ end end end - -## -## Build our 16 bit and 32 bit coreboot entry code. -## if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/entry16.inc @@ -119,19 +80,13 @@ ldscript /cpu/x86/16bit/entry16.lds end end - mainboardinit cpu/x86/32bit/entry32.inc - if USE_DCACHE_RAM if CONFIG_USE_INIT ldscript /cpu/x86/32bit/entry32.lds ldscript /cpu/amd/car/cache_as_ram.lds end end - -## -## Build our reset vector (this is where coreboot is entered). -## if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -149,22 +104,14 @@ ldscript /cpu/x86/32bit/reset32.lds end end - if USE_DCACHE_RAM else - ### Should this be in the northbridge code? mainboardinit arch/i386/lib/cpu_reset.inc end - -## -## Include an ID string (for safe flashing). -## +# Include an ID string (for safe flashing). mainboardinit southbridge/nvidia/ck804/id.inc ldscript /southbridge/nvidia/ck804/id.lds - -## -## ROMSTRAP table for CK804 -## +# ROMSTRAP table for CK804. if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE mainboardinit southbridge/nvidia/ck804/romstrap.inc @@ -176,20 +123,9 @@ ldscript /southbridge/nvidia/ck804/romstrap.lds end end - if USE_DCACHE_RAM - ## - ## Setup Cache-As-Ram - ## mainboardinit cpu/amd/car/cache_as_ram.inc end - - -### -### This is the early phase of coreboot startup. -### Things are delicate and we test to see if we should -### failover to another image. -### if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE if USE_DCACHE_RAM @@ -203,14 +139,6 @@ end end end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## if USE_DCACHE_RAM if CONFIG_USE_INIT initobject auto.o @@ -218,10 +146,6 @@ mainboardinit ./auto.inc end end - -## -## Include the secondary configuration files -## if CONFIG_CHIP_NAME config chip.h end
Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb 2008-09-30 06:13:54 UTC (rev 3621) +++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb 2008-09-30 15:02:40 UTC (rev 3622) @@ -80,7 +80,6 @@ uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN uses HW_MEM_HOLE_SIZEK - uses USE_DCACHE_RAM uses DCACHE_RAM_BASE uses DCACHE_RAM_SIZE @@ -89,233 +88,81 @@ uses CONFIG_AP_CODE_IN_CAR uses MEM_TRAIN_SEQ uses WAIT_BEFORE_CPUS_INIT - uses ENABLE_APIC_EXT_ID uses APIC_ID_OFFSET uses LIFT_BSP_APIC_ID - uses CONFIG_PCI_64BIT_PREF_MEM - uses HT_CHAIN_UNITID_BASE uses HT_CHAIN_END_UNITID_BASE uses SB_HT_CHAIN_ON_BUS0 uses SB_HT_CHAIN_UNITID_OFFSET_ONLY - uses CONFIG_LB_MEM_TOPK
- -## ROM_SIZE is the size of boot ROM that this board will use. -## ---> 512 Kbytes -default ROM_SIZE=(512*1024) - -## -## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use -## -default FALLBACK_SIZE=(252*1024) - -#FAILOVER: 4K -default FAILOVER_SIZE=(4*1024) - -### -### Build options -### - -## -## Build code for the fallback boot -## -default HAVE_FALLBACK_BOOT=1 -default HAVE_FAILOVER_BOOT=1 - -## -## Build code to reset the motherboard from coreboot -## -default HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=13 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default HAVE_MP_TABLE=1 - -## -## Build code to export a CMOS option table -## -default HAVE_OPTION_TABLE=1 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default LB_CKS_RANGE_START=49 -default LB_CKS_RANGE_END=122 -default LB_CKS_LOC=123 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=2 -default CONFIG_MAX_PHYSICAL_CPUS=1 -default CONFIG_LOGICAL_CPUS=1 - -#1G memory hole -default HW_MEM_HOLE_SIZEK=0x100000 - -##HT Unit ID offset, default is 1, the typical one -default HT_CHAIN_UNITID_BASE=0 - -##real SB Unit ID, default is 0x20, mean dont touch it at last -#default HT_CHAIN_END_UNITID_BASE=0x10 - -#make the SB HT chain on bus 0, default is not (0) -default SB_HT_CHAIN_ON_BUS0=2 - -##only offset for SB chain?, default is yes(1) -default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 - -#BTEXT Console -#default CONFIG_CONSOLE_BTEXT=1 - -#VGA Console -default CONFIG_CONSOLE_VGA=1 -default CONFIG_PCI_ROM_RUN=1 - -## -## enable CACHE_AS_RAM specifics -## -default USE_DCACHE_RAM=1 -#default DCACHE_RAM_BASE=0xcf000 -#default DCACHE_RAM_SIZE=0x1000 -default DCACHE_RAM_BASE=0xc8000 -default DCACHE_RAM_SIZE=0x08000 -default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 -default CONFIG_USE_INIT=0 - -default CONFIG_AP_CODE_IN_CAR=0 -default MEM_TRAIN_SEQ=2 -default WAIT_BEFORE_CPUS_INIT=0 - -## APIC stuff -#default ENABLE_APIC_EXT_ID=0 -#default APIC_ID_OFFSET=0x10 -#default LIFT_BSP_APIC_ID=0 - - -#default CONFIG_PCI_64BIT_PREF_MEM=1 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default MAINBOARD_PART_NUMBER="A8NE" -default MAINBOARD_VENDOR="ASUS" -default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 -default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2891 - -### -### coreboot layout values -### - -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = (64*1024) -#65536 - -## -## Use a small 8K stack -## -default STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -#efault USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE ) - -## -## Coreboot C code runs at this location in RAM -## -default _RAMBASE=0x00004000 - -## -## Load the payload from the ROM -## +default ROM_SIZE = 512 * 1024 +default ROM_IMAGE_SIZE = 64 * 1024 +default FALLBACK_SIZE = 252 * 1024 +default FAILOVER_SIZE = 4 * 1024 +default HAVE_FALLBACK_BOOT = 1 +default HAVE_FAILOVER_BOOT = 1 +default HAVE_HARD_RESET = 1 +default HAVE_PIRQ_TABLE = 1 +default IRQ_SLOT_COUNT = 13 +default HAVE_MP_TABLE = 1 +default HAVE_OPTION_TABLE = 1 +# Move the default coreboot CMOS range off of AMD RTC registers. +default LB_CKS_RANGE_START = 49 +default LB_CKS_RANGE_END = 122 +default LB_CKS_LOC = 123 +# SMP support (only worry about 2 micro processors). +default CONFIG_SMP = 1 +default CONFIG_MAX_CPUS = 2 +default CONFIG_MAX_PHYSICAL_CPUS = 1 +default CONFIG_LOGICAL_CPUS = 1 +# 1G memory hole. +default HW_MEM_HOLE_SIZEK = 0x100000 +# HT Unit ID offset, default is 1, the typical one. +default HT_CHAIN_UNITID_BASE = 0 +# Real SB Unit ID, default is 0x20, mean don't touch it at last. +# default HT_CHAIN_END_UNITID_BASE = 0x10 +# Make the SB HT chain on bus 0, default is not (0). +default SB_HT_CHAIN_ON_BUS0 = 2 +# Only offset for SB chain?, default is yes(1). +default SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0 +# default CONFIG_CONSOLE_BTEXT = 1 # BTEXT console +default CONFIG_CONSOLE_VGA = 1 # For VGA console +default CONFIG_PCI_ROM_RUN = 1 # For VGA console +default USE_DCACHE_RAM = 1 +default DCACHE_RAM_BASE = 0xc8000 +default DCACHE_RAM_SIZE = 32 * 1024 +default DCACHE_RAM_GLOBAL_VAR_SIZE = 4 * 1024 +default CONFIG_USE_INIT = 0 +default CONFIG_AP_CODE_IN_CAR = 0 +default MEM_TRAIN_SEQ = 2 +default WAIT_BEFORE_CPUS_INIT = 0 +# default ENABLE_APIC_EXT_ID = 0 +# default APIC_ID_OFFSET = 0x10 +# default LIFT_BSP_APIC_ID = 0 +# default CONFIG_PCI_64BIT_PREF_MEM = 1 +default CONFIG_IOAPIC = 1 +default MAINBOARD_PART_NUMBER = "A8N-E" +default MAINBOARD_VENDOR = "ASUS" +default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x10f1 +default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x2891 +default STACK_SIZE = 8 * 1024 +default HEAP_SIZE = 16 * 1024 +# Only use the option table in a normal image. +default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE) +default _RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 +default CC = "$(CROSS_COMPILE)gcc -m32" +default HOSTCC = "gcc" +default CONFIG_GDB_STUB = 0 +default CONFIG_CONSOLE_SERIAL8250 = 1 +default TTYS0_BAUD = 115200 +default TTYS0_BASE = 0x3f8 +default TTYS0_LCS = 0x3 +default DEFAULT_CONSOLE_LOGLEVEL = 8 +default MAXIMUM_CONSOLE_LOGLEVEL = 8 +default MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON"
-### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default TTYS0_BAUD=115200 -#default TTYS0_BAUD=57600 -#default TTYS0_BAUD=38400 -#default TTYS0_BAUD=19200 -#default TTYS0_BAUD=9600 -#default TTYS0_BAUD=4800 -#default TTYS0_BAUD=2400 -#default TTYS0_BAUD=1200 - -# Select the serial console base port -default TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -### End Options.lb end
Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8n_e/cache_as_ram_auto.c 2008-09-30 06:13:54 UTC (rev 3621) +++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/cache_as_ram_auto.c 2008-09-30 15:02:40 UTC (rev 3622) @@ -76,17 +76,17 @@
static void memreset_setup(void) { - /* FIXME: Nothing to do? */ + /* Nothing to do. */ }
static void memreset(int controllers, const struct mem_controller *ctrl) { - /* FIXME: Nothing to do? */ + /* Nothing to do. */ }
static inline void activate_spd_rom(const struct mem_controller *ctrl) { - /* FIXME: Nothing to do? */ + /* Nothing to do. */ }
static inline int spd_read_byte(unsigned device, unsigned address) @@ -123,8 +123,7 @@
/* LPC Positive Decode 0 */ dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0); - /* Serial 0, Serial 1 */ - dword |= (1 << 0) | (1 << 1); + dword |= (1 << 0) | (1 << 1); /* Serial 0, Serial 1 */ pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0, dword); }
@@ -212,14 +211,11 @@ };
int needs_reset; - unsigned bsp_apicid = 0; - + unsigned nodes, bsp_apicid = 0; struct mem_controller ctrl[8]; - unsigned nodes;
- if (bist == 0) { + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx); - }
it8712f_24mhz_clkin(); it8712f_enable_serial(SERIAL_DEV, TTYS0_BASE); @@ -237,13 +233,12 @@
wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS==1 - // It is said that we should start core1 after all core0 launched + /* It is said that we should start core1 after all core0 launched. */ start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif
needs_reset |= ht_setup_chains_x(); - needs_reset |= ck804_early_setup_x();
if (needs_reset) { @@ -254,7 +249,7 @@ allow_all_aps_stop(bsp_apicid);
nodes = get_nodes(); - //It's the time to set ctrl now; + /* It's the time to set ctrl now. */ fill_mem_ctrl(nodes, ctrl, spd_addr);
enable_smbus();
Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/get_bus_conf.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8n_e/get_bus_conf.c 2008-09-30 06:13:54 UTC (rev 3621) +++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/get_bus_conf.c 2008-09-30 15:02:40 UTC (rev 3622) @@ -26,13 +26,14 @@ #include <device/pci_ids.h> #include <string.h> #include <stdint.h> +#include <stdlib.h> #if CONFIG_LOGICAL_CPUS == 1 #include <cpu/amd/dualcore.h> #endif - #include <cpu/amd/amdk8_sysconf.h>
-/* Global variables for MB layouts and these will be shared by irqtable, +/* + * Global variables for MB layouts and these will be shared by irqtable, * mptable and acpi_tables. */ /* busnum is default */ @@ -40,13 +41,23 @@ unsigned char bus_ck804[6]; unsigned apicid_ck804;
-unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not - //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail - 0x0000ff0, //no HTIO for a8n_e +/* + * Here you only need to set value in pci1234 for HT-IO that could be installed + * or not. You may need to preset pci1234 for HT-IO board, please refer to + * src/northbridge/amd/amdk8/get_sblk_pci1234.c for details. + */ +unsigned pci1234x[] = { + 0x0000ff0, /* No HTIO for A8N-E */ }; -unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most - 0x20202020, //a8n_e has only one ht-chain + +/* + * HT Chain device num, actually it is unit id base of every ht device in + * chain, assume every chain only have 4 ht device at most. + */ +unsigned hcdnx[] = { + 0x20202020, /* A8N-E has only one ht-chain */ }; + unsigned bus_type[256];
extern void get_sblk_pci1234(void); @@ -55,19 +66,18 @@
void get_bus_conf(void) { - unsigned apicid_base; - + unsigned apicid_base, sbdn; device_t dev; - unsigned sbdn; int i, j;
if (get_bus_conf_done == 1) - return; //do it only once + return; /* Do it only once. */
get_bus_conf_done = 1;
- sysconf.hc_possible_num = sizeof(pci1234x) / sizeof(pci1234x[0]); - sysconf.hc_possible_num = sizeof(pci1234x) / sizeof(pci1234x[0]); + /* FIXME: Is this really needed twice? */ + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); for (i = 0; i < sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; sysconf.hcdn[i] = hcdnx[i]; @@ -75,18 +85,15 @@
get_sblk_pci1234();
- sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain + sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain sbdn = sysconf.sbdn;
- for (i = 0; i < 6; i++) { + for (i = 0; i < 6; i++) bus_ck804[i] = 0; - } - - for (i = 0; i < 256; i++) { + for (i = 0; i < 256; i++) bus_type[i] = 0; - }
- bus_type[0] = 1; //pci + bus_type[0] = 1; /* PCI */
bus_ck804[0] = (sysconf.pci1234[0] >> 16) & 0xff;
@@ -107,9 +114,8 @@ }
for (i = 2; i < 6; i++) { - dev = - dev_find_slot(bus_ck804[0], - PCI_DEVFN(sbdn + 0x0b + i - 2, 0)); + dev = dev_find_slot(bus_ck804[0], + PCI_DEVFN(sbdn + 0x0b + i - 2, 0)); if (dev) { bus_ck804[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); @@ -117,14 +123,12 @@ for (j = bus_ck804[i]; j < bus_isa; j++) bus_type[j] = 1; } else { - printk_debug - ("ERROR - could not find PCI %02x:%02x.0, using defaults\n", + printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804[0], sbdn + 0x0b + i - 2); bus_isa = bus_ck804[i - 1] + 1; } }
-/*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS==1 apicid_base = get_apicid_base(3); #else
Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/irq_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8n_e/irq_tables.c 2008-09-30 06:13:54 UTC (rev 3621) +++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/irq_tables.c 2008-09-30 15:02:40 UTC (rev 3622) @@ -21,8 +21,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-/* Documentation at: http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM */ - #include <console/console.h> #include <device/pci.h> #include <string.h> @@ -63,18 +61,14 @@ */ unsigned long write_pirq_routing_table(unsigned long addr) { - struct irq_routing_table *pirq; struct irq_info *pirq_info; - unsigned slot_num; - uint8_t *v; - - uint8_t sum = 0; + unsigned slot_num, sbdn; + uint8_t *v, sum = 0; int i; - unsigned sbdn;
- /* get_bus_conf() will find out all bus num and apic that share with - * mptable.c and mptable.c + /* get_bus_conf() will find out all bus num and APIC that share with + * mptable.c and mptable.c. */ get_bus_conf(); sbdn = sysconf.sbdn; @@ -83,23 +77,19 @@ addr += 15; addr &= ~15;
- /* This table must be betweeen 0xf0000 & 0x100000 */ + /* This table must be betweeen 0xf0000 & 0x100000. */ printk_info("Writing IRQ routing tables to 0x%x...", addr);
pirq = (void *)(addr); - v = (uint8_t *) (addr); + v = (uint8_t *)(addr);
pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - pirq->rtr_bus = bus_ck804[0]; pirq->rtr_devfn = ((sbdn + 9) << 3) | 0; - pirq->exclusive_irqs = 0x828; - pirq->rtr_vendor = 0x10de; pirq->rtr_device = 0x005c; - pirq->miniport_data = 0;
memset(pirq->rfu, 0, sizeof(pirq->rfu)); @@ -107,32 +97,31 @@ pirq_info = (void *)(&pirq->checksum + 1); slot_num = 0;
-//Slot1 PCIE 16x + /* Slot1 PCIE 16x */ write_pirq_info(pirq_info, bus_ck804[1], (0 << 3) | 0, 0x3, 0xdeb8, 0x4, 0xdeb8, 0x1, 0xdeb8, 0x2, 0xdeb8, 4, 0); pirq_info++; slot_num++;
-//Slot2 PCIE 1x + /* Slot2 PCIE 1x */ write_pirq_info(pirq_info, bus_ck804[2], (0 << 3) | 0, 0x4, 0xdeb8, 0x1, 0xdeb8, 0x2, 0xdeb8, 0x3, 0xdeb8, 5, 0); pirq_info++; slot_num++;
-//Slot3 PCIE 1x + /* Slot3 PCIE 1x */ write_pirq_info(pirq_info, bus_ck804[3], (0 << 3) | 0, 0x1, 0xdeb8, 0x2, 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 6, 0); pirq_info++; slot_num++;
-//Slot4 PCIE 4x - write_pirq_info(pirq_info, bus_ck804[4], (0x4 << 3) | 0, - 0x2, 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 0x1, 0xdeb8, - 7, 0); + /* Slot4 PCIE 4x */ + write_pirq_info(pirq_info, bus_ck804[4], (0x4 << 3) | 0, 0x2, + 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 0x1, 0xdeb8, 7, 0); pirq_info++; slot_num++;
-//Slot5 - 7 PCI + /* Slot5 - Slot7 PCI */ for (i = 0; i < 3; i++) { write_pirq_info(pirq_info, bus_ck804[5], (0 << (6 + i)) | 0, ((i + 0) % 4) + 1, 0xdeb8, @@ -143,47 +132,50 @@ slot_num++; }
-//pci bridge + /* PCI bridge */ write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 9) << 3) | 0, 0x1, 0xdeb8, 0x2, 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 0, 0); pirq_info++; slot_num++;
-//smbus + /* SMBus */ write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 1) << 3) | 0, 0x2, 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0); pirq_info++; slot_num++;
-//usb + /* USB */ write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 2) << 3) | 0, 0x1, 0xdeb8, 0x2, 0xdeb8, 0, 0, 0, 0, 0, 0); pirq_info++; slot_num++;
-//audio + /* Audio */ write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 4) << 3) | 0, 0x1, 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0); pirq_info++; slot_num++; -//sata + + /* SATA */ write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 7) << 3) | 0, 0x1, 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0); pirq_info++; slot_num++; -//sata + + /* SATA */ write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 8) << 3) | 0, 0x1, 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0); pirq_info++; slot_num++; -//nic + + /* NIC */ write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 0xa) << 3) | 0, 0x1, 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0); pirq_info++; slot_num++;
#if 0 -//firewire ?? + /* Firewire? */ write_pirq_info(pirq_info, bus_ck804_1, (0x5 << 3) | 0, 0x3, 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0); pirq_info++; @@ -196,10 +188,8 @@ sum += v[i];
sum = pirq->checksum - sum; - - if (sum != pirq->checksum) { + if (sum != pirq->checksum) pirq->checksum = sum; - }
printk_info("done.\n");
Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/mptable.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8n_e/mptable.c 2008-09-30 06:13:54 UTC (rev 3621) +++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/mptable.c 2008-09-30 15:02:40 UTC (rev 3622) @@ -26,28 +26,23 @@ #include <device/pci.h> #include <string.h> #include <stdint.h> - #include <cpu/amd/amdk8_sysconf.h>
extern unsigned char bus_isa; extern unsigned char bus_ck804[6]; extern unsigned apicid_ck804; - extern unsigned bus_type[256]; - extern void get_bus_conf(void);
void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; static const char oem[8] = "ASUS "; - static const char productid[12] = "A8NE "; + static const char productid[12] = "A8N-E "; struct mp_config_table *mc; unsigned sbdn; + int i, bus_num;
- int bus_num; - int i; - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc));
@@ -70,15 +65,15 @@ get_bus_conf(); sbdn = sysconf.sbdn;
-/* Bus: Bus ID Type*/ - /* define numbers for pci and isa bus */ + /* Bus: Bus ID Type */ + /* Define numbers for PCI and ISA bus. */ for (bus_num = 0; bus_num < 256; bus_num++) { if (bus_type[bus_num]) smp_write_bus(mc, bus_num, "PCI "); - } + } smp_write_bus(mc, bus_isa, "ISA ");
-/* I/O APICs: APIC ID Version State Address*/ + /* I/O APICs: APIC ID Version State Address */ { device_t dev; struct resource *res; @@ -92,7 +87,7 @@ res->base); }
- /* Initialize interrupt mapping */ + /* Initialize interrupt mapping. */ dword = 0x01200000; pci_write_config32(dev, 0x7c, dword);
@@ -105,7 +100,7 @@ } }
-/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x0, apicid_ck804, 0x0); @@ -151,21 +146,31 @@ 0xa);
// Onboard ck804 USB 1.1 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_ck804[0], ((sbdn + 2) << 2) | 0, apicid_ck804, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + bus_ck804[0], ((sbdn + 2) << 2) | 0, apicid_ck804, + 0x15);
// Onboard ck804 USB 2 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_ck804[0], ((sbdn + 2) << 2) | 1, apicid_ck804, 0x14); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + bus_ck804[0], ((sbdn + 2) << 2) | 1, apicid_ck804, + 0x14);
// Onboard ck804 SATA 0 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_ck804[0], ((sbdn + 7) << 2) | 0, apicid_ck804, 0x17); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + bus_ck804[0], ((sbdn + 7) << 2) | 0, apicid_ck804, + 0x17);
// Onboard ck804 SATA 1 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_ck804[0], ((sbdn + 8) << 2) | 0, apicid_ck804, 0x16); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + bus_ck804[0], ((sbdn + 8) << 2) | 0, apicid_ck804, + 0x16);
// Onboard ck804 NIC - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_ck804[0], ((sbdn + 10) << 2) | 0, apicid_ck804, 0x17); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, + bus_ck804[0], ((sbdn + 10) << 2) | 0, apicid_ck804, + 0x17);
-/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ + /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT, bus_ck804[0], 0x0, MP_APIC_ALL, 0x0); @@ -175,7 +180,7 @@
/* There is no extension information... */
- /* Compute the checksums */ + /* Compute the checksums. */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); @@ -186,7 +191,6 @@
unsigned long write_smp_table(unsigned long addr) { - void *v; - v = smp_write_floating_table(addr); + void *v = smp_write_floating_table(addr); return (unsigned long)smp_write_config_table(v); }
Modified: trunk/coreboot-v2/targets/asus/a8n_e/Config.lb =================================================================== --- trunk/coreboot-v2/targets/asus/a8n_e/Config.lb 2008-09-30 06:13:54 UTC (rev 3621) +++ trunk/coreboot-v2/targets/asus/a8n_e/Config.lb 2008-09-30 15:02:40 UTC (rev 3622) @@ -23,30 +23,30 @@ mainboard asus/a8n_e
romimage "normal" - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x20000 - option XIP_ROM_SIZE=0x20000 - option COREBOOT_EXTRA_VERSION="_Normal" + option USE_FAILOVER_IMAGE = 0 + option USE_FALLBACK_IMAGE = 0 + option ROM_IMAGE_SIZE = 128 * 1024 + option XIP_ROM_SIZE = 128 * 1024 + option COREBOOT_EXTRA_VERSION = "_Normal" payload ../payload.elf end
romimage "fallback" - option USE_FAILOVER_IMAGE=0 - option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x20000 - option XIP_ROM_SIZE=0x20000 - option COREBOOT_EXTRA_VERSION="_Fallback" + option USE_FAILOVER_IMAGE = 0 + option USE_FALLBACK_IMAGE = 1 + option ROM_IMAGE_SIZE = 128 * 1024 + option XIP_ROM_SIZE = 128 * 1024 + option COREBOOT_EXTRA_VERSION = "_Fallback" payload ../payload.elf end
romimage "failover" - option USE_FAILOVER_IMAGE=1 - option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=FAILOVER_SIZE - option XIP_ROM_SIZE=FAILOVER_SIZE - option COREBOOT_EXTRA_VERSION="_Failover" + option USE_FAILOVER_IMAGE = 1 + option USE_FALLBACK_IMAGE = 0 + option ROM_IMAGE_SIZE = FAILOVER_SIZE + option XIP_ROM_SIZE = FAILOVER_SIZE + option COREBOOT_EXTRA_VERSION = "_Failover" end
buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover" -#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" +# buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
-
svn＠coreboot.org