coreboot July 2008

coreboot@coreboot.org

58 participants
214 discussions

Phoenix reassembly
by Myles Watson 27 Jul '08

27 Jul '08

In the s2891 tutorial it shows phnxdeco producing a rom.scr file, which the readme says will reassemble the BIOS. The version I downloaded doesn't seem to produce this file with the -xs or -x options. What's the preferred way to get the BIOS out of the .wph file so that flashrom can use it? Thanks, Myles

3 4

Pentium MMX L1 cache enable problems
by Urja Rannikko 27 Jul '08

27 Jul '08

Hi list, So, i'm having problems with enabling L1 cache on this Pentium MMX 233. The current code (called after raminit still in non-RAM part) goes here: static void m1531_enable_l1(const struct mem_controller *ctrl) { uint8_t reg; asm volatile( "invd" "\n\t" :: ); reg = pci_read_config8(ctrl->d0, L1CDBC); reg |= 1; pci_write_config8(ctrl->d0,L1CDBC,reg); asm volatile( "movl %%cr0, %%eax" "\n\t" "andl $0x9FFFFFFF, %%eax" "\n\t" "movl %%eax, %%cr0" "\n\t" ::: "eax" ); } And yes, i know that that code isn't exactly to the guidelines, but after i get it to work i can work on that. Including this code causes the board to immediately reset/reboot upon trying to jump to coreboot. The only clue/idea i've got is that maybe it needs some MSR stuff to work, but i really don't know. Any ideas, comments, etc welcomed. -- urjaman

1 0

Coreboot for MSI K8M NEO-V MoBo
by Kunal Ghosh 26 Jul '08

26 Jul '08

Hi all, Just joined this group. I have a MSI K8M NEO-V Motherboard, details at - http://www1.dealtime.com/xPF-MSI-K8M-NEO-V-skt-754-800FSB-K8M800-5-1-ch-aud… Could someone please tell me if I can use Coreboot on this MOBO ? If yes, which version and where do I find the howto. Many thanks. --K.Ghosh ------------------------------- Tel: +91 93 910 58 749 SIP: 1-747-025-2812 Mail: kghosh22(a)gmail.com Debian GNU/Linux user No.301508

1 0

Re: [coreboot] r698 - coreboot-v3/include/arch/x86
by Carl-Daniel Hailfinger 25 Jul '08

25 Jul '08

Hi, r698 left me with the desire to put these new #defines to good use. On 25.07.2008 21:44, svn(a)coreboot.org wrote: > Author: rminnich > New Revision: 698 > > Add names for control bits. > Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> > Acked-by: Marc Jones <marc.jones(a)amd.com> > > > Modified: coreboot-v3/include/arch/x86/amd_geodelx.h > =================================================================== > --- coreboot-v3/include/arch/x86/amd_geodelx.h 2008-07-20 21:05:25 UTC (rev 697) > +++ coreboot-v3/include/arch/x86/amd_geodelx.h 2008-07-25 19:44:08 UTC (rev 698) > @@ -230,6 +230,21 @@ > #define DM_CONFIG0_LOWER_DCDIS_SET (1 << 8) > #define DM_CONFIG0_LOWER_MISSER_SET (1<<1) > > +/* Region CONFiguration registers (RCONF) */ > +/* There are control bits for memory configuration. They are at different > + * offsets depending on the MSR. We define them here with values > + * independent of their position in a 64-bit MSR, with a "shift" value > + * to get them into the right place. To use them for, e.g., the > + * CPU_RCONF_DEFAULT register, you would use > + * RCONF_WT(RCONF_DEFAULT_LOWER_SYSRC_SHIFT) > + */ > +#define RCONF_WS(x) (1<<(5+x)) /* Write-serialize */ > +#define RCONF_WC(x) (1<<(4+x)) /* Write-combine */ > +#define RCONF_WT(x) (1<<(3+x)) /* Write-through */ > +#define RCONF_WP(x) (1<<(2+x)) /* Write-protect */ > +#define RCONF_WA(x) (1<<(1+x)) /* Write-allocate */ > +#define RCONF_CD(x) (1<<(0+x)) /* Cache Disable */ > + > #define CPU_RCONF_DEFAULT 0x1808 > #define RCONF_DEFAULT_UPPER_ROMRC_SHIFT 24 > #define RCONF_DEFAULT_UPPER_ROMBASE_SHIFT 4 > Hmm... that would mean we can change the GeodeLX CAR code a bit. RFC for a patch follows. I have no idea whether this is completely correct. Index: arch/x86/geodelx/stage0.S =================================================================== --- arch/x86/geodelx/stage0.S (Revision 698) +++ arch/x86/geodelx/stage0.S (Arbeitskopie) @@ -180,8 +180,10 @@ movl $CPU_RCONF_DEFAULT, %ecx rdmsr - /* 1MB system memory in write back 1|00100|00. */ - movl $0x010010000, %eax + /* 1 MB system memory (256 blocks of 4kB), + * disable cache between SYSTOP and ROMBASE. + */ + movl $(RCONF_CD(RCONF_DEFAULT_LOWER_DEVRC_LOW_SHIFT)|(256<<RCONF_DEFAULT_LOWER_SYSTOP_SHIFT)), %eax wrmsr /* In LX DCDIS is set after POR which disables the cache..., clear Index: arch/x86/geodelx/stage1.c =================================================================== --- arch/x86/geodelx/stage1.c (Revision 698) +++ arch/x86/geodelx/stage1.c (Arbeitskopie) @@ -26,7 +26,12 @@ static const struct msrinit msr_table[] = { /* Setup access to cache under 1MB. */ - {CPU_RCONF_DEFAULT, {.hi = 0x24fffc02,.lo = 0x1000A000}}, // 0x00000-0xA0000 + {CPU_RCONF_DEFAULT, {.hi = (RCONF_WS(RCONF_DEFAULT_UPPER_ROMRC_SHIFT)| + RCONF_WP(RCONF_DEFAULT_UPPER_ROMRC_SHIFT)| + (0xfffc<<RCONF_DEFAULT_UPPER_ROMBASE_SHIFT)| + RCONF_CD((RCONF_DEFAULT_LOWER_DEVRC_LOW_SHIFT-32))), + .lo = RCONF_CD(RCONF_DEFAULT_LOWER_DEVRC_LOW_SHIFT)| + (0x00A0<<RCONF_DEFAULT_LOWER_SYSTOP_SHIFT)}}, // 0x00000-0xA0000 {CPU_RCONF_A0_BF, {.hi = 0x00000000,.lo = 0x00000000}}, // 0xA0000-0xBFFFF {CPU_RCONF_C0_DF, {.hi = 0x00000000,.lo = 0x00000000}}, // 0xC0000-0xDFFFF {CPU_RCONF_E0_FF, {.hi = 0x00000000,.lo = 0x00000000}}, // 0xE0000-0xFFFFF Regards, Carl-Daniel -- http://www.hailfinger.org/

1 0

r698 - coreboot-v3/include/arch/x86
by svn＠coreboot.org 25 Jul '08

25 Jul '08

Author: rminnich Date: 2008-07-25 21:44:08 +0200 (Fri, 25 Jul 2008) New Revision: 698 Modified: coreboot-v3/include/arch/x86/amd_geodelx.h Log: Add names for control bits. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Marc Jones <marc.jones(a)amd.com> Modified: coreboot-v3/include/arch/x86/amd_geodelx.h =================================================================== --- coreboot-v3/include/arch/x86/amd_geodelx.h 2008-07-20 21:05:25 UTC (rev 697) +++ coreboot-v3/include/arch/x86/amd_geodelx.h 2008-07-25 19:44:08 UTC (rev 698) @@ -230,6 +230,21 @@ #define DM_CONFIG0_LOWER_DCDIS_SET (1 << 8) #define DM_CONFIG0_LOWER_MISSER_SET (1<<1) +/* Region CONFiguration registers (RCONF) */ +/* There are control bits for memory configuration. They are at different + * offsets depending on the MSR. We define them here with values + * independent of their position in a 64-bit MSR, with a "shift" value + * to get them into the right place. To use them for, e.g., the + * CPU_RCONF_DEFAULT register, you would use + * RCONF_WT(RCONF_DEFAULT_LOWER_SYSRC_SHIFT) + */ +#define RCONF_WS(x) (1<<(5+x)) /* Write-serialize */ +#define RCONF_WC(x) (1<<(4+x)) /* Write-combine */ +#define RCONF_WT(x) (1<<(3+x)) /* Write-through */ +#define RCONF_WP(x) (1<<(2+x)) /* Write-protect */ +#define RCONF_WA(x) (1<<(1+x)) /* Write-allocate */ +#define RCONF_CD(x) (1<<(0+x)) /* Cache Disable */ + #define CPU_RCONF_DEFAULT 0x1808 #define RCONF_DEFAULT_UPPER_ROMRC_SHIFT 24 #define RCONF_DEFAULT_UPPER_ROMBASE_SHIFT 4

1 0

add bit field names on geode north
by ron minnich 25 Jul '08

25 Jul '08

attached. ron

2 1

patch: lxirq understander
by ron minnich 24 Jul '08

24 Jul '08

Can I get feedback on this one? It's the lx irq understander. I'd like to get this in so others can give it a try. I want to finish this as I need to write an LX NB understander, in an attempt to do a first-principals pass at 'what the hell is wrong with the dbe62'. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> ron

5 9

kernel panics reserving EBDA pages
by Roman Kononov 23 Jul '08

23 Jul '08

Hello, I have this chain: coreboot v2 -> etherboot as the payload -> x86_64 kernel 2.6.25.6. The kernel panics in arch/x86/e820_64.c, reserve_early() with the message: Overlapping early reservations f0-100ef EBDA to 0-fff BIOS data page reserve_early(start,end) is called from arch/x86/head64.c, reserve_ebda() with start=0xf0 and end=0x100f0. The address and size of EBDA is gotten this way: #define EBDA_ADDR_POINTER 0x40E ebda_addr = *(unsigned short *)__va(EBDA_ADDR_POINTER); ebda_addr <<= 4; ebda_size = *(unsigned short *)__va(ebda_addr); After the above sequence ebda_addr=0xf0 and ebda_size=0x2049 KiB; This all happened in a very well working system after I added the second dual-core Opteron. Without the second CPU, ebda_addr=0x12010 and ebda_size=0, which combination passes reserve_early() without overlapping. The resulting reservations are: early res: 0 [0-fff] BIOS data page early res: 1 [6000-7fff] SMP_TRAMPOLINE early res: 2 [200000-75b503] TEXT DATA BSS early res: 3 [800000-9bd8dd] RAMDISK early res: 4 [12010-1300f] EBDA early res: 5 [8000-cfff] PGTABLE How come? What is responsible to clear the memory at 0x40e? What is EBDA and what needs it? Thanks, Roman Kononov

3 6

Re: [coreboot] r3434 - in trunk/coreboot-v2/src: config cpu/amd/model_10xxx mainboard/amd/serengeti_cheetah_fam10
by Carl-Daniel Hailfinger 23 Jul '08

23 Jul '08

On 23.07.2008 23:11, svn(a)coreboot.org wrote: > Author: mjones > Date: 2008-07-23 23:11:20 +0200 (Wed, 23 Jul 2008) > New Revision: 3434 > > Log: > Update to the latest AMD Fam10 microcode patches. > Add platform option for patch file name. > > Signed-off-by: Marc Jones <marc.jones(a)amd.com> > Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> > > > > Modified: trunk/coreboot-v2/src/config/Options.lb > =================================================================== > --- trunk/coreboot-v2/src/config/Options.lb 2008-07-23 21:04:03 UTC (rev 3433) > +++ trunk/coreboot-v2/src/config/Options.lb 2008-07-23 21:11:20 UTC (rev 3434) > @@ -1061,6 +1061,12 @@ > comment "use AMD MCT to init RAM instead of native code" > end > > +define AMD_UCODE_PATCH_FILE > + default none > + export used > + format "\"%s\"" > + comment "name of the micorcode patch file" > Sorry, I missed the "micorcode" typo above in the review. Could you fix it up? Feel free to reuse my Ack for that. > + > define CONFIG_VIDEO_MB > default none > export used > Regards, Carl-Daniel

1 0

r3436 build service
by coreboot information 23 Jul '08

23 Jul '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "mjones" checked in revision 3436 to the coreboot source repository and caused the following changes: Change Log: Fix r3434 check-in. Added missing end to Options.lb. Not entirely sure how it went missing.... Signed-off-by: Marc Jones <marc.jones(a)amd.com> Acked-by: Marc Jones <marc.jones(a)amd.com> Build Log: Configuration of a-trend:atc-6220 has been fixed Configuration of a-trend:atc-6240 has been fixed Configuration of abit:be6-ii_v2_0 has been fixed Configuration of advantech:pcm-5820 has been fixed Configuration of agami:aruma has been fixed Configuration of amd:db800 has been fixed Configuration of amd:norwich has been fixed Configuration of amd:rumba has been fixed Configuration of amd:serengeti_cheetah has been fixed Configuration of amd:serengeti_cheetah_fam10 has been fixed Configuration of arima:hdama has been fixed Configuration of artecgroup:dbe61 has been fixed Configuration of asi:mb_5blmp has been fixed Configuration of asus:a8n_e has been fixed Configuration of asus:a8v-e_se has been fixed Configuration of asus:mew-am has been fixed Configuration of asus:mew-vm has been fixed Configuration of asus:p2b has been fixed Configuration of asus:p2b-f has been fixed Configuration of asus:p3b-f has been fixed Configuration of axus:tc320 has been fixed Configuration of azza:pt-6ibd has been fixed Configuration of bcom:winnet100 has been fixed Configuration of biostar:m6tba has been fixed Configuration of broadcom:blast has been fixed Configuration of compaq:deskpro_en_sff_p600 has been fixed Configuration of dell:s1850 has been fixed Configuration of digitallogic:adl855pc has been fixed Configuration of digitallogic:msm586seg has been fixed Configuration of digitallogic:msm800sev has been fixed Configuration of eaglelion:5bcm has been fixed Configuration of embeddedplanet:ep405pc has been fixed Configuration of emulation:qemu-x86 has been fixed Configuration of gigabyte:ga-6bxc has been fixed Configuration of gigabyte:ga_2761gxdk has been fixed Configuration of gigabyte:m57sli has been fixed Configuration of ibm:e325 has been fixed Configuration of ibm:e326 has been fixed Configuration of iei:juki-511p has been fixed Configuration of iei:nova4899r has been fixed Configuration of iei:pcisa-lx-800-r10 has been fixed Configuration of intel:jarrell has been fixed Configuration of intel:mtarvon has been fixed Configuration of intel:xe7501devkit has been fixed Configuration of iwill:dk8_htx has been fixed Configuration of iwill:dk8s2 has been fixed Configuration of iwill:dk8x has been fixed Configuration of lippert:frontrunner has been fixed Configuration of motorola:sandpointx3_altimus_mpc7410 has been fixed Configuration of msi:ms6119 has been fixed Configuration of msi:ms6178 has been fixed Configuration of msi:ms7135 has been fixed Configuration of msi:ms7260 has been fixed Configuration of msi:ms9185 has been fixed Configuration of msi:ms9282 has been fixed Configuration of newisys:khepri has been fixed Configuration of nvidia:l1_2pvv has been fixed Configuration of olpc:btest has been fixed Configuration of olpc:rev_a has been fixed Configuration of pcengines:alix1c has been fixed Configuration of rca:rm4100 has been fixed Configuration of sunw:ultra40 has been fixed Configuration of supermicro:h8dmr has been fixed Configuration of supermicro:x6dai_g has been fixed Configuration of supermicro:x6dhe_g has been fixed Configuration of supermicro:x6dhe_g2 has been fixed Configuration of supermicro:x6dhr_ig has been fixed Configuration of supermicro:x6dhr_ig2 has been fixed Configuration of technologic:ts5300 has been fixed Configuration of televideo:tc7020 has been fixed Configuration of thomson:ip1000 has been fixed Configuration of totalimpact:briq has been fixed Configuration of tyan:s1846 has been fixed Configuration of tyan:s2735 has been fixed Configuration of tyan:s2850 has been fixed Configuration of tyan:s2875 has been fixed Configuration of tyan:s2880 has been fixed Configuration of tyan:s2881 has been fixed Configuration of tyan:s2882 has been fixed Configuration of tyan:s2885 has been fixed Configuration of tyan:s2891 has been fixed Configuration of tyan:s2892 has been fixed Configuration of tyan:s2895 has been fixed Configuration of tyan:s2912 has been fixed Configuration of tyan:s4880 has been fixed Configuration of tyan:s4882 has been fixed Configuration of via:epia has been fixed Configuration of via:epia-cn has been fixed Configuration of via:epia-m has been fixed If something broke during this checkin please be a pain in mjones's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

← Newer
1
2
3
4
5
6
7
8
9
...
22
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot July 2008