coreboot July 2008

coreboot@coreboot.org

58 participants
214 discussions

section .id cant be allocated in segment 1 - error
by Amrish Purohit 01 Aug '08

01 Aug '08

hi all i am implementing coreboot in qemu with linux kernel as a payload. but when i compile coreboot it shows above subject error. i have changed the ROM_SIZE option to 2048x1024 and my linux.elf size is 440785 bytes. so what may be wrong. regds amrish purohit

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Hackontest: Last chance for free travel/accommodation/food
by Carl-Daniel Hailfinger 31 Jul '08

31 Jul '08

Hi! Coreboot has entered Hackontest a few weeks ago and we're doing reasonably well, but YOUR help is needed NOW. We have ~48 hours left until the hackontest finalists are chosen. What's Hackontest? It's a 24 hour coding sprint located in Zürich/Switzerland during OpenExpo (September 24/25) organized by the Swiss Open Systems User Group and sponsored by Google. http://hackontest.org/index.php?action=Root-projectDetail%2836%29 We need one or two additional people who agree to implement or work/hack on any the following features for 24 hours: - Bring up the K8 (Athlon64) in coreboot v3 - Create flashrom support for the EeePc - Easy web interface to create coreboot ROMs - Offer a compat EFI plugin - Add support for AMD Phenom processors - Offer a compat BIOS plugin - Add AMD 690 chipset series support to coreboot - Add AMD 700 chipset series support to coreboot Only one feature will be selected by the review comittee, so please add your name to all of those you think you could work on. Adding your name is a simple as logging in and clicking on "Agree to implement" for each feature. Benefits for you (if coreboot is chosen and you're part of the team): - Google pays for your travel to Zürich/Switzerland including accommodation and meals from September 23 - 26, 2008 up to USD 1000 each person. - The participating team may win cash prizes of USD 1000, 2500 and 5000. - You get to code for 24 hours non-stop in a famous etoy.TANK http://www.etoy.com/projects/etoy-tanks/ - Travel to Switzerland. - Free all you can eat pizza/caffeine during the coding marathon. Please also vote for all coreboot features. It really helps. http://hackontest.org/index.php?action=Root-projectDetail%2836%29 Benefits for the project: - Media coverage. Lots of it. - Money. Can help cover the costs of another coreboot symposium. - More developers. Visibility will help us a lot. - One more feature is getting done. Regards, Carl-Daniel

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8mm tapes from coreboot meeting in denver
by ron minnich 31 Jul '08

31 Jul '08

I need help getting these 8mm tapes on to the web site. Anyone in the CA area who can give me a hand? I am in livermore ca. ron

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How to switch the coreboot-v2 from the ROMCC mode to CAR/gcc mode?
by JasonZhao＠viatech.com.cn 31 Jul '08

31 Jul '08

Hi all, I think alI need to do is to edit one of the config.lb, and adapt the cache_as_ram..inc. Is that right? But which config.lb and what need to be changed in it? (My CAR code now can work under EFI, but I want to migrate it into coreboot) I didn't found the information I need on the www.coreboot.org/document and this maillist. So any comment are welcome, I am a newbie.

2 1

some interesting quotes
by ron minnich 31 Jul '08

31 Jul '08

you may or may not have seen them http://eecue.com/log_archive/eecue-log-724-Black_Hat_2007___Day_2___John_He… "There are many ways to get code into the EFI environment. An attacker can modify the bootlader directly, modify bootloader varibles in NVRAM, modify and reflash firmware or exploit an implementation flaw in the driver. Once the attacher is in, they can shim a boot service, modify an ACPI table like in the tradition BIOS attack, load an SMM driver, or hook interrup handlers. Modifying the boot loader is actually quite simple in Mac OSX as the bootloader binary is located in user disk space: /System/Library/CoreSerbvice.boot.efi. This isn't very stealthy as you are modifying a file on disk which could easily be detected by verifying checksums with an application like tripwire." now we've been trying to get this message across for eitght years now and it's good to see people are independently figuring it out. Here's another part: "The bottom line is that with the added functionality, EFI offers an attacker many more options than BIOS for exploitation. The EFI specification is not very clear with regards to security which will result in various vendors implementing insecure versions of EFI. In the future look out for nasty rootkits based on EFI." thanks ron

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SeaBIOS debug output
by Myles Watson 31 Jul '08

31 Jul '08

Kevin, When I increase the debug level in SeaBIOS, I see the enter handle_10 messages in hardware, but not in qemu. Do you see that as well? Thanks, Myles

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Device number to use with testbios & lspci output difference between Commercial BIOS and coreboot
by Ken.Fuchs＠bench.com 31 Jul '08

31 Jul '08

I have a PCI video card in an nVidia CRB system that I'm trying to init via testbios (user mode VGA option ROM init). I need to determine which device number (-d argument) I should use with testbios, so I did a lspci under coreboot, but the video card doesn't seem to show up. When I switch back to the Commercial BIOS, the video card is clearly identified as: 01:06.0 VGA compatible controller: Tseng Labs Inc ET6000 (rev 30) lspci output for both LinuxBIOS and Phoenix BIOS appears after my sig. The testbios command line I'm using is: ./testbios -s 65536 --abseg /dev/mem ./vgabios1.bin What should the -d argument for testbios be? It is confusing that LinuxBIOS (coreboot) and Phoenix BIOS are using different PCI bus numbers. I always assumed that didn't matter, but now I'm not so positive. Does it really matter? Sincerely, Ken Fuchs ------ LinuxBIOS (coreboot): [root@localhost ~]# lspci lspci 00:18.0 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration 00:18.1 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map 00:18.2 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller 00:18.3 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control 00:19.0 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration 00:19.1 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map 00:19.2 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller 00:19.3 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control 01:00.0 Memory controller: nVidia Corporation CK804 Memory Controller (rev a3) 01:01.0 ISA bridge: nVidia Corporation: Unknown device 0051 (rev a3) 01:01.2 Memory controller: nVidia Corporation: Unknown device 005f (rev a3) 01:02.0 USB Controller: nVidia Corporation CK804 USB Controller (rev a2) 01:02.1 USB Controller: nVidia Corporation CK804 USB Controller (rev a3) 01:06.0 IDE interface: nVidia Corporation CK804 IDE (rev a2) 01:07.0 IDE interface: nVidia Corporation CK804 Serial ATA Controller (rev a3) 01:08.0 IDE interface: nVidia Corporation CK804 Serial ATA Controller (rev a3) 01:0b.0 PCI bridge: nVidia Corporation CK804 PCIE Bridge (rev a3) 01:0c.0 PCI bridge: nVidia Corporation CK804 PCIE Bridge (rev a3) 01:0d.0 PCI bridge: nVidia Corporation CK804 PCIE Bridge (rev a3) 01:0e.0 PCI bridge: nVidia Corporation CK804 PCIE Bridge (rev a3) 02:00.0 Memory controller: nVidia Corporation CK804 Memory Controller (rev a3) 02:01.0 Memory controller: nVidia Corporation CK804 Memory Controller (rev a3) 02:01.1 SMBus: nVidia Corporation CK804 SMBus (rev a2) 02:01.2 Memory controller: nVidia Corporation: Unknown device 005f (rev a3) 02:07.0 IDE interface: nVidia Corporation CK804 Serial ATA Controller (rev a3) 02:08.0 IDE interface: nVidia Corporation CK804 Serial ATA Controller (rev a3) 02:0a.0 Ethernet controller: nVidia Corporation CK804 Ethernet Controller (rev a3) 02:0b.0 PCI bridge: nVidia Corporation CK804 PCIE Bridge (rev a3) 02:0c.0 PCI bridge: nVidia Corporation CK804 PCIE Bridge (rev a3) 02:0d.0 PCI bridge: nVidia Corporation CK804 PCIE Bridge (rev a3) 02:0e.0 PCI bridge: nVidia Corporation CK804 PCIE Bridge (rev a3) [root@localhost ~]# ------ Phoenix Technologies BIOS: [root@localhost ~]# lspci lspci 00:00.0 Memory controller: nVidia Corporation CK804 Memory Controller (rev a3) 00:01.0 ISA bridge: nVidia Corporation: Unknown device 0051 (rev a3) 00:01.1 SMBus: nVidia Corporation CK804 SMBus (rev a2) 00:02.0 USB Controller: nVidia Corporation CK804 USB Controller (rev a2) 00:02.1 USB Controller: nVidia Corporation CK804 USB Controller (rev a3) 00:04.0 Multimedia audio controller: nVidia Corporation CK804 AC'97 Audio Controller (rev a2) 00:06.0 IDE interface: nVidia Corporation CK804 IDE (rev a2) 00:07.0 IDE interface: nVidia Corporation CK804 Serial ATA Controller (rev a3) 00:08.0 IDE interface: nVidia Corporation CK804 Serial ATA Controller (rev a3) 00:09.0 PCI bridge: nVidia Corporation CK804 PCI Bridge (rev a2) 00:0a.0 Bridge: nVidia Corporation CK804 Ethernet Controller (rev a3) 00:0d.0 PCI bridge: nVidia Corporation CK804 PCIE Bridge (rev a3) 00:0e.0 PCI bridge: nVidia Corporation CK804 PCIE Bridge (rev a3) 00:18.0 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration 00:18.1 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map 00:18.2 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller 00:18.3 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control 00:19.0 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration 00:19.1 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map 00:19.2 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller 00:19.3 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control 01:06.0 VGA compatible controller: Tseng Labs Inc ET6000 (rev 30) 80:00.0 Memory controller: nVidia Corporation CK804 Memory Controller (rev a3) 80:01.0 Memory controller: nVidia Corporation CK804 Memory Controller (rev a3) 80:07.0 IDE interface: nVidia Corporation CK804 Serial ATA Controller (rev a3) 80:08.0 IDE interface: nVidia Corporation CK804 Serial ATA Controller (rev a3) 80:0a.0 Bridge: nVidia Corporation CK804 Ethernet Controller (rev a3) 80:0c.0 PCI bridge: nVidia Corporation CK804 PCIE Bridge (rev a3) 80:0d.0 PCI bridge: nVidia Corporation CK804 PCIE Bridge (rev a3) 80:0e.0 PCI bridge: nVidia Corporation CK804 PCIE Bridge (rev a3) [root@localhost ~]#

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[PATCH] [v3] Let the user chose a toolchain explicitly
by Philip Schulz 30 Jul '08

30 Jul '08

Hi, I don't know if this is the right way, but here's a diff to xcompile that lets the user pick a toolchain by setting the $CROSS environment variable. Yes, the idea is shamelessly stolen from SLOF ;-) I found this usefuly as the host compiler on my system won't produce a working binary whereas GCC 4.3.1 and binutils 2.18 compiled from the GNU tarballs work. Regards, Philip --- Make xcompile less smart and allow user to pick a toolchain by setting $CROSS Signed-off-by: Philip Schulz <philip.s.schulz(a)googlemail.com> diff -r 9bfb3ac80f66 util/xcompile/xcompile --- a/util/xcompile/xcompile Tue Jul 29 20:42:48 2008 +0200 +++ b/util/xcompile/xcompile Wed Jul 30 21:32:26 2008 +0200 @@ -53,54 +53,69 @@ exit 1 } -case "$ARCH" in -"x86_64") - echo "CC_x86 := gcc -m32" - CC="gcc -m32" +if [ -n "${CROSS:+1}" ] ; then + # If $CROSS is set, assume the user knows what he/she is doing - searchgnu ar >/dev/null && echo "AR_x86 := $(searchgnu ar)" - searchgnu as >/dev/null && echo "AS_x86 := $(searchgnu as) --32" - searchgnu ld >/dev/null && echo "LD_x86 := $(searchgnu ld) -b elf32-i386 -melf_i386" - searchgnu nm >/dev/null && echo "NM_x86 := $(searchgnu nm)" - searchgnu objcopy >/dev/null && echo "OBJCOPY_x86 := $(searchgnu objcopy)" - ;; -"x86") - if [ "$OS" != "Darwin" ]; then - echo "CC_x86 := gcc" - CC="gcc" + CC="${CROSS}gcc" + echo "CC_${ARCH} := ${CROSS}gcc" + echo "AR_${ARCH} := ${CROSS}ar" + echo "AS_${ARCH} := ${CROSS}as" + echo "LD_${ARCH} := ${CROSS}ld" + echo "NM_${ARCH} := ${CROSS}nm" + echo "OBJCOPY_${ARCH} := ${CROSS}objcopy" +else + # $CROSS is not set, so try to be smart and figure out the right + # settings automatically + + case "$ARCH" in + "x86_64") + echo "CC_x86 := gcc -m32" + CC="gcc -m32" searchgnu ar >/dev/null && echo "AR_x86 := $(searchgnu ar)" - searchgnu as >/dev/null && echo "AS_x86 := $(searchgnu as)" - searchgnu ld >/dev/null && echo "LD_x86 := $(searchgnu ld)" + searchgnu as >/dev/null && echo "AS_x86 := $(searchgnu as) --32" + searchgnu ld >/dev/null && echo "LD_x86 := $(searchgnu ld) -b elf32-i386 -melf_i386" searchgnu nm >/dev/null && echo "NM_x86 := $(searchgnu nm)" searchgnu objcopy >/dev/null && echo "OBJCOPY_x86 := $(searchgnu objcopy)" - else - CC=`find /opt/local/bin/ -name "i386-elf-gcc-*"` - if [ "$CC" == "" ]; then - echo "ERROR: Please install i386-elf-gcc from MacPorts" >&2 - exit 1 + ;; + "x86") + if [ "$OS" != "Darwin" ]; then + echo "CC_x86 := gcc" + CC="gcc" + + searchgnu ar >/dev/null && echo "AR_x86 := $(searchgnu ar)" + searchgnu as >/dev/null && echo "AS_x86 := $(searchgnu as)" + searchgnu ld >/dev/null && echo "LD_x86 := $(searchgnu ld)" + searchgnu nm >/dev/null && echo "NM_x86 := $(searchgnu nm)" + searchgnu objcopy >/dev/null && echo "OBJCOPY_x86 := $(searchgnu objcopy)" + else + CC=`find /opt/local/bin/ -name "i386-elf-gcc-*"` + if [ "$CC" == "" ]; then + echo "ERROR: Please install i386-elf-gcc from MacPorts" >&2 + exit 1 + fi + echo "CC_x86 := $CC" + echo "AR_x86 := i386-elf-ar" + echo "AS_x86 := i386-elf-as --divide" + echo "LD_x86 := i386-elf-ld" + echo "NM_x86 := i386-elf-nm" + echo "OBJCOPY_x86 := i386-elf-objcopy" + echo "INTLCFLAGS := -I/opt/local/include" + echo "INTLLIBS := -L/opt/local/lib -lintl" fi - echo "CC_x86 := $CC" - echo "AR_x86 := i386-elf-ar" - echo "AS_x86 := i386-elf-as --divide" - echo "LD_x86 := i386-elf-ld" - echo "NM_x86 := i386-elf-nm" - echo "OBJCOPY_x86 := i386-elf-objcopy" - echo "INTLCFLAGS := -I/opt/local/include" - echo "INTLLIBS := -L/opt/local/lib -lintl" - fi - ;; -*) - # FIXME: This should be detected. - CC="i386-linux-gcc" - echo "CC_x86 := i386-linux-gcc" - echo "AR_x86 := i386-linux-ar" - echo "AS_x86 := i386-linux-as" - echo "LD_x86 := i386-linux-ld" - echo "NM_x86 := i386-linux-nm" - echo "OBJCOPY_x86 := i386-linux-objcopy" - ;; -esac + ;; + *) + # FIXME: This should be detected. + CC="i386-linux-gcc" + echo "CC_x86 := i386-linux-gcc" + echo "AR_x86 := i386-linux-ar" + echo "AS_x86 := i386-linux-as" + echo "LD_x86 := i386-linux-ld" + echo "NM_x86 := i386-linux-nm" + echo "OBJCOPY_x86 := i386-linux-objcopy" + ;; + esac +fi # This is where we test for various flags and other things

1 0

New motherboard for EHCI Debug Port list
by David Mauss 30 Jul '08

30 Jul '08

Hello Coreboot mailing list, I did a check on my new motherboard, and I wanted to give you guys another EHCI controller for the "Controllers Verified to Have the Debug Port Capability" list 8086:293a Intel ICH9 (rev 2) Keep up the good work --David Mauss

1 0

v3 patch: fix dtc to correctly parse @x values as hex, not decimal.
by ron minnich 30 Jul '08

30 Jul '08

attached. ron

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