coreboot July 2008

coreboot@coreboot.org

58 participants
214 discussions

#105: flashrom: add documentation files (ChangeLog etc) that need to be in the release
by coreboot 15 Feb '09

15 Feb '09

#105: flashrom: add documentation files (ChangeLog etc) that need to be in the release ---------------------------------+------------------------------------------ Reporter: stuge | Owner: somebody Type: enhancement | Status: new Priority: blocker | Milestone: flashrom v1.0 Component: flashrom | Version: Keywords: documentation | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/105> coreboot <http://www.coreboot.org/>

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[LinuxBIOS] Add initial support for intel i855gme northbridge
by Jon Dufresne 20 Jan '09

20 Jan '09

Add initial support for i855gme. This is a work in progress and I don't expect it to work on all boards, or even any besides mine. This is based heavily on i855pm. Signed off by Jon Dufresne <jon.dufresne(a)gmail.com>

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#102: flashrom: coreboot ROM image file identification heuristic is broken
by coreboot 08 Dec '08

08 Dec '08

#102: flashrom: coreboot ROM image file identification heuristic is broken -----------------------------------+---------------------------------------- Reporter: stuge | Owner: somebody Type: defect | Status: new Priority: blocker | Milestone: flashrom v1.0 Component: flashrom | Version: Keywords: rom image heuristic | Dependencies: Patchstatus: patch needs work | -----------------------------------+---------------------------------------- Non-coreboot ROM images are incorrectly identified as coreboot images, and arbitrary data is used in flashrom code. The heuristic is far too simplistic, we need a proper signature in all coreboot images. The suggested fix is to add a LAR header to the ROM image, I like that too. When an image is incorrectly identified, junk data used by flashrom typically causes flashrom to segfault. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/102> coreboot <http://www.coreboot.org/>

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#107: flashrom: Display test status in -L chip listing
by coreboot 05 Dec '08

05 Dec '08

#107: flashrom: Display test status in -L chip listing ---------------------------------+------------------------------------------ Reporter: stuge | Owner: somebody Type: enhancement | Status: new Priority: minor | Milestone: flashrom v1.0 Component: flashrom | Version: Keywords: testing | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/107> coreboot <http://www.coreboot.org/>

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#109: flash base autodetection on AMD SC520
by coreboot 03 Dec '08

03 Dec '08

#109: flash base autodetection on AMD SC520 ----------------------------------+----------------------------------------- Reporter: stepan | Owner: stepan Type: defect | Status: new Priority: major | Milestone: Component: adlo | Version: v2 Keywords: | Dependencies: Patchstatus: patch needs review | ----------------------------------+----------------------------------------- this code has been sitting on my hard disk for a while. It drops the nasty ifdefs and implements auto detection for AMD SC520 systems, such as the Technologic Systems TS5300. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/109> coreboot <http://www.coreboot.org/>

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[LinuxBIOS] A8N5X port
by Robert Millan 21 Nov '08

21 Nov '08

This patch includes config files for the asus/a8n5x port. It is the same as asus/a8n_e with a different pnp layout, so I used #include's whenever possible. System boots and is usable with usb keyboard. works: - serial port - vga (old pci card) - memtest86+ succeeds, but only with Rudolf's patch for unbuffered dimms in K8. Otherwise you get spurious memory corruption. - ide disk - usb doesn't: - ps/2 keyboard - onboard ethernet - vga pci-e card (??) - any other pci card I tried wasn't tested: - sata - game port - onboard audio (not supported by alsa anyway) - ps/2 mouse -- Robert Millan <GPLv2> I know my rights; I want my phone call! <DRM> What use is a phone call, if you are unable to speak? (as seen on /.)

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LZMA magic number
by Myles Watson 29 Sep '08

29 Sep '08

Is there a magic number for LZMA? Should there be? I accidentally used an uncompressed payload with v2 when it expected a compressed payload, and it gave me the message: Decoder scratchpad too small!! Decoding error = 1 I think it would be nicer to have an error like: Payload not compressed with lzma! Myles

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#98: Eliminate false positive "unknown .. SPI chip" matches
by coreboot 03 Sep '08

03 Sep '08

#98: Eliminate false positive "unknown .. SPI chip" matches ----------------------------------+----------------------------------------- Reporter: stuge | Owner: somebody Type: defect | Status: new Priority: major | Milestone: flashrom v1.0 Component: flashrom | Version: Keywords: spi probe | Dependencies: #97 Patchstatus: patch needs review | ----------------------------------+----------------------------------------- -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/98> coreboot <http://www.coreboot.org/>

1 4

epia-cn patch
by aaron lwe 28 Aug '08

28 Aug '08

> Do you have the dsdt.dsl source? Where did it come from? dsdt.c comes from disassembling the dsl file. the dsl file is extracted from memory when booted with factory bios. I'll add that file if necessary. > Index: src/mainboard/via/epia-cn/fadt.c > =================================================================== > --- src/mainboard/via/epia-cn/fadt.c (revision 0) > +++ src/mainboard/via/epia-cn/fadt.c (revision 0) > @@ -0,0 +1,154 @@ > +/* > + * ACPI - create the Fixed ACPI Description Tables (FADT) > + * Copyright (C) 2004 Nick Barker <nick.barker9(a)btinternet.com> > Did you change anything in this file? Then I think you should add your copyright, possibly even remove Nick's. yes, I changed the values. > +void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ > + acpi_header_t *header=&(fadt->header); > + > + memset((void *)fadt,0,sizeof(acpi_fadt_t)); > + memcpy(header->signature,"FACP",4); > + header->length = 244; > + header->revision = 1; > + memcpy(header->oem_id,"CN700 ",6); > + memcpy(header->oem_table_id,"AWRDACPI",8); > + memcpy(header->asl_compiler_id,"AWRD",4); > We are not Award. What is this about? These values are extracted from factory bios FACP table, so I just keep them. > + header->asl_compiler_revision=0; > + > + fadt->firmware_ctrl=facs; > + fadt->dsdt= dsdt; > + fadt->preferred_pm_profile=0; > + fadt->sci_int=9; > + fadt->smi_cmd = 0x0; > + fadt->acpi_enable = 0x0; > + fadt->acpi_disable = 0x0; > + fadt->s4bios_req = 0x0; > + fadt->pstate_cnt = 0x0; > + > + fadt->pm1a_evt_blk = 0x400; > + fadt->pm1b_evt_blk = 0x0; > + fadt->pm1a_cnt_blk = 0x404; > + fadt->pm1b_cnt_blk = 0x0; > + fadt->pm2_cnt_blk = 0x0; > + fadt->pm_tmr_blk = 0x408; > + fadt->gpe0_blk = 0x420; > + fadt->gpe1_blk = 0x0; > Where do all these magic values come from? By extracting FACP table of the factory BIOS, these values are all in that table. > -/** > - * Configure the bus between the cpu and the northbridge. This might be able to > - * be moved to post-ram code in the future. For the most part, these registers > - * should not be messed around with. These are too complex to explain short of > - * copying the datasheets into the comments, but most of these values are from > - * the BIOS Porting Guide, so they should work on any board. If they don't, > - * try the values from your factory BIOS. > - * > - * TODO: Changing the DRAM frequency doesn't work (hard lockup) > - * > - * @param dev The northbridge's CPU Host Interface (D0F2) > - */ > static void c7_cpu_setup(device_t dev) > { > Hey, please don't remove doxygen. :) Oh...my bad ;-) > Index: src/northbridge/via/cn700/northbridge.c > =================================================================== > --- src/northbridge/via/cn700/northbridge.c (revision 3300) > +++ src/northbridge/via/cn700/northbridge.c (working copy) > @@ -1,6 +1,8 @@ > /* > * This file is part of the coreboot project. > * > + * Copyright (C) 2008 VIA Technologies, Inc. > + * Copyright (C) 2008 Aaron Lwe <aaron.lwe(a)gmail.com> > How is VIA involved in this? I'm a VIA employee, so I think I should add VIA here, sorry not making this clear. >Thanks a lot for the patch! I guess Corey and Bari will have a go at it but I'll try to test as well. Thanks. If dram didn't work right, try to change the values of D0F2 registers in c7_cpu_setup to be the same as the facotry BIOS set. -Aaron

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[v3] VT8237R support
by Corey Osgood 28 Aug '08

28 Aug '08

See attached. Not perfect, but enough to get started with.

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coreboot July 2008