coreboot July 2008

coreboot@coreboot.org

58 participants
214 discussions

[PATCH] v3: missing 640k-1024k mem hole for i440bxemulation
by Carl-Daniel Hailfinger 22 Aug '08

22 Aug '08

i440bxemulation is missing the 640k-1024k mem hole. geodelx has the hole. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: LinuxBIOSv3-stuff/northbridge/intel/i440bxemulation/i440bx.c =================================================================== --- LinuxBIOSv3-stuff/northbridge/intel/i440bxemulation/i440bx.c (Revision 644) +++ LinuxBIOSv3-stuff/northbridge/intel/i440bxemulation/i440bx.c (Arbeitskopie) @@ -59,7 +59,10 @@ mc_dev = dev->link[0].children; if (mc_dev) { idx = 10; - ram_resource(dev, idx++, 0, tolmk); + /* 0 .. 640 KB */ + ram_resource(dev, idx++, 0, 640); + /* 1 MB .. (Systop - 1 MB) (in KB) */ + ram_resource(dev, idx++, 1024, tolmk - 1024); } phase4_assign_resources(&dev->link[0]); } -- http://www.hailfinger.org/

4 6

[PATCH] [RFC] v3: CS5536 cleanup
by Carl-Daniel Hailfinger 18 Aug '08

18 Aug '08

Clean up Geode companion chip CS5536 code and improve VPCI hiding debug message. This also eliminates a few dev_find_pci_device(). I'm not happy with the new code yet. hide_vpci() should have a variant which takes a struct device *. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: LinuxBIOSv3-cs5536cleanup/southbridge/amd/cs5536/cs5536.c =================================================================== --- LinuxBIOSv3-cs5536cleanup/southbridge/amd/cs5536/cs5536.c (Revision 676) +++ LinuxBIOSv3-cs5536cleanup/southbridge/amd/cs5536/cs5536.c (Arbeitskopie) @@ -175,8 +175,7 @@ static void enable_ide_nand_flash_header(void) { /* Tell VSA to use FLASH PCI header. Not IDE header. */ - outl(0x80007A40, 0xCF8); - outl(0xDEADBEEF, 0xCFC); + hide_vpci(0x800079C4); } #define RTC_CENTURY 0x32 @@ -240,16 +239,13 @@ * * @param sb Southbridge config structure. */ -static void uarts_init(struct southbridge_amd_cs5536_dts_config *sb) +static void uarts_init(struct southbridge_amd_cs5536_dts_config *sb, + struct device *dev) { struct msr msr; u16 addr = 0; u32 gpio_addr; - struct device *dev; - dev = dev_find_pci_device(PCI_VENDOR_ID_AMD, - PCI_DEVICE_ID_AMD_CS5536_ISA, 0); - gpio_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1); gpio_addr &= ~1; /* Clear I/O bit */ printk(BIOS_DEBUG, "GPIO_ADDR: %08X\n", gpio_addr); @@ -418,7 +414,7 @@ { u32 *bar; struct msr msr; - struct device *dev; + struct device *dev, *otg_dev; dev = dev_find_pci_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_EHCI, 0); @@ -440,9 +436,9 @@ *(bar + HCCPARAMS) = 0x00005012; } - dev = dev_find_pci_device(PCI_VENDOR_ID_AMD, + otg_dev = dev_find_pci_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_OTG, 0); - if (dev) { + if (otg_dev) { bar = (u32 *) pci_read_config32(dev, PCI_BASE_ADDRESS_0); *(bar + UOCMUX) &= PUEN_SET; @@ -472,9 +468,7 @@ *(bar + UDCDEVCTL) |= UDC_SD_SET; } - dev = dev_find_pci_device(PCI_VENDOR_ID_AMD, - PCI_DEVICE_ID_AMD_CS5536_OTG, 0); - if (dev) { + if (otg_dev) { bar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_0); *(bar + UOCCTL) |= PADEN_SET; *(bar + UOCCAP) |= APU_SET; @@ -482,15 +476,8 @@ } /* Disable virtual PCI UDC and OTG headers. */ - dev = dev_find_pci_device(PCI_VENDOR_ID_AMD, - PCI_DEVICE_ID_AMD_CS5536_UDC, 0); - if (dev) - pci_write_config32(dev, 0x7C, 0xDEADBEEF); - - dev = dev_find_pci_device(PCI_VENDOR_ID_AMD, - PCI_DEVICE_ID_AMD_CS5536_OTG, 0); - if (dev) - pci_write_config32(dev, 0x7C, 0xDEADBEEF); + hide_vpci(0x80007e00); /* UDC */ + hide_vpci(0x80007f00); /* OTG */ } /** @@ -603,9 +590,19 @@ static void hide_vpci(u32 vpci_devid) { - /* Hide unwanted virtual PCI device. */ - printk(BIOS_DEBUG, "Hiding VPCI device: 0x%08X\n", - vpci_devid); + /* Hide unwanted virtual PCI device. + * bits 0 -> 1 zero + * bits 2 -> 7 target dword within the target function + * (zero if we're disabling entire pci devices) + * bits 8 -> 10 target function of the device + * bits 11 -> 15 target pci device + * bits 16 -> 23 pci bus + * bits 24 -> 30 reserved and set to zero + * bit 31 triggers the config cycle + */ + printk(BIOS_DEBUG, "Hiding VPCI device: 0x%08X (%02x:%02x.%01x)\n", + vpci_devid, (vpci_devid >> 16) & 0xff, + (vpci_devid >> 11) & 0x1f, (vpci_devid >> 8) & 0x7); outl(vpci_devid + 0x7C, 0xCF8); outl(0xDEADBEEF, 0xCFC); } @@ -630,7 +627,7 @@ setup_i8259(); lpc_init(sb); - uarts_init(sb); + uarts_init(sb, dev); if (sb->enable_gpio_int_route) { printk(BIOS_SPEW, "cs5536: call vr_write\n");

4 27

patch: grow grafix memory, and fix PLL on dbe62
by ron minnich 09 Aug '08

09 Aug '08

This grows graphics mem to 16M per artec's recommendation. The PLL autoconfig works now, so move to an auto value instead of manual config. This does not fix the problem with the memory errors. We've still got something wrong in memory, and it is not clear what. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> I forgot it in the patch. ron

7 20

Minimal seabios for coreboot
by Kevin O'Connor 08 Aug '08

08 Aug '08

Hi, Several people have raised the possibility of replacing the coreboot BIOS emulation for option roms with SeaBIOS. My original goal with SeaBIOS was to make it a payload that was capable of booting the system. However, I can understand the desire to leave coreboot as it is and add a little bit of bios emulation so that option roms work. It may also be useful to have some minimal support for simple calls from the payload. (For an example of a payload use - see the recent thread on Linux failing due to EBDA not being initialized.) On that note, I spent a few minutes to see how much I could strip down seabios to make it as small as possible. If I turn off everything besides basic coreboot support, I can get the lzma compressed rom down to 5695 bytes. Note that this still includes e820 map support, timer support, acpi/mptable/pir table relocation, and many other basic bios features. It's probably a good idea to turn on pcibios support as option roms tend to want this (rom then totals 6113 bytes). Also keyboard support might be useful to some payloads (total 8131 bytes). So, I can see a mode where coreboot would lzma uncompress a minimal seabios into 0xf0000, call into seabios, seabios would then init itself and return to coreboot. Then coreboot would finish initialization and launch the payload from flash. I can see where the above would be useful if the payload is always coming out of flash. However, if the user ever needs to boot using seabios (or via a scsi/pxe option rom) then I think seabios needs to be the payload and needs to drive the bootup. If there is interest in doing this, we'll need to figure out how to work out the interactions. Zhang Rui is currently working on having seabios return to coreboot. As for code integration - I'd like to avoid forking the seabios code. Perhaps it would be okay to simply copy a seabios binary into the svn repo with directions on how to build it manually. (This is what qemu and bochs do for their bios blobs.) Thoughts? -Kevin

5 9

How can I call the interrupt of SeaBIOS in coreboot?
by Zhang Rui 07 Aug '08

07 Aug '08

Hello Kevin, I can use SeaBIOS to initialize vga and return to coreboot now. But when I returned to coreboot and call int19, nothing happens. It can boot correctly when call int19 in SeaBIOS. Maybe it has something to do with the stack? How can I call the interrupt of SeaBIOS in coreboot? 2008/7/14, Zhang Rui <zrfail(a)gmail.com>: > 2008/7/14, Kevin O'Connor <kevin(a)koconnor.net>: > >[...] > > Right - seabios needs to be using its stack in order to call 16bit > > functions. You probably need to save and restore the stack. > [...] > I used this: > "movl %esp, %esi\n" > "movl $" __stringify(BUILD_STACK_ADDR) ", %esp\n" > "ljmp $0x10, $post_coreboot\n" > > and added this at the end of post_coreboot() function: > asm( > "movl %esi, %esp\n" > "retl" > ); > Then it can return to coreboot correctly. Till the payload(I used no > payload here) > > But pci_dev_init() is executed more than one time so vga is > initialized more than one time in SeaBIOS. A flag variable would be > used to run SeaBIOS only once. > This is fixed now. > > > > However, note that the above wont save/restore the idt/gdt. And > > again, I'm not sure if coreboot puts its stack/idt/gdt somewhere where > > seabios may overwrite it. [...] > And I want to know where will SeaBIOS write in the memory. Such as the > range of bda and ebda? > ? Best regards. Zhang Rui

3 8

[PATCH] Support for the ASI MB-5BLGP (Neoware Eon 4000s)
by Uwe Hermann 04 Aug '08

04 Aug '08

Hi, here's a patch for the Neoware Eon 4000s thin client, based on the info from http://www.coreboot.org/pipermail/coreboot/2008-June/036110.html Thanks, Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

4 14

KMT890 VT8237S status update
by Rudolf Marek 04 Aug '08

04 Aug '08

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hi all, Today I managed to boot kernel and userspace on the Asus M2V-MX SE (K8M890 VT8237S AMD am2 socket + SPI flash in socket) What works: 1) IDE 2) serial line 3) USB 4) APCI poweroff with halt command + some basic ACPI powerbutton event 5) APICs are routing irqs I will test more stuff later. Known issues: 1) slow boot, perhaps SPI timming is too low 2) cpu freq change does not work 3) sata seems not to work 4) PCI IRQ routing does not work for external cards 5) v-link set to 8 bit (default) Attached patch is mine WIP state of the tree. Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.6 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iD8DBQFIZURD3J9wPJqZRNURAipHAJ9gH5+iumn3mhZlevp4VGLMczYSbgCgrIBD uGcPQjnmc2Js7D9ZMB9N5vs= =UZkA -----END PGP SIGNATURE-----

4 6

VIA picks up the pace
by Carl-Daniel Hailfinger 03 Aug '08

03 Aug '08

Hi, I just read that VIA has hired Harald Welte of gpl-violations.org. The results will probably be pretty interesting and hopefully beneficial for us. http://lwn.net/Articles/291517/?format=printable Regards, Carl-Daniel

4 3

[PATCH] v3: convert stage2 and initram makefile rules from object to source files
by Carl-Daniel Hailfinger 02 Aug '08

02 Aug '08

Convert stage2 and initram makefile rules from object to source files. This creates a clearer distinction between source files in the source tree we want to have compiled and indirectly created object/source files in the object tree. It also will make enable us to move to whole-program optimization/compilation which should yield substantial size savings. Then again, we may be able to do that without the makefile conversion as well. This is a RFC, not to be applied immediately. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: LinuxBIOSv3-makefilerewrite/southbridge/amd/cs5536/Makefile =================================================================== --- LinuxBIOSv3-makefilerewrite/southbridge/amd/cs5536/Makefile (Revision 626) +++ LinuxBIOSv3-makefilerewrite/southbridge/amd/cs5536/Makefile (Arbeitskopie) @@ -21,7 +21,7 @@ ifeq ($(CONFIG_SOUTHBRIDGE_AMD_CS5536),y) -STAGE2_CHIPSET_OBJ += $(obj)/southbridge/amd/cs5536/cs5536.o +STAGE2_CHIPSET_SRC += $(src)/southbridge/amd/cs5536/cs5536.c STAGE0_CHIPSET_OBJ += $(obj)/southbridge/amd/cs5536/stage1.o Index: LinuxBIOSv3-makefilerewrite/southbridge/intel/i82371eb/Makefile =================================================================== --- LinuxBIOSv3-makefilerewrite/southbridge/intel/i82371eb/Makefile (Revision 626) +++ LinuxBIOSv3-makefilerewrite/southbridge/intel/i82371eb/Makefile (Arbeitskopie) @@ -20,6 +20,6 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82371EB),y) -STAGE2_CHIPSET_OBJ += $(obj)/southbridge/intel/i82371eb/i82371eb.o +STAGE2_CHIPSET_SRC += $(src)/southbridge/intel/i82371eb/i82371eb.c endif Index: LinuxBIOSv3-makefilerewrite/superio/winbond/w83627hf/Makefile =================================================================== --- LinuxBIOSv3-makefilerewrite/superio/winbond/w83627hf/Makefile (Revision 626) +++ LinuxBIOSv3-makefilerewrite/superio/winbond/w83627hf/Makefile (Arbeitskopie) @@ -25,6 +25,6 @@ STAGE0_CHIPSET_OBJ += $(obj)/device/pnp_raw.o # Always add to variables, as there could be more than one Super I/O. -STAGE2_CHIPSET_OBJ += $(obj)/superio/winbond/w83627hf/superio.o +STAGE2_CHIPSET_SRC += $(src)/superio/winbond/w83627hf/superio.c endif Index: LinuxBIOSv3-makefilerewrite/superio/fintek/f71805f/Makefile =================================================================== --- LinuxBIOSv3-makefilerewrite/superio/fintek/f71805f/Makefile (Revision 626) +++ LinuxBIOSv3-makefilerewrite/superio/fintek/f71805f/Makefile (Arbeitskopie) @@ -24,6 +24,6 @@ STAGE0_CHIPSET_OBJ += $(obj)/device/pnp_raw.o # Always add to variables, as there could be more than one Super I/O. -STAGE2_CHIPSET_OBJ += $(obj)/superio/fintek/f71805f/superio.o +STAGE2_CHIPSET_SRC += $(src)/superio/fintek/f71805f/superio.c endif Index: LinuxBIOSv3-makefilerewrite/mainboard/adl/msm800sev/Makefile =================================================================== --- LinuxBIOSv3-makefilerewrite/mainboard/adl/msm800sev/Makefile (Revision 626) +++ LinuxBIOSv3-makefilerewrite/mainboard/adl/msm800sev/Makefile (Arbeitskopie) @@ -21,12 +21,12 @@ STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o -INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ +INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ $(src)/northbridge/amd/geodelx/raminit.c \ $(src)/southbridge/amd/cs5536/smbus_initram.c \ $(src)/arch/x86/geodelx/geodelx.c -STAGE2_MAINBOARD_OBJ = +STAGE2_MAINBOARD_SRC = $(obj)/coreboot.vpd: $(Q)printf " BUILD DUMMY VPD\n" Index: LinuxBIOSv3-makefilerewrite/mainboard/amd/norwich/Makefile =================================================================== --- LinuxBIOSv3-makefilerewrite/mainboard/amd/norwich/Makefile (Revision 626) +++ LinuxBIOSv3-makefilerewrite/mainboard/amd/norwich/Makefile (Arbeitskopie) @@ -21,12 +21,12 @@ STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o -INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ +INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ $(src)/northbridge/amd/geodelx/raminit.c \ $(src)/southbridge/amd/cs5536/smbus_initram.c \ $(src)/arch/x86/geodelx/geodelx.c -STAGE2_MAINBOARD_OBJ = irq_tables.o +STAGE2_MAINBOARD_SRC = irq_tables.c $(obj)/coreboot.vpd: $(Q)printf " BUILD DUMMY VPD\n" Index: LinuxBIOSv3-makefilerewrite/mainboard/artecgroup/dbe61/Makefile =================================================================== --- LinuxBIOSv3-makefilerewrite/mainboard/artecgroup/dbe61/Makefile (Revision 626) +++ LinuxBIOSv3-makefilerewrite/mainboard/artecgroup/dbe61/Makefile (Arbeitskopie) @@ -21,11 +21,11 @@ STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o -INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ +INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ $(src)/northbridge/amd/geodelx/raminit.c \ $(src)/arch/x86/geodelx/geodelx.c -STAGE2_MAINBOARD_OBJ = +STAGE2_MAINBOARD_SRC = $(obj)/coreboot.vpd: $(Q)printf " BUILD DUMMY VPD\n" Index: LinuxBIOSv3-makefilerewrite/mainboard/artecgroup/dbe62/Makefile =================================================================== --- LinuxBIOSv3-makefilerewrite/mainboard/artecgroup/dbe62/Makefile (Revision 626) +++ LinuxBIOSv3-makefilerewrite/mainboard/artecgroup/dbe62/Makefile (Arbeitskopie) @@ -21,11 +21,11 @@ STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o -INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ +INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ $(src)/northbridge/amd/geodelx/raminit.c \ $(src)/arch/x86/geodelx/geodelx.c -STAGE2_MAINBOARD_OBJ = irq_tables.o +STAGE2_MAINBOARD_SRC = irq_tables.c $(obj)/coreboot.vpd: $(Q)printf " BUILD DUMMY VPD\n" Index: LinuxBIOSv3-makefilerewrite/mainboard/pcengines/alix1c/Makefile =================================================================== --- LinuxBIOSv3-makefilerewrite/mainboard/pcengines/alix1c/Makefile (Revision 626) +++ LinuxBIOSv3-makefilerewrite/mainboard/pcengines/alix1c/Makefile (Arbeitskopie) @@ -21,11 +21,11 @@ STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o -INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ +INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ $(src)/northbridge/amd/geodelx/raminit.c \ $(src)/arch/x86/geodelx/geodelx.c -STAGE2_MAINBOARD_OBJ = irq_tables.o +STAGE2_MAINBOARD_SRC = irq_tables.c $(obj)/coreboot.vpd: $(Q)printf " BUILD DUMMY VPD\n" Index: LinuxBIOSv3-makefilerewrite/mainboard/emulation/qemu-x86/Makefile =================================================================== --- LinuxBIOSv3-makefilerewrite/mainboard/emulation/qemu-x86/Makefile (Revision 626) +++ LinuxBIOSv3-makefilerewrite/mainboard/emulation/qemu-x86/Makefile (Arbeitskopie) @@ -28,10 +28,10 @@ # directory and is built from what was auto.c in v2. # -INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ +INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ $(src)/mainboard/$(MAINBOARDDIR)/initram_printktest.c -STAGE2_MAINBOARD_OBJ = vga.o +STAGE2_MAINBOARD_SRC = vga.c # # VPD or SIP ROM or... how does NVIDIA call it? Index: LinuxBIOSv3-makefilerewrite/device/Makefile =================================================================== --- LinuxBIOSv3-makefilerewrite/device/Makefile (Revision 626) +++ LinuxBIOSv3-makefilerewrite/device/Makefile (Arbeitskopie) @@ -24,6 +24,6 @@ $(Q)printf " CC $(subst $(shell pwd)/,,$(@))\n" $(Q)$(CC) $(INITCFLAGS) -c $< -o $@ -STAGE2_DEVICE_OBJ = device.o device_util.o root_device.o \ - pci_device.o pci_ops.o pci_rom.o pnp_device.o pnp_raw.o +STAGE2_DEVICE_SRC = device.c device_util.c root_device.c \ + pci_device.c pci_ops.c pci_rom.c pnp_device.c pnp_raw.c Index: LinuxBIOSv3-makefilerewrite/northbridge/amd/geodelx/Makefile =================================================================== --- LinuxBIOSv3-makefilerewrite/northbridge/amd/geodelx/Makefile (Revision 626) +++ LinuxBIOSv3-makefilerewrite/northbridge/amd/geodelx/Makefile (Arbeitskopie) @@ -21,9 +21,9 @@ ifeq ($(CONFIG_NORTHBRIDGE_AMD_GEODELX),y) -STAGE2_CHIPSET_OBJ += $(obj)/northbridge/amd/geodelx/geodelx.o \ - $(obj)/northbridge/amd/geodelx/vsmsetup.o \ - $(obj)/util/x86emu/vm86_gdt.o \ - $(obj)/northbridge/amd/geodelx/grphinit.o +STAGE2_CHIPSET_SRC += $(src)/northbridge/amd/geodelx/geodelx.c \ + $(src)/northbridge/amd/geodelx/vsmsetup.c \ + $(src)/util/x86emu/vm86_gdt.c \ + $(src)/northbridge/amd/geodelx/grphinit.c endif Index: LinuxBIOSv3-makefilerewrite/northbridge/intel/i440bxemulation/Makefile =================================================================== --- LinuxBIOSv3-makefilerewrite/northbridge/intel/i440bxemulation/Makefile (Revision 626) +++ LinuxBIOSv3-makefilerewrite/northbridge/intel/i440bxemulation/Makefile (Arbeitskopie) @@ -21,6 +21,6 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I440BXEMULATION),y) -STAGE2_CHIPSET_OBJ += $(obj)/northbridge/intel/i440bxemulation/i440bx.o +STAGE2_CHIPSET_SRC += $(src)/northbridge/intel/i440bxemulation/i440bx.c endif Index: LinuxBIOSv3-makefilerewrite/arch/x86/Makefile =================================================================== --- LinuxBIOSv3-makefilerewrite/arch/x86/Makefile (Revision 626) +++ LinuxBIOSv3-makefilerewrite/arch/x86/Makefile (Arbeitskopie) @@ -179,27 +179,32 @@ # TODO: This should be compressed with the default compressor. # -STAGE2_LIB_OBJ = stage2.o clog2.o mem.o tables.o delay.o \ - compute_ip_checksum.o string.o +STAGE2_LIB_SRC = stage2.c clog2.c mem.c tables.c delay.c \ + compute_ip_checksum.c string.c -STAGE2_ARCH_X86_OBJ = archtables.o coreboot_table.o udelay_io.o -STAGE2_ARCH_X86_OBJ += pci_ops_auto.o pci_ops_conf1.o pci_ops_conf2.o -STAGE2_ARCH_X86_OBJ += keyboard.o i8259.o isa-dma.o +STAGE2_ARCH_X86_SRC = archtables.c coreboot_table.c udelay_io.c +STAGE2_ARCH_X86_SRC += pci_ops_auto.c pci_ops_conf1.c pci_ops_conf2.c +STAGE2_ARCH_X86_SRC += keyboard.c i8259.c isa-dma.c ifeq ($(CONFIG_PIRQ_TABLE),y) -STAGE2_ARCH_X86_OBJ += pirq_routing.o +STAGE2_ARCH_X86_SRC += pirq_routing.c endif STAGE2_DYNAMIC_OBJ = statictree.o -STAGE2_OBJ := $(patsubst %,$(obj)/lib/%,$(STAGE2_LIB_OBJ)) \ - $(patsubst %,$(obj)/arch/x86/%,$(STAGE2_ARCH_X86_OBJ)) \ - $(patsubst %,$(obj)/device/%,$(STAGE2_DEVICE_OBJ)) \ - $(patsubst %,$(obj)/mainboard/$(MAINBOARDDIR)/%,$(STAGE2_MAINBOARD_OBJ)) \ - $(patsubst %,$(obj)/mainboard/$(MAINBOARDDIR)/%,$(STAGE2_DYNAMIC_OBJ)) +STAGE2_SRC := $(patsubst %,$(src)/lib/%,$(STAGE2_LIB_SRC)) \ + $(patsubst %,$(src)/arch/x86/%,$(STAGE2_ARCH_X86_SRC)) \ + $(patsubst %,$(src)/device/%,$(STAGE2_DEVICE_SRC)) \ + $(patsubst %,$(src)/mainboard/$(MAINBOARDDIR)/%,$(STAGE2_MAINBOARD_SRC)) -STAGE2_OBJ += $(STAGE2_CHIPSET_OBJ) +STAGE2_SRC += $(STAGE2_CHIPSET_SRC) +STAGE2_OBJ := $(patsubst $(src)/%.c,$(obj)/%.o,$(STAGE2_SRC)) + +# This one is special, but only due to slightly incorrect rules and dependencies. +# Don't change the dependencies for now. +STAGE2_OBJ += $(patsubst %,$(obj)/mainboard/$(MAINBOARDDIR)/%,$(STAGE2_DYNAMIC_OBJ)) + ifeq ($(CONFIG_PCI_OPTION_ROM_RUN),y) ifeq ($(CONFIG_PCI_OPTION_ROM_RUN_X86EMU),y) # x86emu wants libgcc @@ -215,7 +220,7 @@ STAGE2_OBJ_NEEDED = $(filter-out $(STAGE0_OBJ), $(STAGE2_OBJ)) -$(obj)/coreboot.stage2 $(obj)/coreboot.stage2.map: $(obj)/stage0.o $(STAGE2_OBJ_NEEDED) +$(obj)/coreboot.stage2 $(obj)/coreboot.stage2.map: $(obj)/stage0.o $(STAGE2_OBJ_NEEDED) $(STAGE2_SRC) $(Q)# leave a .o with full symbols in it for debugging. $(Q)printf " LD $(subst $(shell pwd)/,,$(@))\n" $(Q)$(LD) -R $(obj)/stage0.o -Ttext 0x2000 --entry=stage2 \ @@ -249,9 +254,9 @@ $(Q)printf " AS $(subst $(shell pwd)/,,$(@))\n" $(Q)$(AS) $(obj)/arch/x86/stage0_asm.s -o $@ -$(obj)/coreboot.initram $(obj)/coreboot.initram.map: $(obj)/stage0.init $(obj)/stage0-prefixed.o $(INITRAM_OBJ) +$(obj)/coreboot.initram $(obj)/coreboot.initram.map: $(obj)/stage0.init $(obj)/stage0-prefixed.o $(INITRAM_SRC) $(Q)printf " CC $(subst $(shell pwd)/,,$(@)) (XIP)\n" - $(Q)$(CC) $(INITCFLAGS) -D_SHARED -fPIE -c -combine $(INITRAM_OBJ) -o $(obj)/coreboot.initram_partiallylinked.o + $(Q)$(CC) $(INITCFLAGS) -D_SHARED -fPIE -c -combine $(INITRAM_SRC) -o $(obj)/coreboot.initram_partiallylinked.o $(Q)# initram links against stage0 $(Q)printf " LD $(subst $(shell pwd)/,,$(@))\n" $(Q)$(LD) -Ttext 0 --entry main -N -R $(obj)/stage0-prefixed.o \ -- http://www.hailfinger.org/

2 4

[RFC] v3 mainboard Kconfig cleanup
by Carl-Daniel Hailfinger 01 Aug '08

01 Aug '08

Hi! Right now, our Kconfig files in the mainboard/ directory in the v3 tree are not exactly in the best shape. - MAINBOARD_NAME is claimed to be the mainboard name, but it is used exclusively as mainboard directory. - MAINBOARD_NAME is set in mainboard/$VENDOR/$BOARD/Kconfig to $VENDOR/$BOARD, but mainboard/$VENDOR/Kconfig already hardcodes $VENDOR/$BOARD as board path. - MAINBOARD_NAME has a help text which will never be displayed to the user. The following patch is a proof of concept, only touches AMD manufactured mainboards, and is missing conversions for all other board manufacturers to keep the patch short. Diffstat follows: Kconfig | 15 +++++++++++++-- db800/Kconfig | 28 ---------------------------- norwich/Kconfig | 28 ---------------------------- 3 files changed, 13 insertions(+), 58 deletions(-) Basically, per-board Kconfig files have been deleted, the remnants making sense have been merged into per-vendor Kconfig files and the comments+help texts have been corrected. If there are ever some real per-board options and not just tricks to make the makefiles behave, we can resurrect the per-board Kconfig files. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: mainboard/amd/Kconfig =================================================================== --- mainboard/amd/Kconfig (Revision 693) +++ mainboard/amd/Kconfig (Arbeitskopie) @@ -48,6 +48,17 @@ endchoice -source "mainboard/amd/db800/Kconfig" -source "mainboard/amd/norwich/Kconfig" +config MAINBOARD_NAME + string + default amd/db800 + depends BOARD_AMD_DB800 + help + This is the mainboard directory. +config MAINBOARD_NAME + string + default amd/norwich + depends BOARD_AMD_NORWICH + help + This is the mainboard directory. + Index: mainboard/amd/norwich/Kconfig =================================================================== --- mainboard/amd/norwich/Kconfig (Revision 693) +++ mainboard/amd/norwich/Kconfig (Arbeitskopie) @@ -1,28 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 coresystems GmbH -## (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH) -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -config MAINBOARD_NAME - string - default amd/norwich - depends BOARD_AMD_NORWICH - help - This is the default mainboard name. - Index: mainboard/amd/db800/Kconfig =================================================================== --- mainboard/amd/db800/Kconfig (Revision 693) +++ mainboard/amd/db800/Kconfig (Arbeitskopie) @@ -1,28 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 coresystems GmbH -## (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH) -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -config MAINBOARD_NAME - string - default amd/db800 - depends BOARD_AMD_DB800 - help - This is the default mainboard name. - -- http://www.hailfinger.org/

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coreboot July 2008