coreboot July 2008

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r3437 - trunk/coreboot-v2/src/arch/i386/boot
by svn＠coreboot.org 24 Jul '08

24 Jul '08

Author: mjones Date: 2008-07-24 01:22:59 +0200 (Thu, 24 Jul 2008) New Revision: 3437 Modified: trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c trunk/coreboot-v2/src/arch/i386/boot/tables.c Log: This patch fixes the kernel EBDA mislocation problem. Thank you, Yinghai. The change in tables.c protects the legacy x86 BIOS data segment (0x400-0x4ff) from being used for storing coreboot tables. Some bytes from the segment are used by the kernel and should not be garbled. The change in coreboot_table.c is not strictly necessary. It removes some redundancy and confusion. Signed-off-by: Roman Kononov <kononov(a)dls.net> Acked-by: Marc Jones <marc.jones(a)amd.com> Modified: trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c 2008-07-23 22:27:19 UTC (rev 3436) +++ trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c 2008-07-23 23:22:59 UTC (rev 3437) @@ -402,7 +402,6 @@ unsigned long low_table_start, unsigned long low_table_end, unsigned long rom_table_start, unsigned long rom_table_end) { - unsigned long table_size; struct lb_header *head; struct lb_memory *mem; @@ -445,9 +444,8 @@ low_table_start, low_table_end - low_table_start); /* Record the pirq table, acpi tables, and maybe the mptable */ - table_size=rom_table_end-rom_table_start; lb_add_memory_range(mem, LB_MEM_TABLE, - rom_table_start, table_size<0x10000?0x10000:table_size); + rom_table_start, rom_table_end-rom_table_start); /* Note: * I assume that there is always memory at immediately after Modified: trunk/coreboot-v2/src/arch/i386/boot/tables.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/tables.c 2008-07-23 22:27:19 UTC (rev 3436) +++ trunk/coreboot-v2/src/arch/i386/boot/tables.c 2008-07-23 23:22:59 UTC (rev 3437) @@ -72,8 +72,9 @@ #if HAVE_MP_TABLE==1 /* Don't write anything in the traditional x86 BIOS data segment, * for example the linux kernel smp need to use 0x467 to pass reset vector + * or use 0x40e/0x413 for EBDA finding... */ - if(new_low_table_end>0x467){ + if(new_low_table_end>0x400){ unsigned mptable_size; unsigned mpc_start; low_table_end += SMP_FLOATING_TABLE_LEN; /* keep the mpf in 1k low, so kernel can find it */

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r3434 build service
by coreboot information 24 Jul '08

24 Jul '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "mjones" checked in revision 3434 to the coreboot source repository and caused the following changes: Change Log: Update to the latest AMD Fam10 microcode patches. Add platform option for patch file name. Signed-off-by: Marc Jones <marc.jones(a)amd.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Build Log: Configuration of a-trend:atc-6220 has been broken Configuration of a-trend:atc-6240 has been broken Configuration of abit:be6-ii_v2_0 has been broken Configuration of advantech:pcm-5820 has been broken Configuration of agami:aruma has been broken Configuration of amd:db800 has been broken Configuration of amd:norwich has been broken Configuration of amd:rumba has been broken Configuration of amd:serengeti_cheetah has been broken Configuration of amd:serengeti_cheetah_fam10 has been broken Configuration of arima:hdama has been broken Configuration of artecgroup:dbe61 has been broken Configuration of asi:mb_5blmp has been broken Configuration of asus:a8n_e has been broken Configuration of asus:a8v-e_se has been broken Configuration of asus:mew-am has been broken Configuration of asus:mew-vm has been broken Configuration of asus:p2b has been broken Configuration of asus:p2b-f has been broken Configuration of asus:p3b-f has been broken Configuration of axus:tc320 has been broken Configuration of azza:pt-6ibd has been broken Configuration of bcom:winnet100 has been broken Configuration of biostar:m6tba has been broken Configuration of broadcom:blast has been broken Configuration of compaq:deskpro_en_sff_p600 has been broken Configuration of dell:s1850 has been broken Configuration of digitallogic:adl855pc has been broken Configuration of digitallogic:msm586seg has been broken Configuration of digitallogic:msm800sev has been broken Configuration of eaglelion:5bcm has been broken Configuration of embeddedplanet:ep405pc has been broken Configuration of emulation:qemu-x86 has been broken Configuration of gigabyte:ga-6bxc has been broken Configuration of gigabyte:ga_2761gxdk has been broken Configuration of gigabyte:m57sli has been broken Configuration of ibm:e325 has been broken Configuration of ibm:e326 has been broken Configuration of iei:juki-511p has been broken Configuration of iei:nova4899r has been broken Configuration of iei:pcisa-lx-800-r10 has been broken Configuration of intel:jarrell has been broken Configuration of intel:mtarvon has been broken Configuration of intel:xe7501devkit has been broken Configuration of iwill:dk8_htx has been broken Configuration of iwill:dk8s2 has been broken Configuration of iwill:dk8x has been broken Configuration of lippert:frontrunner has been broken Configuration of motorola:sandpointx3_altimus_mpc7410 has been broken Configuration of msi:ms6119 has been broken Configuration of msi:ms6178 has been broken Configuration of msi:ms7135 has been broken Configuration of msi:ms7260 has been broken Configuration of msi:ms9185 has been broken Configuration of msi:ms9282 has been broken Configuration of newisys:khepri has been broken Configuration of nvidia:l1_2pvv has been broken Configuration of olpc:btest has been broken Configuration of olpc:rev_a has been broken Configuration of pcengines:alix1c has been broken Configuration of rca:rm4100 has been broken Configuration of sunw:ultra40 has been broken Configuration of supermicro:h8dmr has been broken Configuration of supermicro:x6dai_g has been broken Configuration of supermicro:x6dhe_g has been broken Configuration of supermicro:x6dhe_g2 has been broken Configuration of supermicro:x6dhr_ig has been broken Configuration of supermicro:x6dhr_ig2 has been broken Configuration of technologic:ts5300 has been broken Configuration of televideo:tc7020 has been broken Configuration of thomson:ip1000 has been broken Configuration of totalimpact:briq has been broken Configuration of tyan:s1846 has been broken Configuration of tyan:s2735 has been broken Configuration of tyan:s2850 has been broken Configuration of tyan:s2875 has been broken Configuration of tyan:s2880 has been broken Configuration of tyan:s2881 has been broken Configuration of tyan:s2882 has been broken Configuration of tyan:s2885 has been broken Configuration of tyan:s2891 has been broken Configuration of tyan:s2892 has been broken Configuration of tyan:s2895 has been broken Configuration of tyan:s2912 has been broken Configuration of tyan:s4880 has been broken Configuration of tyan:s4882 has been broken Configuration of via:epia has been broken Configuration of via:epia-cn has been broken Configuration of via:epia-m has been broken If something broke during this checkin please be a pain in mjones's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

2 2

r3436 - trunk/coreboot-v2/src/config
by svn＠coreboot.org 24 Jul '08

24 Jul '08

Author: mjones Date: 2008-07-24 00:27:19 +0200 (Thu, 24 Jul 2008) New Revision: 3436 Modified: trunk/coreboot-v2/src/config/Options.lb Log: Fix r3434 check-in. Added missing end to Options.lb. Not entirely sure how it went missing.... Signed-off-by: Marc Jones <marc.jones(a)amd.com> Acked-by: Marc Jones <marc.jones(a)amd.com> Modified: trunk/coreboot-v2/src/config/Options.lb =================================================================== --- trunk/coreboot-v2/src/config/Options.lb 2008-07-23 21:44:23 UTC (rev 3435) +++ trunk/coreboot-v2/src/config/Options.lb 2008-07-23 22:27:19 UTC (rev 3436) @@ -1065,7 +1065,8 @@ default none export used format "\"%s\"" - comment "name of the micorcode patch file" + comment "name of the microcode patch file" +end define CONFIG_VIDEO_MB default none

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r3435 build service
by coreboot information 23 Jul '08

23 Jul '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "mjones" checked in revision 3435 to the coreboot source repository and caused the following changes: Change Log: Add AMD Fam10 B3 default settings to match AMD example code. Includes setting for most recent errata. Signed-off-by: Marc Jones <marc.jones(a)amd.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Build Log: Configuration of a-trend:atc-6220 is still broken Configuration of a-trend:atc-6240 is still broken Configuration of abit:be6-ii_v2_0 is still broken Configuration of advantech:pcm-5820 is still broken Configuration of agami:aruma is still broken Configuration of amd:db800 is still broken Configuration of amd:norwich is still broken Configuration of amd:rumba is still broken Configuration of amd:serengeti_cheetah is still broken Configuration of amd:serengeti_cheetah_fam10 is still broken Configuration of arima:hdama is still broken Configuration of artecgroup:dbe61 is still broken Configuration of asi:mb_5blmp is still broken Configuration of asus:a8n_e is still broken Configuration of asus:a8v-e_se is still broken Configuration of asus:mew-am is still broken Configuration of asus:mew-vm is still broken Configuration of asus:p2b is still broken Configuration of asus:p2b-f is still broken Configuration of asus:p3b-f is still broken Configuration of axus:tc320 is still broken Configuration of azza:pt-6ibd is still broken Configuration of bcom:winnet100 is still broken Configuration of biostar:m6tba is still broken Configuration of broadcom:blast is still broken Configuration of compaq:deskpro_en_sff_p600 is still broken Configuration of dell:s1850 is still broken Configuration of digitallogic:adl855pc is still broken Configuration of digitallogic:msm586seg is still broken Configuration of digitallogic:msm800sev is still broken Configuration of eaglelion:5bcm is still broken Configuration of embeddedplanet:ep405pc is still broken Configuration of emulation:qemu-x86 is still broken Configuration of gigabyte:ga-6bxc is still broken Configuration of gigabyte:ga_2761gxdk is still broken Configuration of gigabyte:m57sli is still broken Configuration of ibm:e325 is still broken Configuration of ibm:e326 is still broken Configuration of iei:juki-511p is still broken Configuration of iei:nova4899r is still broken Configuration of iei:pcisa-lx-800-r10 is still broken Configuration of intel:jarrell is still broken Configuration of intel:mtarvon is still broken Configuration of intel:xe7501devkit is still broken Configuration of iwill:dk8_htx is still broken Configuration of iwill:dk8s2 is still broken Configuration of iwill:dk8x is still broken Configuration of lippert:frontrunner is still broken Configuration of motorola:sandpointx3_altimus_mpc7410 is still broken Configuration of msi:ms6119 is still broken Configuration of msi:ms6178 is still broken Configuration of msi:ms7135 is still broken Configuration of msi:ms7260 is still broken Configuration of msi:ms9185 is still broken Configuration of msi:ms9282 is still broken Configuration of newisys:khepri is still broken Configuration of nvidia:l1_2pvv is still broken Configuration of olpc:btest is still broken Configuration of olpc:rev_a is still broken Configuration of pcengines:alix1c is still broken Configuration of rca:rm4100 is still broken Configuration of sunw:ultra40 is still broken Configuration of supermicro:h8dmr is still broken Configuration of supermicro:x6dai_g is still broken Configuration of supermicro:x6dhe_g is still broken Configuration of supermicro:x6dhe_g2 is still broken Configuration of supermicro:x6dhr_ig is still broken Configuration of supermicro:x6dhr_ig2 is still broken Configuration of technologic:ts5300 is still broken Configuration of televideo:tc7020 is still broken Configuration of thomson:ip1000 is still broken Configuration of totalimpact:briq is still broken Configuration of tyan:s1846 is still broken Configuration of tyan:s2735 is still broken Configuration of tyan:s2850 is still broken Configuration of tyan:s2875 is still broken Configuration of tyan:s2880 is still broken Configuration of tyan:s2881 is still broken Configuration of tyan:s2882 is still broken Configuration of tyan:s2885 is still broken Configuration of tyan:s2891 is still broken Configuration of tyan:s2892 is still broken Configuration of tyan:s2895 is still broken Configuration of tyan:s2912 is still broken Configuration of tyan:s4880 is still broken Configuration of tyan:s4882 is still broken Configuration of via:epia is still broken Configuration of via:epia-cn is still broken Configuration of via:epia-m is still broken If something broke during this checkin please be a pain in mjones's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[patch][v2] AMD Fam10 rev B3 CPU
by Marc Jones 23 Jul '08

23 Jul '08

Update default CPU settings for B3 Marc -- Marc Jones Senior Firmware Engineer (970) 226-9684 Office mailto:Marc.Jones@amd.com http://www.amd.com/embeddedprocessors Add AMD Fam10 B3 default settings to match AMD example code. Includes setting for most resent errata. Signed-off-by: Marc Jones <marc.jones(a)amd.com> Index: coreboot-v2/src/cpu/amd/model_10xxx/defaults.h =================================================================== --- coreboot-v2.orig/src/cpu/amd/model_10xxx/defaults.h 2008-07-21 15:39:58.000000000 -0600 +++ coreboot-v2/src/cpu/amd/model_10xxx/defaults.h 2008-07-21 16:14:24.000000000 -0600 @@ -46,10 +46,6 @@ 0xF << 19, 0x00000000, 0xF << 19, 0x00000000 }, /* [RtryHt[0..3]]=1 */ - { MC4_CTL_MASK, AMD_DR_ALL, AMD_PTYPE_ALL, - 0x1 << 10, 0x00000000, - 0x1 << 10, 0x00000000 }, /* [GartTblWkEn]=1 */ - { DC_CFG, AMD_DR_ALL, AMD_PTYPE_SVR, 0x00000000, 0x00000004, 0x00000000, 0x0000000C }, /* [REQ_CTR] = 1 for Server */ @@ -68,7 +64,7 @@ { DC_CFG, AMD_DR_ALL, AMD_PTYPE_ALL, 1 << 24, 0x00000000, - 1 << 24, 0x00000000 }, /* Erratum #202 [DIS_PIGGY_BACK_SCRUB]=1 */ + 1 << 24, 0x00000000 }, /* Erratum #261 [DIS_PIGGY_BACK_SCRUB]=1 */ { LS_CFG, AMD_DR_GT_B0, AMD_PTYPE_ALL, 0 << 1, 0x00000000, @@ -160,11 +156,14 @@ 0x00000100, 0x00000100 }, /* [8] MstrAbrtEn */ { 3, 0x44, AMD_DR_ALL, AMD_PTYPE_ALL, - 0x0A100044, 0x0A300044 }, /* [27] NB MCA to CPU0 Enable, - [25] DisPciCfgCpuErrRsp, - [21] SyncOnErr=0, + 0x4A30005C, 0x4A30005C }, /* [30] SyncOnDramAdrParErrEn=1, + [27] NbMcaToMstCpuEn=1, + [25] DisPciCfgCpuErrRsp=1, + [21] SyncOnAnyErrEn=1, [20] SyncOnWDTEn=1, - [6] CpuErrDis, + [6] CpuErrDis=1, + [4] SyncPktPropDis=1, + [3] SyncPktGenDis=1, [2] SyncOnUcEccEn=1 */ /* XBAR buffer settings */ @@ -222,7 +221,7 @@ { 3, 0x84, AMD_DR_ALL, AMD_PTYPE_ALL, 0xA0E641E6, 0xFFFFFFFF }, - { 3, 0xA0, AMD_DR_ALL, AMD_PTYPE_MOB, + { 3, 0xA0, AMD_DR_ALL, AMD_PTYPE_MOB | AMD_PTYPE_DSK, 0x00000080, 0x00000080 }, /* [7] PSIVidEnable */ { 3, 0xA0, AMD_DR_ALL, AMD_PTYPE_ALL, @@ -250,9 +249,13 @@ /* Extended NB MCA Config Register */ { 3, 0x180, AMD_DR_ALL, AMD_PTYPE_ALL, - 0x00700022, 0x00700022 }, /* [5] = DisPciCfgCpuMstAbtRsp - [22:20] = SyncFloodOn_Err = 7, - [1] = SyncFloodOnUsPwDataErr = 1 */ + 0x007003E2, 0x007003E2 }, /* [22:20] = SyncFloodOn_Err = 7, + [9] SyncOnUncNbAryEn = 1 , + [8] SyncOnProtEn = 1, + [7] SyncFloodOnTgtAbtErr] = 1, + [6] SyncFloodOnDatErr] = 1, + [5] DisPciCfgCpuMstAbtRsp=1, + [1] SyncFloodOnUsPwDataErr = 1 */ /* L3 Control Register */ { 3, 0x1B8, AMD_DR_ALL, AMD_PTYPE_ALL, Index: coreboot-v2/src/cpu/amd/model_10xxx/init_cpus.c =================================================================== --- coreboot-v2.orig/src/cpu/amd/model_10xxx/init_cpus.c 2008-07-21 15:39:58.000000000 -0600 +++ coreboot-v2/src/cpu/amd/model_10xxx/init_cpus.c 2008-07-21 16:45:47.000000000 -0600 @@ -669,6 +669,35 @@ } +void AMD_SetupPSIVID_d (u32 platform_type, u8 node) +{ + u32 dword; + int i; + msr_t msr; + + if (platform_type & (AMD_PTYPE_MOB | AMD_PTYPE_DSK)) { + + /* The following code sets the PSIVID to the highest supported P state + * assuming that the VID for the highest power state is below + * the VDD voltage regulator threshold. (This also assumes that there + * is a Pstate higher than P0) + */ + + for( i = 4; i >= 0; i--) { + msr = rdmsr(0xC0010064 + i); + /* Pstate valid? */ + if ((msr.hi >> 31) & 1) { + dword = pci_read_config32(NODE_PCI(i,3), 0xA0); + dword &= ~0x7F; + dword |= (msr.lo >> 9) & 0x7F; + pci_write_config32(NODE_PCI(i,3), 0xA0, dword); + break; + } + } + } +} + + /** * AMD_CpuFindCapability - Traverse PCI capability list to find host HT links. * HT Phy operations are not valid on links that aren't present, so this @@ -857,6 +886,8 @@ revision = mctGetLogicalCPUID(node); platform = get_platform_type(); + AMD_SetupPSIVID_d(platform, node); /* Set PSIVID offset which is not table driven */ + for(i = 0; i < sizeof(fam10_pci_default)/sizeof(fam10_pci_default[0]); i++) { if ((fam10_pci_default[i].revision & revision) && (fam10_pci_default[i].platform & platform)) {

3 3

r3435 - trunk/coreboot-v2/src/cpu/amd/model_10xxx
by svn＠coreboot.org 23 Jul '08

23 Jul '08

Author: mjones Date: 2008-07-23 23:44:23 +0200 (Wed, 23 Jul 2008) New Revision: 3435 Modified: trunk/coreboot-v2/src/cpu/amd/model_10xxx/defaults.h trunk/coreboot-v2/src/cpu/amd/model_10xxx/init_cpus.c Log: Add AMD Fam10 B3 default settings to match AMD example code. Includes setting for most recent errata. Signed-off-by: Marc Jones <marc.jones(a)amd.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/coreboot-v2/src/cpu/amd/model_10xxx/defaults.h =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_10xxx/defaults.h 2008-07-23 21:11:20 UTC (rev 3434) +++ trunk/coreboot-v2/src/cpu/amd/model_10xxx/defaults.h 2008-07-23 21:44:23 UTC (rev 3435) @@ -46,10 +46,6 @@ 0xF << 19, 0x00000000, 0xF << 19, 0x00000000 }, /* [RtryHt[0..3]]=1 */ - { MC4_CTL_MASK, AMD_DR_ALL, AMD_PTYPE_ALL, - 0x1 << 10, 0x00000000, - 0x1 << 10, 0x00000000 }, /* [GartTblWkEn]=1 */ - { DC_CFG, AMD_DR_ALL, AMD_PTYPE_SVR, 0x00000000, 0x00000004, 0x00000000, 0x0000000C }, /* [REQ_CTR] = 1 for Server */ @@ -68,7 +64,7 @@ { DC_CFG, AMD_DR_ALL, AMD_PTYPE_ALL, 1 << 24, 0x00000000, - 1 << 24, 0x00000000 }, /* Erratum #202 [DIS_PIGGY_BACK_SCRUB]=1 */ + 1 << 24, 0x00000000 }, /* Erratum #261 [DIS_PIGGY_BACK_SCRUB]=1 */ { LS_CFG, AMD_DR_GT_B0, AMD_PTYPE_ALL, 0 << 1, 0x00000000, @@ -160,12 +156,15 @@ 0x00000100, 0x00000100 }, /* [8] MstrAbrtEn */ { 3, 0x44, AMD_DR_ALL, AMD_PTYPE_ALL, - 0x0A100044, 0x0A300044 }, /* [27] NB MCA to CPU0 Enable, - [25] DisPciCfgCpuErrRsp, - [21] SyncOnErr=0, - [20] SyncOnWDTEn=1, - [6] CpuErrDis, - [2] SyncOnUcEccEn=1 */ + 0x4A30005C, 0x4A30005C }, /* [30] SyncOnDramAdrParErrEn = 1, + [27] NbMcaToMstCpuEn = 1, + [25] DisPciCfgCpuErrRsp = 1, + [21] SyncOnAnyErrEn = 1, + [20] SyncOnWDTEn = 1, + [6] CpuErrDis = 1, + [4] SyncPktPropDis = 1, + [3] SyncPktGenDis = 1, + [2] SyncOnUcEccEn = 1 */ /* XBAR buffer settings */ { 3, 0x6C, AMD_DR_ALL, AMD_PTYPE_ALL, @@ -222,7 +221,7 @@ { 3, 0x84, AMD_DR_ALL, AMD_PTYPE_ALL, 0xA0E641E6, 0xFFFFFFFF }, - { 3, 0xA0, AMD_DR_ALL, AMD_PTYPE_MOB, + { 3, 0xA0, AMD_DR_ALL, AMD_PTYPE_MOB | AMD_PTYPE_DSK, 0x00000080, 0x00000080 }, /* [7] PSIVidEnable */ { 3, 0xA0, AMD_DR_ALL, AMD_PTYPE_ALL, @@ -250,9 +249,13 @@ /* Extended NB MCA Config Register */ { 3, 0x180, AMD_DR_ALL, AMD_PTYPE_ALL, - 0x00700022, 0x00700022 }, /* [5] = DisPciCfgCpuMstAbtRsp - [22:20] = SyncFloodOn_Err = 7, - [1] = SyncFloodOnUsPwDataErr = 1 */ + 0x007003E2, 0x007003E2 }, /* [22:20] = SyncFloodOn_Err = 7, + [9] SyncOnUncNbAryEn = 1 , + [8] SyncOnProtEn = 1, + [7] SyncFloodOnTgtAbtErr = 1, + [6] SyncFloodOnDatErr = 1, + [5] DisPciCfgCpuMstAbtRsp = 1, + [1] SyncFloodOnUsPwDataErr = 1 */ /* L3 Control Register */ { 3, 0x1B8, AMD_DR_ALL, AMD_PTYPE_ALL, Modified: trunk/coreboot-v2/src/cpu/amd/model_10xxx/init_cpus.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_10xxx/init_cpus.c 2008-07-23 21:11:20 UTC (rev 3434) +++ trunk/coreboot-v2/src/cpu/amd/model_10xxx/init_cpus.c 2008-07-23 21:44:23 UTC (rev 3435) @@ -669,6 +669,35 @@ } +void AMD_SetupPSIVID_d (u32 platform_type, u8 node) +{ + u32 dword; + int i; + msr_t msr; + + if (platform_type & (AMD_PTYPE_MOB | AMD_PTYPE_DSK)) { + + /* The following code sets the PSIVID to the lowest support P state + * assuming that the VID for the lowest power state is below + * the VDD voltage regulator threshold. (This also assumes that there + * is a Pstate lower than P0) + */ + + for( i = 4; i >= 0; i--) { + msr = rdmsr(PS_REG_BASE + i); + /* Pstate valid? */ + if (msr.hi & PS_EN_MASK) { + dword = pci_read_config32(NODE_PCI(i,3), 0xA0); + dword &= ~0x7F; + dword |= (msr.lo >> 9) & 0x7F; + pci_write_config32(NODE_PCI(i,3), 0xA0, dword); + break; + } + } + } +} + + /** * AMD_CpuFindCapability - Traverse PCI capability list to find host HT links. * HT Phy operations are not valid on links that aren't present, so this @@ -854,9 +883,12 @@ printk_debug("cpuSetAMDPCI %02d", node); + revision = mctGetLogicalCPUID(node); platform = get_platform_type(); + AMD_SetupPSIVID_d(platform, node); /* Set PSIVID offset which is not table driven */ + for(i = 0; i < sizeof(fam10_pci_default)/sizeof(fam10_pci_default[0]); i++) { if ((fam10_pci_default[i].revision & revision) && (fam10_pci_default[i].platform & platform)) {

1 0

r3434 - in trunk/coreboot-v2/src: config cpu/amd/model_10xxx mainboard/amd/serengeti_cheetah_fam10
by svn＠coreboot.org 23 Jul '08

23 Jul '08

Author: mjones Date: 2008-07-23 23:11:20 +0200 (Wed, 23 Jul 2008) New Revision: 3434 Added: trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000083.h trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000084.h Removed: trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000065.h trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000066.h Modified: trunk/coreboot-v2/src/config/Options.lb trunk/coreboot-v2/src/cpu/amd/model_10xxx/update_microcode.c trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb Log: Update to the latest AMD Fam10 microcode patches. Add platform option for patch file name. Signed-off-by: Marc Jones <marc.jones(a)amd.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/coreboot-v2/src/config/Options.lb =================================================================== --- trunk/coreboot-v2/src/config/Options.lb 2008-07-23 21:04:03 UTC (rev 3433) +++ trunk/coreboot-v2/src/config/Options.lb 2008-07-23 21:11:20 UTC (rev 3434) @@ -1061,6 +1061,12 @@ comment "use AMD MCT to init RAM instead of native code" end +define AMD_UCODE_PATCH_FILE + default none + export used + format "\"%s\"" + comment "name of the micorcode patch file" + define CONFIG_VIDEO_MB default none export used Deleted: trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000065.h =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000065.h 2008-07-23 21:04:03 UTC (rev 3433) +++ trunk/coreboot-v2/src/cpu/amd/model_10xxx/mc_patch_01000065.h 2008-07-23 21:11:20 UTC (rev 3434) @@ -1,164 +0,0 @@ -/* - ============================================================ - (c) Advanced Micro Devices, Inc., 2004-2008 - - The enclosed microcode is intended to be used with AMD - Microprocessors. You may copy, view and install the - enclosed microcode only for development and deployment of - firmware, BIOS, or operating system code for computer - systems that contain AMD processors. You are not - authorized to use the enclosed microcode for any other - purpose. - - THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR - IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO - WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, - TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES - ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. - AMD does not assume any responsibility for any errors which - may appear in this microcode or any other related - information provided to you by AMD, or result from use of - this microcode. AMD is not obligated to furnish, support, - or make any further information, software, technical - information, know-how, or show-how available related to this - microcode. - - The microcode is provided with "RESTRICTED RIGHTS." Use, - duplication, or disclosure by the U.S. Government is subject - to the restrictions as set forth in FAR 52.227-14 and - DFAR252.227-7013, et seq., or its successor. Use of the - microcode by the U.S. Government constitutes - acknowledgement of AMD's proprietary rights in them. - ============================================================ -*/ - - -0x08, 0x20, 0x11, 0x01, 0x65, 0x00, 0x00, 0x01, 0x00, 0x80, 0x20, 0x00, -0x9B, 0x78, 0x67, 0x6C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x22, 0x10, 0x00, 0x00, 0x00, 0xAA, 0xAA, 0xAA, 0x70, 0x09, 0x00, 0x00, -0x49, 0x01, 0x00, 0x00, 0x8B, 0x01, 0x00, 0x00, 0xC1, 0x08, 0x00, 0x00, -0xAA, 0x0B, 0x00, 0x00, 0x56, 0x0F, 0x00, 0x00, 0x9E, 0x0B, 0x00, 0x00, -0x9A, 0x0B, 0x00, 0x00, 0x2A, 0xFF, 0xFF, 0x29, 0xC3, 0x5F, 0xD0, 0xC1, -0xBD, 0xFF, 0xFF, 0xB3, 0x0F, 0xFF, 0x7E, 0xFD, 0xF6, 0x1F, 0xF8, 0x57, -0x3C, 0xBC, 0x63, 0x2D, 0x80, 0x96, 0xD6, 0x00, 0xAA, 0xFF, 0xEF, 0xAF, -0xE0, 0xD1, 0x9F, 0x15, 0x57, 0xEF, 0xFF, 0xFF, 0xEA, 0x87, 0x7F, 0xBF, -0x03, 0xFA, 0x0F, 0xFC, 0xFC, 0x1F, 0xBE, 0xF5, 0x00, 0xE0, 0x4A, 0x4B, -0x7F, 0xC8, 0xFF, 0xF7, 0xB4, 0xF8, 0xF0, 0x2F, 0xFF, 0x1F, 0xC5, 0xFE, -0xC0, 0xCF, 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You may copy, view and install the - enclosed microcode only for development and deployment of - firmware, BIOS, or operating system code for computer - systems that contain AMD processors. You are not - authorized to use the enclosed microcode for any other - purpose. - - THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR - IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO - WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, - TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES - ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. - AMD does not assume any responsibility for any errors which - may appear in this microcode or any other related - information provided to you by AMD, or result from use of - this microcode. AMD is not obligated to furnish, support, - or make any further information, software, technical - information, know-how, or show-how available related to this - microcode. - - The microcode is provided with "RESTRICTED RIGHTS." Use, - duplication, or disclosure by the U.S. Government is subject - to the restrictions as set forth in FAR 52.227-14 and - DFAR252.227-7013, et seq., or its successor. Use of the - microcode by the U.S. Government constitutes - acknowledgement of AMD's proprietary rights in them. - ============================================================ -*/ - - -0x08, 0x20, 0x11, 0x01, 0x66, 0x00, 0x00, 0x01, 0x00, 0x80, 0x20, 0x00, -0x83, 0x75, 0xF0, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x20, 0x10, 0x00, 0x00, 0x00, 0xAA, 0xAA, 0xAA, 0x70, 0x09, 0x00, 0x00, -0x49, 0x01, 0x00, 0x00, 0x8B, 0x01, 0x00, 0x00, 0xC1, 0x08, 0x00, 0x00, -0xFF, 0xFF, 0xFF, 0xFF, 0x56, 0x0F, 0x00, 0x00, 0x9E, 0x0B, 0x00, 0x00, -0x9A, 0x0B, 0x00, 0x00, 0x2A, 0xFF, 0xFF, 0x29, 0xC3, 0x5F, 0xD0, 0xC1, -0xBD, 0xFF, 0xFF, 0xB3, 0x0F, 0xFF, 0x7E, 0xFD, 0xF6, 0x1F, 0xF8, 0x57, -0x3C, 0xBC, 0x63, 0x2D, 0x80, 0x96, 0xD6, 0x00, 0xAA, 0xFF, 0xEF, 0xAF, -0xE0, 0xD1, 0x9F, 0x15, 0x57, 0xEF, 0xFF, 0xFF, 0xEA, 0x87, 0x7F, 0xBF, -0x03, 0xFA, 0x0F, 0xFC, 0xFC, 0x1F, 0xBE, 0xF5, 0x00, 0xE0, 0x4A, 0x4B, -0x7F, 0xC8, 0xFF, 0xF7, 0xB4, 0xF8, 0xF0, 0x2F, 0xFF, 0x1F, 0xC5, 0xFE, -0xC0, 0xCF, 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You may copy, view and install the + enclosed microcode only for development and deployment of + firmware, BIOS, or operating system code for computer + systems that contain AMD processors. You are not + authorized to use the enclosed microcode for any other + purpose. + + THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR + IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO + WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, + TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES + ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + AMD does not assume any responsibility for any errors which + may appear in this microcode or any other related + information provided to you by AMD, or result from use of + this microcode. AMD is not obligated to furnish, support, + or make any further information, software, technical + information, know-how, or show-how available related to this + microcode. + + The microcode is provided with "RESTRICTED RIGHTS." Use, + duplication, or disclosure by the U.S. Government is subject + to the restrictions as set forth in FAR 52.227-14 and + DFAR252.227-7013, et seq., or its successor. Use of the + microcode by the U.S. Government constitutes + acknowledgement of AMD's proprietary rights in them. + ============================================================ +*/ + + +0x08, 0x20, 0x30, 0x04, 0x83, 0x00, 0x00, 0x01, 0x00, 0x80, 0x20, 0x00, +0xA8, 0x88, 0x43, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x22, 0x10, 0x00, 0x00, 0x00, 0xAA, 0xAA, 0xAA, 0x70, 0x09, 0x00, 0x00, +0x49, 0x01, 0x00, 0x00, 0x8B, 0x01, 0x00, 0x00, 0xC1, 0x08, 0x00, 0x00, +0xAA, 0x0B, 0x00, 0x00, 0x56, 0x0F, 0x00, 0x00, 0x9E, 0x0B, 0x00, 0x00, +0x70, 0x0C, 0x00, 0x00, 0x2A, 0xFF, 0xFF, 0x29, 0xC3, 0x5F, 0xD0, 0xC1, +0xBD, 0xFF, 0xFF, 0xB3, 0x0F, 0xFF, 0x7E, 0xFD, 0xF6, 0x1F, 0xF8, 0x57, +0x3C, 0xBC, 0x63, 0x2D, 0x80, 0x96, 0xD6, 0x00, 0xAA, 0xFF, 0xEF, 0xAF, +0xE0, 0xD1, 0x9F, 0x15, 0x57, 0xEF, 0xFF, 0xFF, 0xEA, 0x87, 0x7F, 0xBF, +0x03, 0xFA, 0x0F, 0xFC, 0xFC, 0x1F, 0xBE, 0xF5, 0x00, 0xE0, 0x4A, 0x4B, +0x7F, 0xC8, 0xFF, 0xF7, 0xB4, 0xF8, 0xF0, 0x2F, 0xFF, 0x1F, 0xC5, 0xFE, +0xC0, 0xCF, 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You may copy, view and install the + enclosed microcode only for development and deployment of + firmware, BIOS, or operating system code for computer + systems that contain AMD processors. You are not + authorized to use the enclosed microcode for any other + purpose. + + THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR + IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO + WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, + TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES + ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + AMD does not assume any responsibility for any errors which + may appear in this microcode or any other related + information provided to you by AMD, or result from use of + this microcode. AMD is not obligated to furnish, support, + or make any further information, software, technical + information, know-how, or show-how available related to this + microcode. + + The microcode is provided with "RESTRICTED RIGHTS." Use, + duplication, or disclosure by the U.S. Government is subject + to the restrictions as set forth in FAR 52.227-14 and + DFAR252.227-7013, et seq., or its successor. Use of the + microcode by the U.S. Government constitutes + acknowledgement of AMD's proprietary rights in them. + ============================================================ +*/ + + +0x08, 0x20, 0x01, 0x05, 0x84, 0x00, 0x00, 0x01, 0x00, 0x80, 0x20, 0x00, +0x90, 0x85, 0xCC, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x20, 0x10, 0x00, 0x00, 0x00, 0xAA, 0xAA, 0xAA, 0x70, 0x09, 0x00, 0x00, +0x49, 0x01, 0x00, 0x00, 0x8B, 0x01, 0x00, 0x00, 0xC1, 0x08, 0x00, 0x00, +0xFF, 0xFF, 0xFF, 0xFF, 0x56, 0x0F, 0x00, 0x00, 0x9E, 0x0B, 0x00, 0x00, +0x70, 0x0C, 0x00, 0x00, 0x2A, 0xFF, 0xFF, 0x29, 0xC3, 0x5F, 0xD0, 0xC1, +0xBD, 0xFF, 0xFF, 0xB3, 0x0F, 0xFF, 0x7E, 0xFD, 0xF6, 0x1F, 0xF8, 0x57, +0x3C, 0xBC, 0x63, 0x2D, 0x80, 0x96, 0xD6, 0x00, 0xAA, 0xFF, 0xEF, 0xAF, +0xE0, 0xD1, 0x9F, 0x15, 0x57, 0xEF, 0xFF, 0xFF, 0xEA, 0x87, 0x7F, 0xBF, +0x03, 0xFA, 0x0F, 0xFC, 0xFC, 0x1F, 0xBE, 0xF5, 0x00, 0xE0, 0x4A, 0x4B, +0x7F, 0xC8, 0xFF, 0xF7, 0xB4, 0xF8, 0xF0, 0x2F, 0xFF, 0x1F, 0xC5, 0xFE, +0xC0, 0xCF, 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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + Modified: trunk/coreboot-v2/src/cpu/amd/model_10xxx/update_microcode.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_10xxx/update_microcode.c 2008-07-23 21:04:03 UTC (rev 3433) +++ trunk/coreboot-v2/src/cpu/amd/model_10xxx/update_microcode.c 2008-07-23 21:11:20 UTC (rev 3434) @@ -31,15 +31,23 @@ #ifdef __ROMCC__ - // Barcelona rev Ax -// #include "mc_patch_01000020.h" +/* From the Revision Guide : + * Equivalent Processor Table for AMD Family 10h Processors + * + * Installed Processor Equivalent Processor Patch Level + * Revision ID Revision ID + * 00100F00h 1000h 01000020h + * 00100F01h 1000h 01000020h + * 00100F02h 1000h 01000020h + * 00100F20h 1020h 01000084h + * 00100F21h 1020h 01000084h + * 00100F2Ah 1020h 01000084h + * 00100F22h 1022h 01000083h + * 00100F23h 1022h 01000083h + */ - // Barcelona rev B0, B1, BA -// #include "mc_patch_01000066.h" +#include AMD_UCODE_PATCH_FILE - // Barcelona rev B2, B3 - #include "mc_patch_01000065.h" - #endif /* Dummy terminator */ 0x0, 0x0, 0x0, 0x0, Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb 2008-07-23 21:04:03 UTC (rev 3433) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb 2008-07-23 21:11:20 UTC (rev 3434) @@ -114,6 +114,7 @@ uses CONFIG_USE_PRINTK_IN_CAR uses CAR_FAM10 +uses AMD_UCODE_PATCH_FILE ### ### Build options @@ -260,6 +261,15 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80 +## +## Set microcode patch file name +## +## Barcelona rev Ax: "mc_patch_01000020.h" +## Barcelona rev B0, B1, BA: "mc_patch_01000084.h" +## Barcelona rev B2, B3: "mc_patch_01000083.h" +## +default AMD_UCODE_PATCH_FILE="mc_patch_01000083.h" + ### ### coreboot layout values ###

1 0

[patch][v2] AMD fam10 rev B3 memory init
by Marc Jones 23 Jul '08

23 Jul '08

Add memory init support for B3. Marc -- Marc Jones Senior Firmware Engineer (970) 226-9684 Office mailto:Marc.Jones@amd.com http://www.amd.com/embeddedprocessors Memory initialization support for AMD Fam10 B3 (B0-B2 already supported). Signed-off-by: Marc Jones <marc.jones(a)amd.com> Index: coreboot-v2/src/northbridge/amd/amdmct/mct/mct_d.c =================================================================== --- coreboot-v2.orig/src/northbridge/amd/amdmct/mct/mct_d.c 2008-07-21 15:40:02.000000000 -0600 +++ coreboot-v2/src/northbridge/amd/amdmct/mct/mct_d.c 2008-07-21 16:14:22.000000000 -0600 @@ -2401,30 +2401,34 @@ mct_BeforeDramInit_Prod_D(pMCTstat, pDCTstat); // FIXME: for rev A: mct_BeforeDramInit_D(pDCTstat, dct); - /* Disable auto refresh before Dram init when in ganged mode */ - if (pDCTstat->GangedMode) { - val = Get_NB32(pDCTstat->dev_dct, 0x8C + (0x100 * dct)); - val |= 1 << DisAutoRefresh; - Set_NB32(pDCTstat->dev_dct, 0x8C + (0x100 * dct), val); + /* Disable auto refresh before Dram init when in ganged mode (Erratum 278) */ + if (pDCTstat->LogicalCPUID & (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_BA)) { + if (pDCTstat->GangedMode) { + val = Get_NB32(pDCTstat->dev_dct, 0x8C + (0x100 * dct)); + val |= 1 << DisAutoRefresh; + Set_NB32(pDCTstat->dev_dct, 0x8C + (0x100 * dct), val); + } } mct_DramInit_Hw_D(pMCTstat, pDCTstat, dct); /* Re-enable auto refresh after Dram init when in ganged mode - * to ensure both DCTs are in sync + * to ensure both DCTs are in sync (Erratum 278) */ - if (pDCTstat->GangedMode) { - do { - val = Get_NB32(pDCTstat->dev_dct, 0x90 + (0x100 * dct)); - } while (!(val & (1 << InitDram))); - - WaitRoutine_D(50); - - val = Get_NB32(pDCTstat->dev_dct, 0x8C + (0x100 * dct)); - val &= ~(1 << DisAutoRefresh); - val |= 1 << DisAutoRefresh; - val &= ~(1 << DisAutoRefresh); + if (pDCTstat->LogicalCPUID & (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_BA)) { + if (pDCTstat->GangedMode) { + do { + val = Get_NB32(pDCTstat->dev_dct, 0x90 + (0x100 * dct)); + } while (!(val & (1 << InitDram))); + + WaitRoutine_D(50); + + val = Get_NB32(pDCTstat->dev_dct, 0x8C + (0x100 * dct)); + val &= ~(1 << DisAutoRefresh); + val |= 1 << DisAutoRefresh; + val &= ~(1 << DisAutoRefresh); + } } } @@ -3792,7 +3796,10 @@ u8 wrap32dis = 0; u8 valid = 0; - /* FIXME: Skip reset DLL for B3 */ + /* Skip reset DLL for B3 */ + if (pDCTstat->LogicalCPUID & AMD_DR_B3) { + return; + } addr = HWCR; _RDMSR(addr, &lo, &hi); @@ -3885,8 +3892,7 @@ u32 reg_off = 0x100 * dct; u32 dev = pDCTstat->dev_dct; - /* FIXME: Add B3 */ - if (pDCTstat->LogicalCPUID & AMD_DR_B2) { + if (pDCTstat->LogicalCPUID & (AMD_DR_B2 | AMD_DR_B3)) { mct_Wait(10000); /* Wait 50 us*/ val = Get_NB32(dev, 0x110); if ( val & (1 << DramEnabled)) {

2 2

r3433 - in trunk/coreboot-v2/src/northbridge/amd/amdmct: . mct
by svn＠coreboot.org 23 Jul '08

23 Jul '08

Author: mjones Date: 2008-07-23 23:04:03 +0200 (Wed, 23 Jul 2008) New Revision: 3433 Modified: trunk/coreboot-v2/src/northbridge/amd/amdmct/amddefs.h trunk/coreboot-v2/src/northbridge/amd/amdmct/mct/mct_d.c Log: Memory initialization support for AMD Fam10 B3 (B0-B2 already supported). Signed-off-by: Marc Jones <marc.jones(a)amd.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/coreboot-v2/src/northbridge/amd/amdmct/amddefs.h =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdmct/amddefs.h 2008-07-21 22:23:57 UTC (rev 3432) +++ trunk/coreboot-v2/src/northbridge/amd/amdmct/amddefs.h 2008-07-23 21:04:03 UTC (rev 3433) @@ -53,6 +53,7 @@ #define AMD_GT_F0 (AMD_NPT_ALL AND NOT AMD_NPT_F0) #define AMD_DR_Ax (AMD_DR_A0A + AMD_DR_A1B + AMD_DR_A2) #define AMD_DR_Bx (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_B2 | AMD_DR_B3 | AMD_DR_BA) +#define AMD_DR_LT_B2 (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_BA) #define AMD_DR_LT_B3 (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_B2 | AMD_DR_BA) #define AMD_DR_GT_B0 (AMD_DR_ALL & ~(AMD_DR_B0)) #define AMD_DR_ALL (AMD_DR_Bx) Modified: trunk/coreboot-v2/src/northbridge/amd/amdmct/mct/mct_d.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdmct/mct/mct_d.c 2008-07-21 22:23:57 UTC (rev 3432) +++ trunk/coreboot-v2/src/northbridge/amd/amdmct/mct/mct_d.c 2008-07-23 21:04:03 UTC (rev 3433) @@ -2401,30 +2401,34 @@ mct_BeforeDramInit_Prod_D(pMCTstat, pDCTstat); // FIXME: for rev A: mct_BeforeDramInit_D(pDCTstat, dct); - /* Disable auto refresh before Dram init when in ganged mode */ - if (pDCTstat->GangedMode) { - val = Get_NB32(pDCTstat->dev_dct, 0x8C + (0x100 * dct)); - val |= 1 << DisAutoRefresh; - Set_NB32(pDCTstat->dev_dct, 0x8C + (0x100 * dct), val); + /* Disable auto refresh before Dram init when in ganged mode (Erratum 278) */ + if (pDCTstat->LogicalCPUID & AMD_DR_LT_B2) { + if (pDCTstat->GangedMode) { + val = Get_NB32(pDCTstat->dev_dct, 0x8C + (0x100 * dct)); + val |= 1 << DisAutoRefresh; + Set_NB32(pDCTstat->dev_dct, 0x8C + (0x100 * dct), val); + } } mct_DramInit_Hw_D(pMCTstat, pDCTstat, dct); /* Re-enable auto refresh after Dram init when in ganged mode - * to ensure both DCTs are in sync + * to ensure both DCTs are in sync (Erratum 278) */ - if (pDCTstat->GangedMode) { - do { - val = Get_NB32(pDCTstat->dev_dct, 0x90 + (0x100 * dct)); - } while (!(val & (1 << InitDram))); + if (pDCTstat->LogicalCPUID & AMD_DR_LT_B2) { + if (pDCTstat->GangedMode) { + do { + val = Get_NB32(pDCTstat->dev_dct, 0x90 + (0x100 * dct)); + } while (!(val & (1 << InitDram))); - WaitRoutine_D(50); + WaitRoutine_D(50); - val = Get_NB32(pDCTstat->dev_dct, 0x8C + (0x100 * dct)); - val &= ~(1 << DisAutoRefresh); - val |= 1 << DisAutoRefresh; - val &= ~(1 << DisAutoRefresh); + val = Get_NB32(pDCTstat->dev_dct, 0x8C + (0x100 * dct)); + val &= ~(1 << DisAutoRefresh); + val |= 1 << DisAutoRefresh; + val &= ~(1 << DisAutoRefresh); + } } } @@ -3792,7 +3796,10 @@ u8 wrap32dis = 0; u8 valid = 0; - /* FIXME: Skip reset DLL for B3 */ + /* Skip reset DLL for B3 */ + if (pDCTstat->LogicalCPUID & AMD_DR_B3) { + return; + } addr = HWCR; _RDMSR(addr, &lo, &hi); @@ -3885,8 +3892,7 @@ u32 reg_off = 0x100 * dct; u32 dev = pDCTstat->dev_dct; - /* FIXME: Add B3 */ - if (pDCTstat->LogicalCPUID & AMD_DR_B2) { + if (pDCTstat->LogicalCPUID & (AMD_DR_B2 | AMD_DR_B3)) { mct_Wait(10000); /* Wait 50 us*/ val = Get_NB32(dev, 0x110); if ( val & (1 << DramEnabled)) {

1 0

how to update firmware with tftp
by Amrish Purohit 22 Jul '08

22 Jul '08

hi all, i want help in following scenario. as computer boot up with coreboot. it must wait for approximately 5 seconds and listnen on tftp. if during that time if any firmware available than my system will download that firmware and update with corrent one and that system must boot with this new firmware. otherwise it will boot up with old firmware. i am using qemu. so is thre any idea for qemu with tftp Amrish purohit

2 1

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coreboot July 2008