coreboot July 2008

coreboot@coreboot.org

58 participants
214 discussions

r3432 - trunk/coreboot-v2/src/northbridge/amd/amdht
by svn＠coreboot.org 22 Jul '08

22 Jul '08

Author: mjones Date: 2008-07-22 00:23:57 +0200 (Tue, 22 Jul 2008) New Revision: 3432 Modified: trunk/coreboot-v2/src/northbridge/amd/amdht/ht_wrapper.c Log: Missed a const in my previous checkin, r3426 (trivial). Signed-off-by: Marc Jones <marc.jones(a)amd.com> Acked-by: Marc Jones <marc.jones(a)amd.com> Modified: trunk/coreboot-v2/src/northbridge/amd/amdht/ht_wrapper.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdht/ht_wrapper.c 2008-07-21 17:48:40 UTC (rev 3431) +++ trunk/coreboot-v2/src/northbridge/amd/amdht/ht_wrapper.c 2008-07-21 22:23:57 UTC (rev 3432) @@ -116,7 +116,7 @@ */ BOOL AMD_CB_ManualBUIDSwapList (u8 node, u16 link, u8 **List) { - u8 swaplist[] = { 0xFF, HT_CHAIN_UNITID_BASE, HT_CHAIN_END_UNITID_BASE, 0xFF }; + const u8 swaplist[] = { 0xFF, HT_CHAIN_UNITID_BASE, HT_CHAIN_END_UNITID_BASE, 0xFF }; /* If the BUID was adjusted in early_ht we need to do the manual override */ if ((HT_CHAIN_UNITID_BASE != 0) && (HT_CHAIN_END_UNITID_BASE != 0)) { printk_debug("AMD_CB_ManualBUIDSwapList()\n");

1 0

flashrom: Winbond W39V040C and MSI K8T Neo2-F
by Peter Stuge 21 Jul '08

21 Jul '08

Patch attached. //Peter

2 2

r3431 - trunk/util/flashrom
by svn＠coreboot.org 21 Jul '08

21 Jul '08

Author: stuge Date: 2008-07-21 19:48:40 +0200 (Mon, 21 Jul 2008) New Revision: 3431 Added: trunk/util/flashrom/w39v040c.c Modified: trunk/util/flashrom/Makefile trunk/util/flashrom/board_enable.c trunk/util/flashrom/flash.h trunk/util/flashrom/flashchips.c Log: flashrom: Winbond W39V040C and MSI K8T Neo2-F W39V040C does standard JEDEC commands except chip erase so add a small driver. probe_w39v040c() prints the block lock pin status when a chip is found. The Neo2 board enable matches on 8237-internal IDE and onboard NIC PCI IDs. Many thanks to Daniel McLellan for testing all of this on hardware! Build tested by Uwe. Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/util/flashrom/Makefile =================================================================== --- trunk/util/flashrom/Makefile 2008-07-21 14:49:04 UTC (rev 3430) +++ trunk/util/flashrom/Makefile 2008-07-21 17:48:40 UTC (rev 3431) @@ -29,7 +29,7 @@ w49f002u.o 82802ab.o pm49fl00x.o sst49lf040.o \ sst49lfxxxc.o sst_fwhub.o layout.o cbtable.o flashchips.o \ flashrom.o w39v080fa.o sharplhf00l04.o w29ee011.o spi.o it87spi.o \ - ichspi.o + ichspi.o w39v040c.o all: pciutils dep $(PROGRAM) Modified: trunk/util/flashrom/board_enable.c =================================================================== --- trunk/util/flashrom/board_enable.c 2008-07-21 14:49:04 UTC (rev 3430) +++ trunk/util/flashrom/board_enable.c 2008-07-21 17:48:40 UTC (rev 3431) @@ -114,6 +114,7 @@ * Winbond W83627THF: GPIO 4, bit 4 * * Suited for: + * - MSI K8T Neo2-F * - MSI K8N-NEO3 */ static int w83627thf_gpio4_4_raise(uint16_t index, const char *name) @@ -141,6 +142,11 @@ return 0; } +static int w83627thf_gpio4_4_raise_2e(const char *name) +{ + return w83627thf_gpio4_4_raise(0x2e, name); +} + static int w83627thf_gpio4_4_raise_4e(const char *name) { return w83627thf_gpio4_4_raise(0x4e, name); @@ -617,6 +623,8 @@ NULL, NULL, "BioStar P4M80-M4", board_biostar_p4m80_m4}, {0x1106, 0x3227, 0x1458, 0x5001, 0x10ec, 0x8139, 0x1458, 0xe000, NULL, NULL, "GIGABYTE GA-7VT600", board_biostar_p4m80_m4}, + {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, + NULL, NULL, "MSI K8T Neo2", w83627thf_gpio4_4_raise_2e}, {0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL} /* Keep this */ }; Modified: trunk/util/flashrom/flash.h =================================================================== --- trunk/util/flashrom/flash.h 2008-07-21 14:49:04 UTC (rev 3430) +++ trunk/util/flashrom/flash.h 2008-07-21 17:48:40 UTC (rev 3431) @@ -517,6 +517,11 @@ int erase_sst_fwhub(struct flashchip *flash); int write_sst_fwhub(struct flashchip *flash, uint8_t *buf); +/* w39v040c.c */ +int probe_w39v040c(struct flashchip *flash); +int erase_w39v040c(struct flashchip *flash); +int write_w39v040c(struct flashchip *flash, uint8_t *buf); + /* w39V080fa.c */ int probe_winbond_fwhub(struct flashchip *flash); int erase_winbond_fwhub(struct flashchip *flash); Modified: trunk/util/flashrom/flashchips.c =================================================================== --- trunk/util/flashrom/flashchips.c 2008-07-21 14:49:04 UTC (rev 3430) +++ trunk/util/flashrom/flashchips.c 2008-07-21 17:48:40 UTC (rev 3431) @@ -132,6 +132,7 @@ {"Winbond", "W29EE011", WINBOND_ID, W_29C011, 128, 128, TEST_OK_PREW, probe_w29ee011, erase_chip_jedec, write_jedec}, {"Winbond", "W39V040A", WINBOND_ID, W_39V040A, 512, 64*1024, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_39sf020}, {"Winbond", "W39V040B", WINBOND_ID, W_39V040B, 512, 64*1024, TEST_OK_PREW, probe_jedec, erase_chip_jedec, write_39sf020}, + {"Winbond", "W39V040C", 0xda, 0x50, 512, 64*1024, TEST_OK_PREW, probe_w39v040c, erase_w39v040c, write_w39v040c}, {"Winbond", "W39V040FA", WINBOND_ID, W_39V040FA, 512, 64*1024, TEST_OK_PR, probe_jedec, erase_chip_jedec, write_39sf020}, {"Winbond", "W39V080A", WINBOND_ID, W_39V080A, 1024, 64*1024, TEST_OK_PREW, probe_jedec, erase_chip_jedec, write_39sf020}, {"Winbond", "W49F002U", WINBOND_ID, W_49F002U, 256, 128, TEST_OK_PREW, probe_jedec, erase_chip_jedec, write_49f002}, Added: trunk/util/flashrom/w39v040c.c =================================================================== --- trunk/util/flashrom/w39v040c.c (rev 0) +++ trunk/util/flashrom/w39v040c.c 2008-07-21 17:48:40 UTC (rev 3431) @@ -0,0 +1,98 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2008 Peter Stuge <peter(a)stuge.se> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdio.h> +#include "flash.h" + +int probe_w39v040c(struct flashchip *flash) +{ + volatile uint8_t *bios = flash->virtual_memory; + uint8_t id1, id2, lock; + + *(volatile uint8_t *)(bios + 0x5555) = 0xAA; + myusec_delay(10); + *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; + myusec_delay(10); + *(volatile uint8_t *)(bios + 0x5555) = 0x90; + myusec_delay(10); + + id1 = *(volatile uint8_t *)bios; + id2 = *(volatile uint8_t *)(bios + 1); + lock = *(volatile uint8_t *)(bios + 0xfff2); + + *(volatile uint8_t *)(bios + 0x5555) = 0xAA; + myusec_delay(10); + *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; + myusec_delay(10); + *(volatile uint8_t *)(bios + 0x5555) = 0xF0; + myusec_delay(40); + + printf_debug("%s: id1 0x%x, id2 0x%x", __func__, id1, id2); + if (!oddparity(id1)) + printf_debug(", id1 parity violation"); + printf_debug("\n"); + if (flash->manufacture_id == id1 && flash->model_id == id2) { + printf("%s: Boot block #TBL is %slocked, rest of chip #WP is %slocked.\n", + __func__, lock & 0x4 ? "" : "un", lock & 0x8 ? "" : "un"); + return 1; + } + + return 0; +} + +int erase_w39v040c(struct flashchip *flash) +{ + int i; + unsigned int total_size = flash->total_size * 1024; + volatile uint8_t *bios = flash->virtual_memory; + + for (i = 0; i < total_size; i += flash->page_size) + erase_sector_jedec(flash->virtual_memory, i); + + for (i = 0; i < total_size; i++) + if (0xff != bios[i]) { + printf("ERASE FAILED at 0x%08x! Expected=0xff, Read=0x%02x\n", i, bios[i]); + return -1; + } + + return 0; +} + +int write_w39v040c(struct flashchip *flash, uint8_t *buf) +{ + int i; + int total_size = flash->total_size * 1024; + int page_size = flash->page_size; + volatile uint8_t *bios = flash->virtual_memory; + + if (flash->erase(flash)) + return -1; + + printf("Programming page: "); + for (i = 0; i < total_size / page_size; i++) { + printf("%04d at address: 0x%08x", i, i * page_size); + write_sector_jedec(bios, buf + i * page_size, + bios + i * page_size, page_size); + printf("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b"); + } + printf("\n"); + + return 0; +}

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Re: [coreboot] HT credits and the Opteron
by Steve Casselman 21 Jul '08

21 Jul '08

Credits represent the number of buffers available. There are 7 types of buffers in the Opteron used for the HT subsystem. Each HT link's transmitter sends the receiver on the other side the number of credits (buffers) that are available. If the chip is something like a south bridge then it has a fixed number of credits (buffers) and it sends them to the Opteron. The Opteron has a pool of buffers that can be shared among the three HT links it has. Their use is mostly in high speed data transfer where you want more data buffers on one port than on another. As to the CK804 I'm thinking that Dr Lu double checked those settings in the Nvidia data sheet. The total number of buffers allocated in your BIOS should be checked against the information below. Steve PS You can see these buffer numbers you have to be root.. lspci -s 0:18.0 -xxx pcitweak -r 0:18:0 0x90 (reads LDT0 buffer counts) From the BIOS and Kernel guide... 4.3.15 LDTi Buffer Count Registers LDT0, LDT1, LDT2 Buffer Count Registers Function 0: Offset 90h, B0h, D0h Request Buffer Count (Req)—Bits 3–0. Posted Request Buffer Count (PReq)—Bits 7–4. Response Buffer Count (Rsp)—Bits 11–8. Probe Buffer Count (Probe)—Bits 15–12. Request Data Buffer Count (ReqD)—Bits 18–16. Posted Request Data Buffer Count (PReqD)—Bits 22–20. Response Data Buffer Count (RspD)—Bits 26–24. 4.6.10 XBAR Flow Control Buffers Table 28. XBAR Input Buffers Link Number of Number of Command Buffers Data Buffers HT Link 0-2 16 x 3 8 x 3 SRI 10 5 MCT 12 8 Total 70 37 XBAR command and data buffers are independent. There are 70 command buffers available, but a maximum of 64 can be used at any given time. Number of used data buffers is not restricted. The default allocation of command buffers when all HyperTransport links are present is shown in Table 29. Default Command XBAR Buffers Link Number of Command Buffers HT Link 0-2 15 x 3 SRI 8 MCT 11 Total 64

2 1

branching flashrom?
by Carl-Daniel Hailfinger 21 Jul '08

21 Jul '08

Hi, you all are probably aware now that flashrom 1.0 is pending release and the philosophy for further development (total rewrite vs. incremental changes) is heavily disagreed upon. Completely forking the codebase into separate projects is something I'd like to avoid because we already have too few development resources. Suggestion: After 1.0, we create - a development branch where people can go wild with rewriting stuff - a stable branch with incremental changes where breakage is not allowed. Each branch would have its own maintainer, possibly with final authority over what goes in. I suggest Peter as maintainer for the radical development branch because he has expressed the need for a flashrom rewrite in the past. I personally believe more in the incremental approach with minimal changes. Regards, Carl-Daniel -- http://www.hailfinger.org/

5 6

Re: [coreboot] Super IO: Winbond W83697HF Support
by Uwe Hermann 21 Jul '08

21 Jul '08

[Please always reply to the mailing list, not individual developers] On Fri, Jul 18, 2008 at 09:38:18AM -0700, Sean Nelson wrote: > I'm Sorry about the last patch, it was bad. > Final patch attached. > > Added support for Winbond W83697HF SuperIO. > > Signed-off-by: Sean Nelson <snelson(a)nmt.edu> Thanks, committed in r3430 with some minor changes. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

1 0

r3430 - in trunk/coreboot-v2/src/superio/winbond: . w83697hf
by svn＠coreboot.org 21 Jul '08

21 Jul '08

Author: uwe Date: 2008-07-21 16:49:04 +0200 (Mon, 21 Jul 2008) New Revision: 3430 Added: trunk/coreboot-v2/src/superio/winbond/w83697hf/ trunk/coreboot-v2/src/superio/winbond/w83697hf/Config.lb trunk/coreboot-v2/src/superio/winbond/w83697hf/chip.h trunk/coreboot-v2/src/superio/winbond/w83697hf/superio.c trunk/coreboot-v2/src/superio/winbond/w83697hf/w83697hf.h trunk/coreboot-v2/src/superio/winbond/w83697hf/w83697hf_early_serial.c Log: Add support for the Winbond W83697HF Super I/O. Signed-off-by: Sean Nelson <snelson(a)nmt.edu> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Added: trunk/coreboot-v2/src/superio/winbond/w83697hf/Config.lb =================================================================== --- trunk/coreboot-v2/src/superio/winbond/w83697hf/Config.lb (rev 0) +++ trunk/coreboot-v2/src/superio/winbond/w83697hf/Config.lb 2008-07-21 14:49:04 UTC (rev 3430) @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 Sean Nelson <snelson(a)nmt.edu> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config chip.h +object superio.o Added: trunk/coreboot-v2/src/superio/winbond/w83697hf/chip.h =================================================================== --- trunk/coreboot-v2/src/superio/winbond/w83697hf/chip.h (rev 0) +++ trunk/coreboot-v2/src/superio/winbond/w83697hf/chip.h 2008-07-21 14:49:04 UTC (rev 3430) @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Sean Nelson <snelson(a)nmt.edu> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <uart8250.h> + +extern struct chip_operations superio_winbond_w83697hf_ops; + +struct superio_winbond_w83697hf_config { + struct uart8250 com1, com2; +}; Added: trunk/coreboot-v2/src/superio/winbond/w83697hf/superio.c =================================================================== --- trunk/coreboot-v2/src/superio/winbond/w83697hf/superio.c (rev 0) +++ trunk/coreboot-v2/src/superio/winbond/w83697hf/superio.c 2008-07-21 14:49:04 UTC (rev 3430) @@ -0,0 +1,118 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Sean Nelson <snelson(a)nmt.edu> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include <console/console.h> +#include <string.h> +#include <bitops.h> +#include <uart8250.h> +#include <pc80/mc146818rtc.h> +#include <stdlib.h> +#include "chip.h" +#include "w83697hf.h" + +static void pnp_enter_ext_func_mode(device_t dev) +{ + outb(0x87, dev->path.u.pnp.port); + outb(0x87, dev->path.u.pnp.port); +} + +static void pnp_exit_ext_func_mode(device_t dev) +{ + outb(0xaa, dev->path.u.pnp.port); +} + +static void w83697hf_init(device_t dev) +{ + struct superio_winbond_w83697hf_config *conf; + struct resource *res0, *res1; + + if (!dev->enabled) + return; + + conf = dev->chip_info; + switch(dev->path.u.pnp.device) { + case W83697HF_SP1: + res0 = find_resource(dev, PNP_IDX_IO0); + init_uart8250(res0->base, &conf->com1); + break; + case W83697HF_SP2: + res0 = find_resource(dev, PNP_IDX_IO0); + init_uart8250(res0->base, &conf->com2); + break; + } +} + +static void w83697hf_pnp_set_resources(device_t dev) +{ + pnp_enter_ext_func_mode(dev); + pnp_set_resources(dev); + pnp_exit_ext_func_mode(dev); +} + +static void w83697hf_pnp_enable(device_t dev) +{ + if (!dev->enabled) { + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_exit_ext_func_mode(dev); + } +} + +static void w83697hf_pnp_enable_resources(device_t dev) +{ + pnp_enter_ext_func_mode(dev); + pnp_enable_resources(dev); + pnp_exit_ext_func_mode(dev); +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = w83697hf_pnp_set_resources, + .enable_resources = w83697hf_pnp_enable_resources, + .enable = w83697hf_pnp_enable, + .init = w83697hf_init, +}; + +static struct pnp_info pnp_dev_info[] = { + { &ops, W83697HF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, + { &ops, W83697HF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, + { &ops, W83697HF_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, W83697HF_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, W83697HF_CIR, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, W83697HF_GAME_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 0x4}, }, + { &ops, W83697HF_MIDI_GPIO5, }, + { &ops, W83697HF_GPIO234, }, + { &ops, W83697HF_ACPI, }, + { &ops, W83697HF_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_winbond_w83697hf_ops = { + CHIP_NAME("Winbond W83697HF Super I/O") + .enable_dev = enable_dev, +}; Added: trunk/coreboot-v2/src/superio/winbond/w83697hf/w83697hf.h =================================================================== --- trunk/coreboot-v2/src/superio/winbond/w83697hf/w83697hf.h (rev 0) +++ trunk/coreboot-v2/src/superio/winbond/w83697hf/w83697hf.h 2008-07-21 14:49:04 UTC (rev 3430) @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Sean Nelson <snelson(a)nmt.edu> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define W83697HF_FDC 0 /* Floppy */ +#define W83697HF_PP 1 /* Parallel Port */ +#define W83697HF_SP1 2 /* Com1 */ +#define W83697HF_SP2 3 /* Com2 */ +#define W83697HF_CIR 6 /* Consumer IR */ +#define W83697HF_GAME_GPIO1 7 /* Game port, GPIO 1 */ +#define W83697HF_MIDI_GPIO5 8 /* MIDI, GPIO 5 */ +#define W83697HF_GPIO234 9 /* GPIO 2, 3, 4 */ +#define W83697HF_ACPI 10 /* ACPI */ +#define W83697HF_HWM 11 /* Hardware Monitor */ Added: trunk/coreboot-v2/src/superio/winbond/w83697hf/w83697hf_early_serial.c =================================================================== --- trunk/coreboot-v2/src/superio/winbond/w83697hf/w83697hf_early_serial.c (rev 0) +++ trunk/coreboot-v2/src/superio/winbond/w83697hf/w83697hf_early_serial.c 2008-07-21 14:49:04 UTC (rev 3430) @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Sean Nelson <snelson(a)nmt.edu> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <arch/romcc_io.h> +#include "w83697hf.h" + +static inline void pnp_enter_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + outb(0x87, port); + outb(0x87, port); +} + +static void pnp_exit_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + outb(0xaa, port); +} + +static void w83697hf_enable_serial(device_t dev, u16 iobase) +{ + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_ext_func_mode(dev); +}

1 0

Proper use and intended function of "device pci xx.x on/off" in Config.lb in V2
by bari 21 Jul '08

21 Jul '08

Anyone know how or where in the source "device pci xx.x on/off" is used in /mainboard/../../Config.lb ? In cleaning up the Epia-CN I'm noticing that there are conflicts in enables and disables of PCI devices between what is in its Config.lb and what is in auto.c, mainboard.c etc. I'm trying to clean this up, but almost every board I compare Config.lb files to it's done differently. I know that many of the boards actually do work, but it is not understood how or why it does, only that it does. What board does this correctly and is the example that should be followed? -Bari

2 1

[PATCH] v3: rename mainboard_part_number to mainboard_name
by Carl-Daniel Hailfinger 20 Jul '08

20 Jul '08

Rename mainboard_part_number to mainboard_name in various places. This is the logical continuation of r416 which happened a year ago and was > Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> > Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> As an added bonus, we now have consistent naming again, making grepping the source for dts properties possible. Build tested on all targets. Patch attached for Gmail users. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: corebootv3-mainboard_name/mainboard/adl/msm800sev/dts =================================================================== --- corebootv3-mainboard_name/mainboard/adl/msm800sev/dts (Revision 696) +++ corebootv3-mainboard_name/mainboard/adl/msm800sev/dts (Arbeitskopie) @@ -22,7 +22,7 @@ /{ mainboard_vendor = "Advanced Digital Logic"; - mainboard-name = "MSM800SEV"; + mainboard_name = "MSM800SEV"; mainboard_pci_subsystem_vendor = "0x1022"; mainboard_pci_subsystem_device = "0x2323"; cpus { }; Index: corebootv3-mainboard_name/mainboard/amd/norwich/dts =================================================================== --- corebootv3-mainboard_name/mainboard/amd/norwich/dts (Revision 696) +++ corebootv3-mainboard_name/mainboard/amd/norwich/dts (Arbeitskopie) @@ -20,7 +20,7 @@ /{ mainboard_vendor = "AMD"; - mainboard-name = "NORWICH"; + mainboard_name = "NORWICH"; mainboard_pci_subsystem_vendor = "0x1022"; mainboard_pci_subsystem_device = "0x2323"; cpus { }; Index: corebootv3-mainboard_name/mainboard/amd/db800/dts =================================================================== --- corebootv3-mainboard_name/mainboard/amd/db800/dts (Revision 696) +++ corebootv3-mainboard_name/mainboard/amd/db800/dts (Arbeitskopie) @@ -20,7 +20,7 @@ /{ mainboard_vendor = "AMD"; - mainboard-name = "DB800"; + mainboard_name = "DB800"; mainboard_pci_subsystem_vendor = "0x1022"; mainboard_pci_subsystem_device = "0x2323"; cpus { }; Index: corebootv3-mainboard_name/mainboard/artecgroup/dbe61/dts =================================================================== --- corebootv3-mainboard_name/mainboard/artecgroup/dbe61/dts (Revision 696) +++ corebootv3-mainboard_name/mainboard/artecgroup/dbe61/dts (Arbeitskopie) @@ -74,7 +74,7 @@ /{ mainboard_vendor = "Artec Group"; - mainboard-name = "DBE61"; + mainboard_name = "DBE61"; mainboard_pci_subsystem_vendor = "0x1022"; mainboard_pci_subsystem_device = "0x2323"; cpus { }; Index: corebootv3-mainboard_name/mainboard/artecgroup/dbe62/dts =================================================================== --- corebootv3-mainboard_name/mainboard/artecgroup/dbe62/dts (Revision 696) +++ corebootv3-mainboard_name/mainboard/artecgroup/dbe62/dts (Arbeitskopie) @@ -20,7 +20,7 @@ /{ mainboard_vendor = "Artec"; - mainboard-name = "DBE62"; + mainboard_name = "DBE62"; cpus { }; apic@0 { /config/("northbridge/amd/geodelx/apic"); Index: corebootv3-mainboard_name/mainboard/pcengines/alix1c/dts =================================================================== --- corebootv3-mainboard_name/mainboard/pcengines/alix1c/dts (Revision 696) +++ corebootv3-mainboard_name/mainboard/pcengines/alix1c/dts (Arbeitskopie) @@ -20,7 +20,7 @@ /{ mainboard_vendor = "PC Engines"; - mainboard-name = "ALIX1.C"; + mainboard_name = "ALIX1.C"; cpus { }; apic@0 { /config/("northbridge/amd/geodelx/apic"); Index: corebootv3-mainboard_name/mainboard/pcengines/alix2c3/dts =================================================================== --- corebootv3-mainboard_name/mainboard/pcengines/alix2c3/dts (Revision 696) +++ corebootv3-mainboard_name/mainboard/pcengines/alix2c3/dts (Arbeitskopie) @@ -20,7 +20,7 @@ /{ mainboard_vendor = "PC Engines"; - mainboard-name = "ALIX.2C3"; + mainboard_name = "ALIX.2C3"; cpus { }; apic@0 { /config/("northbridge/amd/geodelx/apic"); Index: corebootv3-mainboard_name/mainboard/emulation/qemu-x86/dts =================================================================== --- corebootv3-mainboard_name/mainboard/emulation/qemu-x86/dts (Revision 696) +++ corebootv3-mainboard_name/mainboard/emulation/qemu-x86/dts (Arbeitskopie) @@ -20,7 +20,7 @@ /{ mainboard_vendor = "Emulation"; - mainboard-name = "QEMU x86"; + mainboard_name = "QEMU x86"; mainboard_pci_subsystem_vendor = "0x15ad"; mainboard_pci_subsystem_device = "0x1976"; device_operations = "qemuvga_pci_ops_dev"; Index: corebootv3-mainboard_name/util/dtc/flattree.c =================================================================== --- corebootv3-mainboard_name/util/dtc/flattree.c (Revision 696) +++ corebootv3-mainboard_name/util/dtc/flattree.c (Arbeitskopie) @@ -1328,7 +1328,7 @@ extern char *code; struct node *next; extern struct node *first_node; - int found_mainboard_vendor = 0, found_mainboard_partnumber = 0, found_mainboard_subsys = 0; + int found_mainboard_vendor = 0, found_mainboard_name = 0, found_mainboard_subsys = 0; labeltree(bi->dt); @@ -1357,9 +1357,9 @@ found_mainboard_vendor = 1; fprintf(f, "const char *mainboard_vendor = \"%s\";\n", prop->val.val); } - if (streq(prop->name, "mainboard-name")){ - found_mainboard_partnumber = 1; - fprintf(f, "const char *mainboard_part_number = \"%s\";\n", prop->val.val); + if (streq(prop->name, "mainboard_name")){ + found_mainboard_name = 1; + fprintf(f, "const char *mainboard_name = \"%s\";\n", prop->val.val); } if (streq(prop->name, "mainboard_pci_subsystem_vendor")){ found_mainboard_subsys++; @@ -1373,11 +1373,11 @@ if (! found_mainboard_vendor){ die("There is no mainboard_vendor property in the root. Please add one." - "(and make sure there is a mainboard-name property too"); + "(and make sure there is a mainboard_name property too"); } - if (! found_mainboard_partnumber){ - die("There is no mainboard-name property in the root. " + if (! found_mainboard_name){ + die("There is no mainboard_name property in the root. " "Please add one." "(and make sure there is a mainboard_vendor property too"); } @@ -1436,7 +1436,7 @@ fix_next(bi->dt); /* emit any includes that we need -- TODO: ONLY ONCE PER TYPE*/ fprintf(f, "#include <device/device.h>\n#include <device/pci.h>\n"); - fprintf(f, "extern const char *mainboard_vendor, *mainboard_part_number;\n"); + fprintf(f, "extern const char *mainboard_vendor, *mainboard_name;\n"); for_each_property(bi->dt, prop) { if (streq(prop->name, "mainboard_pci_subsystem_vendor")){ Index: corebootv3-mainboard_name/arch/x86/coreboot_table.c =================================================================== --- corebootv3-mainboard_name/arch/x86/coreboot_table.c (Revision 696) +++ corebootv3-mainboard_name/arch/x86/coreboot_table.c (Arbeitskopie) @@ -142,14 +142,14 @@ { struct lb_record *rec; struct lb_mainboard *mainboard; - extern char *mainboard_vendor, *mainboard_part_number; + extern char *mainboard_vendor, *mainboard_name; rec = lb_new_record(header); mainboard = (struct lb_mainboard *)rec; mainboard->tag = LB_TAG_MAINBOARD; mainboard->size = (sizeof(*mainboard) + strlen(mainboard_vendor) + 1 + - strlen(mainboard_part_number) + 1 + + strlen(mainboard_name) + 1 + 3) & ~3; mainboard->vendor_idx = 0; @@ -158,7 +158,7 @@ memcpy(mainboard->strings + mainboard->vendor_idx, mainboard_vendor, strlen(mainboard_vendor) + 1); memcpy(mainboard->strings + mainboard->part_number_idx, - mainboard_part_number, strlen(mainboard_part_number) + 1); + mainboard_name, strlen(mainboard_name) + 1); return mainboard; } -- http://www.hailfinger.org/ Index: corebootv3-mainboard_name/mainboard/adl/msm800sev/dts =================================================================== --- corebootv3-mainboard_name/mainboard/adl/msm800sev/dts (Revision 696) +++ corebootv3-mainboard_name/mainboard/adl/msm800sev/dts (Arbeitskopie) @@ -22,7 +22,7 @@ /{ mainboard_vendor = "Advanced Digital Logic"; - mainboard-name = "MSM800SEV"; + mainboard_name = "MSM800SEV"; mainboard_pci_subsystem_vendor = "0x1022"; mainboard_pci_subsystem_device = "0x2323"; cpus { }; Index: corebootv3-mainboard_name/mainboard/amd/norwich/dts =================================================================== --- corebootv3-mainboard_name/mainboard/amd/norwich/dts (Revision 696) +++ corebootv3-mainboard_name/mainboard/amd/norwich/dts (Arbeitskopie) @@ -20,7 +20,7 @@ /{ mainboard_vendor = "AMD"; - mainboard-name = "NORWICH"; + mainboard_name = "NORWICH"; mainboard_pci_subsystem_vendor = "0x1022"; mainboard_pci_subsystem_device = "0x2323"; cpus { }; Index: corebootv3-mainboard_name/mainboard/amd/db800/dts =================================================================== --- corebootv3-mainboard_name/mainboard/amd/db800/dts (Revision 696) +++ corebootv3-mainboard_name/mainboard/amd/db800/dts (Arbeitskopie) @@ -20,7 +20,7 @@ /{ mainboard_vendor = "AMD"; - mainboard-name = "DB800"; + mainboard_name = "DB800"; mainboard_pci_subsystem_vendor = "0x1022"; mainboard_pci_subsystem_device = "0x2323"; cpus { }; Index: corebootv3-mainboard_name/mainboard/artecgroup/dbe61/dts =================================================================== --- corebootv3-mainboard_name/mainboard/artecgroup/dbe61/dts (Revision 696) +++ corebootv3-mainboard_name/mainboard/artecgroup/dbe61/dts (Arbeitskopie) @@ -74,7 +74,7 @@ /{ mainboard_vendor = "Artec Group"; - mainboard-name = "DBE61"; + mainboard_name = "DBE61"; mainboard_pci_subsystem_vendor = "0x1022"; mainboard_pci_subsystem_device = "0x2323"; cpus { }; Index: corebootv3-mainboard_name/mainboard/artecgroup/dbe62/dts =================================================================== --- corebootv3-mainboard_name/mainboard/artecgroup/dbe62/dts (Revision 696) +++ corebootv3-mainboard_name/mainboard/artecgroup/dbe62/dts (Arbeitskopie) @@ -20,7 +20,7 @@ /{ mainboard_vendor = "Artec"; - mainboard-name = "DBE62"; + mainboard_name = "DBE62"; cpus { }; apic@0 { /config/("northbridge/amd/geodelx/apic"); Index: corebootv3-mainboard_name/mainboard/pcengines/alix1c/dts =================================================================== --- corebootv3-mainboard_name/mainboard/pcengines/alix1c/dts (Revision 696) +++ corebootv3-mainboard_name/mainboard/pcengines/alix1c/dts (Arbeitskopie) @@ -20,7 +20,7 @@ /{ mainboard_vendor = "PC Engines"; - mainboard-name = "ALIX1.C"; + mainboard_name = "ALIX1.C"; cpus { }; apic@0 { /config/("northbridge/amd/geodelx/apic"); Index: corebootv3-mainboard_name/mainboard/pcengines/alix2c3/dts =================================================================== --- corebootv3-mainboard_name/mainboard/pcengines/alix2c3/dts (Revision 696) +++ corebootv3-mainboard_name/mainboard/pcengines/alix2c3/dts (Arbeitskopie) @@ -20,7 +20,7 @@ /{ mainboard_vendor = "PC Engines"; - mainboard-name = "ALIX.2C3"; + mainboard_name = "ALIX.2C3"; cpus { }; apic@0 { /config/("northbridge/amd/geodelx/apic"); Index: corebootv3-mainboard_name/mainboard/emulation/qemu-x86/dts =================================================================== --- corebootv3-mainboard_name/mainboard/emulation/qemu-x86/dts (Revision 696) +++ corebootv3-mainboard_name/mainboard/emulation/qemu-x86/dts (Arbeitskopie) @@ -20,7 +20,7 @@ /{ mainboard_vendor = "Emulation"; - mainboard-name = "QEMU x86"; + mainboard_name = "QEMU x86"; mainboard_pci_subsystem_vendor = "0x15ad"; mainboard_pci_subsystem_device = "0x1976"; device_operations = "qemuvga_pci_ops_dev"; Index: corebootv3-mainboard_name/util/dtc/flattree.c =================================================================== --- corebootv3-mainboard_name/util/dtc/flattree.c (Revision 696) +++ corebootv3-mainboard_name/util/dtc/flattree.c (Arbeitskopie) @@ -1328,7 +1328,7 @@ extern char *code; struct node *next; extern struct node *first_node; - int found_mainboard_vendor = 0, found_mainboard_partnumber = 0, found_mainboard_subsys = 0; + int found_mainboard_vendor = 0, found_mainboard_name = 0, found_mainboard_subsys = 0; labeltree(bi->dt); @@ -1357,9 +1357,9 @@ found_mainboard_vendor = 1; fprintf(f, "const char *mainboard_vendor = \"%s\";\n", prop->val.val); } - if (streq(prop->name, "mainboard-name")){ - found_mainboard_partnumber = 1; - fprintf(f, "const char *mainboard_part_number = \"%s\";\n", prop->val.val); + if (streq(prop->name, "mainboard_name")){ + found_mainboard_name = 1; + fprintf(f, "const char *mainboard_name = \"%s\";\n", prop->val.val); } if (streq(prop->name, "mainboard_pci_subsystem_vendor")){ found_mainboard_subsys++; @@ -1373,11 +1373,11 @@ if (! found_mainboard_vendor){ die("There is no mainboard_vendor property in the root. Please add one." - "(and make sure there is a mainboard-name property too"); + "(and make sure there is a mainboard_name property too"); } - if (! found_mainboard_partnumber){ - die("There is no mainboard-name property in the root. " + if (! found_mainboard_name){ + die("There is no mainboard_name property in the root. " "Please add one." "(and make sure there is a mainboard_vendor property too"); } @@ -1436,7 +1436,7 @@ fix_next(bi->dt); /* emit any includes that we need -- TODO: ONLY ONCE PER TYPE*/ fprintf(f, "#include <device/device.h>\n#include <device/pci.h>\n"); - fprintf(f, "extern const char *mainboard_vendor, *mainboard_part_number;\n"); + fprintf(f, "extern const char *mainboard_vendor, *mainboard_name;\n"); for_each_property(bi->dt, prop) { if (streq(prop->name, "mainboard_pci_subsystem_vendor")){ Index: corebootv3-mainboard_name/arch/x86/coreboot_table.c =================================================================== --- corebootv3-mainboard_name/arch/x86/coreboot_table.c (Revision 696) +++ corebootv3-mainboard_name/arch/x86/coreboot_table.c (Arbeitskopie) @@ -142,14 +142,14 @@ { struct lb_record *rec; struct lb_mainboard *mainboard; - extern char *mainboard_vendor, *mainboard_part_number; + extern char *mainboard_vendor, *mainboard_name; rec = lb_new_record(header); mainboard = (struct lb_mainboard *)rec; mainboard->tag = LB_TAG_MAINBOARD; mainboard->size = (sizeof(*mainboard) + strlen(mainboard_vendor) + 1 + - strlen(mainboard_part_number) + 1 + + strlen(mainboard_name) + 1 + 3) & ~3; mainboard->vendor_idx = 0; @@ -158,7 +158,7 @@ memcpy(mainboard->strings + mainboard->vendor_idx, mainboard_vendor, strlen(mainboard_vendor) + 1); memcpy(mainboard->strings + mainboard->part_number_idx, - mainboard_part_number, strlen(mainboard_part_number) + 1); + mainboard_name, strlen(mainboard_name) + 1); return mainboard; }

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r697 - in coreboot-v3: arch/x86 mainboard/adl/msm800sev mainboard/amd/db800 mainboard/amd/norwich mainboard/artecgroup/dbe61 mainboard/artecgroup/dbe62 mainboard/emulation/qemu-x86 mainboard/pcengines/alix1c mainboard/pcengines/alix2c3 util/dtc
by svn＠coreboot.org 20 Jul '08

20 Jul '08

Author: hailfinger Date: 2008-07-20 23:05:25 +0200 (Sun, 20 Jul 2008) New Revision: 697 Modified: coreboot-v3/arch/x86/coreboot_table.c coreboot-v3/mainboard/adl/msm800sev/dts coreboot-v3/mainboard/amd/db800/dts coreboot-v3/mainboard/amd/norwich/dts coreboot-v3/mainboard/artecgroup/dbe61/dts coreboot-v3/mainboard/artecgroup/dbe62/dts coreboot-v3/mainboard/emulation/qemu-x86/dts coreboot-v3/mainboard/pcengines/alix1c/dts coreboot-v3/mainboard/pcengines/alix2c3/dts coreboot-v3/util/dtc/flattree.c Log: Rename mainboard_part_number to mainboard_name in various places. This is the logical continuation of r416 which happened a year ago. As an added bonus, we now have consistent naming again, making grepping the source for dts properties possible. Build tested on all targets. Patch attached for Gmail users. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/arch/x86/coreboot_table.c =================================================================== --- coreboot-v3/arch/x86/coreboot_table.c 2008-07-14 23:04:48 UTC (rev 696) +++ coreboot-v3/arch/x86/coreboot_table.c 2008-07-20 21:05:25 UTC (rev 697) @@ -142,14 +142,14 @@ { struct lb_record *rec; struct lb_mainboard *mainboard; - extern char *mainboard_vendor, *mainboard_part_number; + extern char *mainboard_vendor, *mainboard_name; rec = lb_new_record(header); mainboard = (struct lb_mainboard *)rec; mainboard->tag = LB_TAG_MAINBOARD; mainboard->size = (sizeof(*mainboard) + strlen(mainboard_vendor) + 1 + - strlen(mainboard_part_number) + 1 + + strlen(mainboard_name) + 1 + 3) & ~3; mainboard->vendor_idx = 0; @@ -158,7 +158,7 @@ memcpy(mainboard->strings + mainboard->vendor_idx, mainboard_vendor, strlen(mainboard_vendor) + 1); memcpy(mainboard->strings + mainboard->part_number_idx, - mainboard_part_number, strlen(mainboard_part_number) + 1); + mainboard_name, strlen(mainboard_name) + 1); return mainboard; } Modified: coreboot-v3/mainboard/adl/msm800sev/dts =================================================================== --- coreboot-v3/mainboard/adl/msm800sev/dts 2008-07-14 23:04:48 UTC (rev 696) +++ coreboot-v3/mainboard/adl/msm800sev/dts 2008-07-20 21:05:25 UTC (rev 697) @@ -22,7 +22,7 @@ /{ mainboard_vendor = "Advanced Digital Logic"; - mainboard-name = "MSM800SEV"; + mainboard_name = "MSM800SEV"; mainboard_pci_subsystem_vendor = "0x1022"; mainboard_pci_subsystem_device = "0x2323"; cpus { }; Modified: coreboot-v3/mainboard/amd/db800/dts =================================================================== --- coreboot-v3/mainboard/amd/db800/dts 2008-07-14 23:04:48 UTC (rev 696) +++ coreboot-v3/mainboard/amd/db800/dts 2008-07-20 21:05:25 UTC (rev 697) @@ -20,7 +20,7 @@ /{ mainboard_vendor = "AMD"; - mainboard-name = "DB800"; + mainboard_name = "DB800"; mainboard_pci_subsystem_vendor = "0x1022"; mainboard_pci_subsystem_device = "0x2323"; cpus { }; Modified: coreboot-v3/mainboard/amd/norwich/dts =================================================================== --- coreboot-v3/mainboard/amd/norwich/dts 2008-07-14 23:04:48 UTC (rev 696) +++ coreboot-v3/mainboard/amd/norwich/dts 2008-07-20 21:05:25 UTC (rev 697) @@ -20,7 +20,7 @@ /{ mainboard_vendor = "AMD"; - mainboard-name = "NORWICH"; + mainboard_name = "NORWICH"; mainboard_pci_subsystem_vendor = "0x1022"; mainboard_pci_subsystem_device = "0x2323"; cpus { }; Modified: coreboot-v3/mainboard/artecgroup/dbe61/dts =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe61/dts 2008-07-14 23:04:48 UTC (rev 696) +++ coreboot-v3/mainboard/artecgroup/dbe61/dts 2008-07-20 21:05:25 UTC (rev 697) @@ -74,7 +74,7 @@ /{ mainboard_vendor = "Artec Group"; - mainboard-name = "DBE61"; + mainboard_name = "DBE61"; mainboard_pci_subsystem_vendor = "0x1022"; mainboard_pci_subsystem_device = "0x2323"; cpus { }; Modified: coreboot-v3/mainboard/artecgroup/dbe62/dts =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe62/dts 2008-07-14 23:04:48 UTC (rev 696) +++ coreboot-v3/mainboard/artecgroup/dbe62/dts 2008-07-20 21:05:25 UTC (rev 697) @@ -20,7 +20,7 @@ /{ mainboard_vendor = "Artec"; - mainboard-name = "DBE62"; + mainboard_name = "DBE62"; cpus { }; apic@0 { /config/("northbridge/amd/geodelx/apic"); Modified: coreboot-v3/mainboard/emulation/qemu-x86/dts =================================================================== --- coreboot-v3/mainboard/emulation/qemu-x86/dts 2008-07-14 23:04:48 UTC (rev 696) +++ coreboot-v3/mainboard/emulation/qemu-x86/dts 2008-07-20 21:05:25 UTC (rev 697) @@ -20,7 +20,7 @@ /{ mainboard_vendor = "Emulation"; - mainboard-name = "QEMU x86"; + mainboard_name = "QEMU x86"; mainboard_pci_subsystem_vendor = "0x15ad"; mainboard_pci_subsystem_device = "0x1976"; device_operations = "qemuvga_pci_ops_dev"; Modified: coreboot-v3/mainboard/pcengines/alix1c/dts =================================================================== --- coreboot-v3/mainboard/pcengines/alix1c/dts 2008-07-14 23:04:48 UTC (rev 696) +++ coreboot-v3/mainboard/pcengines/alix1c/dts 2008-07-20 21:05:25 UTC (rev 697) @@ -20,7 +20,7 @@ /{ mainboard_vendor = "PC Engines"; - mainboard-name = "ALIX1.C"; + mainboard_name = "ALIX1.C"; cpus { }; apic@0 { /config/("northbridge/amd/geodelx/apic"); Modified: coreboot-v3/mainboard/pcengines/alix2c3/dts =================================================================== --- coreboot-v3/mainboard/pcengines/alix2c3/dts 2008-07-14 23:04:48 UTC (rev 696) +++ coreboot-v3/mainboard/pcengines/alix2c3/dts 2008-07-20 21:05:25 UTC (rev 697) @@ -20,7 +20,7 @@ /{ mainboard_vendor = "PC Engines"; - mainboard-name = "ALIX.2C3"; + mainboard_name = "ALIX.2C3"; cpus { }; apic@0 { /config/("northbridge/amd/geodelx/apic"); Modified: coreboot-v3/util/dtc/flattree.c =================================================================== --- coreboot-v3/util/dtc/flattree.c 2008-07-14 23:04:48 UTC (rev 696) +++ coreboot-v3/util/dtc/flattree.c 2008-07-20 21:05:25 UTC (rev 697) @@ -1328,7 +1328,7 @@ extern char *code; struct node *next; extern struct node *first_node; - int found_mainboard_vendor = 0, found_mainboard_partnumber = 0, found_mainboard_subsys = 0; + int found_mainboard_vendor = 0, found_mainboard_name = 0, found_mainboard_subsys = 0; labeltree(bi->dt); @@ -1357,9 +1357,9 @@ found_mainboard_vendor = 1; fprintf(f, "const char *mainboard_vendor = \"%s\";\n", prop->val.val); } - if (streq(prop->name, "mainboard-name")){ - found_mainboard_partnumber = 1; - fprintf(f, "const char *mainboard_part_number = \"%s\";\n", prop->val.val); + if (streq(prop->name, "mainboard_name")){ + found_mainboard_name = 1; + fprintf(f, "const char *mainboard_name = \"%s\";\n", prop->val.val); } if (streq(prop->name, "mainboard_pci_subsystem_vendor")){ found_mainboard_subsys++; @@ -1373,11 +1373,11 @@ if (! found_mainboard_vendor){ die("There is no mainboard_vendor property in the root. Please add one." - "(and make sure there is a mainboard-name property too"); + "(and make sure there is a mainboard_name property too"); } - if (! found_mainboard_partnumber){ - die("There is no mainboard-name property in the root. " + if (! found_mainboard_name){ + die("There is no mainboard_name property in the root. " "Please add one." "(and make sure there is a mainboard_vendor property too"); } @@ -1436,7 +1436,7 @@ fix_next(bi->dt); /* emit any includes that we need -- TODO: ONLY ONCE PER TYPE*/ fprintf(f, "#include <device/device.h>\n#include <device/pci.h>\n"); - fprintf(f, "extern const char *mainboard_vendor, *mainboard_part_number;\n"); + fprintf(f, "extern const char *mainboard_vendor, *mainboard_name;\n"); for_each_property(bi->dt, prop) { if (streq(prop->name, "mainboard_pci_subsystem_vendor")){

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coreboot July 2008