coreboot July 2008

coreboot@coreboot.org

58 participants
214 discussions

GA-M57SLI-S4 rev 2.0 dual flash chip modification recipe
by Peter Stuge 20 Jul '08

20 Jul '08

The board can be modified in two ways. One is simpler and less reliable, the other is more complex but much more robust. Materials needed: 1x SO-8 SPI flash chip, ideally 200mil but 150mil can work too Spansion S25FL016A is easy to get. Macronix has the 32Mbit MX25L3205. 2x 0402 100k chip resistors 1x SPTD (Single Pole Dual Throw) switch and three wires For the better modification, you also need: 2x 0402 4k7 chip resistors (1k is OK too, 10k does not work!) 2x 0603 100k chip resistors 2x SOT-23 BC847C transistors See http://stuge.se/m57sli/m57sli_soic_detail_labels.jpg for reference. Common steps always needed: 1. U9: Populate flash chip 2. R509: Remove 3. R89,R130: Populate 0402 100k resistors Simple: NOTE: Keep wires to the switch short! Only a few centimeters/one inch. 4. Solder center contact on switch to Q4-3 or Q5-3. Either is OK. 5. Solder one side contact on switch to Q4-1. 6. Solder other side contact on switch to Q5-1. 7. DONE! Better: NOTE: Switch wires can be rather long. Several meters has been tested. 4. R90,R91: Populate 0402 4k7 resistors 5. R86,R389: Populate 0603 100k resistors 6. Q4,Q5: Populate SOT-23 BC847C transistors 7. Solder center contact on switch to VCC, e.g. at BC54-2. 8. Solder one side contact on switch to R86-2. 9. Solder other side contact on switch to R389-2. 10. DONE! I am happy to sell boards pre-modified with the better modification. Unfortunately I cannot offer these boards to consumers in all EU member states because of EU environmental regulations, but many are OK. //Peter

2 2

flashrom on gigabyte GA-G33-DS3R : success!
by Laurence Darby 20 Jul '08

20 Jul '08

Hi, So I took a huge leap of faith, and used flashrom to update my bios. My motherboard is gigabyte GA-G33-DS3R, lspci attached. I used: flashrom -c MX25L8005 -w g33ds3r.f7h as it had that chip (1024K) and another unknown one (0K). It took around 1 minute. btw, that worked on linux 2.6.24.7, but on linux 2.6.26 (which I need for other device support), I get: # flashrom -r bios.bin Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel ICH9R", enabling flash write... Can't mmap memory using /dev/mem: Invalid argument linux 2.6.26 has an option for filtering userspace access to /dev/mem, I tried both on and off but that didn't fix it. Regards, Laurence

3 6

r3429 - trunk/util/superiotool
by svn＠coreboot.org 19 Jul '08

19 Jul '08

Author: stepan Date: 2008-07-19 16:42:21 +0200 (Sat, 19 Jul 2008) New Revision: 3429 Modified: trunk/util/superiotool/smsc.c Log: superiotool: add support for SMSC SIO10N268 (trivial) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/util/superiotool/smsc.c =================================================================== --- trunk/util/superiotool/smsc.c 2008-07-19 14:07:35 UTC (rev 3428) +++ trunk/util/superiotool/smsc.c 2008-07-19 14:42:21 UTC (rev 3429) @@ -2,6 +2,7 @@ * This file is part of the superiotool project. * * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * Copyright (C) 2008 coresystems GmbH <info(a)coresystems.de> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -558,6 +559,28 @@ 0x00,0x80,0x00,0x00,0x00,0x03,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,EOT}}, {EOT}}}, + {0x5b, "SIO10N268", { + /* Init: 0x55. Exit: 0xaa. Ports: 0x2e/0x4e. */ + {NOLDN, NULL, + {0x00,0x01,0x03,0x04,0x04,0x05,0x06,0x07,0x08,0x09, + 0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13, + 0x14,0x15,0x16,0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d, + 0x1e,0x1f,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27, + 0x28,0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,0x30,0x31, + 0x32,0x33,0x34,0x35,0x36,0x37,0x38,0x39,0x3a,0x3b, + 0x3c,0x3d,0x3e,0x3f,0x40,0x41,0x42,0x43,0x44,0x45, + 0x46,0x47,0x48,0x49,0x4a,0x4b,0x4c,0x4d,0x4e,0x4f, + 0x50,0x51,0x52,0x53,0x54,EOT}, + {0x20,0x98,0x00,0x70,0x00,0x00,0xff,0x00,0x00,0x00, + 0x00,0x00,0x02,0x5b,NANA,0x00,0x00,0x00,MISC,0x00, + NANA,NANA,NANA,0x03,0x00,NANA,NANA,0x00,0x00,0x00, + NANA,0x00,0x3c,0x00,0x00,0x00,0x00,0x00,0xff,0x00, + 0x00,0x80,0x00,0x00,0x0f,0x03,0x00,0x00,0x00,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,0x00,0x00, + 0x00,0x00,0x00,0x00,NANA,NANA,NANA,NANA,NANA,0x50, + NANA,0x00,NANA,NANA,NANA,NANA,NANA,NANA,0x00,0x01, + 0x00,0x01,0x00,0x8c,MISC,EOT}}, + {EOT}}}, {0x65, "FDC37C665GT/IR", { /* Init: 0x55, 0x55. Exit: 0xaa. Port: 0x3f0. */ /* Chiprev: 0x02 = FDC37C665GT, 0x82 = FDC37C665IR */

1 0

r3428 - trunk/util/superiotool
by svn＠coreboot.org 19 Jul '08

19 Jul '08

Author: stepan Date: 2008-07-19 16:07:35 +0200 (Sat, 19 Jul 2008) New Revision: 3428 Modified: trunk/util/superiotool/smsc.c Log: add support for 2 new SMSC superio chips. Information is a bit ambiguous and scattered within the datasheets. (trivial patch) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/util/superiotool/smsc.c =================================================================== --- trunk/util/superiotool/smsc.c 2008-07-18 14:08:18 UTC (rev 3427) +++ trunk/util/superiotool/smsc.c 2008-07-19 14:07:35 UTC (rev 3428) @@ -32,8 +32,80 @@ /* FIXME: There's another 0x03 but found on port 0x0d/0x0e! */ {EOT}}}, {0x0a, "FDC37N971", { + {NOLDN, NULL, + {0x02,0x07,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27, + 0x28,0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, + {0x00,0x00,0x0a,0x00,0x00,0x00,0x04,0x04,NANA,NANA, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x0, "Floppy", + {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf3,0xf4, + 0xf5,EOT}, + {0x00,0x03,0xf0,0x06,0x02,0x0e,0x00,0xff,RSVD,0x00, + 0x00,EOT}}, + {0x1, "Power Management (PM1)", + {0x30,0x60,0x61,EOT}, + {0x00,0x00,0x00,EOT}}, + {0x3, "Parallel port", + {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,EOT}, + {0x00,0x00,0x00,0x00,0x04,0x3c,0x00,EOT}}, + {0x4, "COM1", + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x5, "COM2", + {0x30,0x60,0x61,0x62,0x63,0x70,0x74,0xf0,0xf1, + 0xf2,0xf7,0xf8,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x02, + 0x03,0x00,0x00,EOT}}, + {0x6, "Real-time clock (RTC)", + {0x30,0x60,0x61,0x62,0x63,0x70,0xf0,0xf1,EOT}, + {0x00,0x00,0x70,0x00,0x74,0x00,0x00,NANA,EOT}}, + {0x7, "Keyboard", + {0x30,0x60,0x61,0x70,0x72,0xf0,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x8, "Embedded Controller (EC)", + {0x30,0x60,0x61,EOT}, + {0x00,0x00,0x62,EOT}}, + {0x9, "Mailbox", + {0x30,0x60,0x61,EOT}, + {0x00,0x00,0x00,EOT}}, {EOT}}}, {0x0b, "FDC37N972", { + {NOLDN, NULL, + {0x02,0x07,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27, + 0x28,0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, + {0x00,0x00,0x0b,0x00,0x00,0x00,0x04,0x04,NANA,NANA, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x0, "Floppy", + {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf3,0xf4, + 0xf5,EOT}, + {0x00,0x03,0xf0,0x06,0x02,0x0e,0x00,0xff,RSVD,0x00, + 0x00,EOT}}, + {0x1, "Power Management (PM1)", + {0x30,0x60,0x61,EOT}, + {0x00,0x00,0x00,EOT}}, + {0x3, "Parallel port", + {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,EOT}, + {0x00,0x00,0x00,0x00,0x04,0x3c,0x00,EOT}}, + {0x4, "COM1", + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x5, "COM2", + {0x30,0x60,0x61,0x62,0x63,0x70,0x74,0xf0,0xf1, + 0xf2,0xf7,0xf8,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x02, + 0x03,0x00,0x00,EOT}}, + {0x6, "Real-time clock (RTC)", + {0x30,0x60,0x61,0x62,0x63,0x70,0xf0,0xf1,EOT}, + {0x00,0x00,0x70,0x00,0x74,0x00,0x00,NANA,EOT}}, + {0x7, "Keyboard", + {0x30,0x60,0x61,0x70,0x72,0xf0,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x8, "Embedded Controller (EC)", + {0x30,0x60,0x61,EOT}, + {0x00,0x00,0x62,EOT}}, + {0x9, "Mailbox", + {0x30,0x60,0x61,EOT}, + {0x00,0x00,0x00,EOT}}, {EOT}}}, {0x0e, "LPC47N252", { /* From sensors-detect */ {EOT}}},

1 0

SeaBIOS release date
by Myles Watson 18 Jul '08

18 Jul '08

Kevin, Have you tried setting the release date for SeaBIOS before 1/1/99? That should disable ACPI in the windows install, according to: http://support.microsoft.com/kb/216573 It didn't help me, but I'm still having the mouse problems. Thanks, Myles

1 0

r3427 - trunk/payloads/coreinfo
by svn＠coreboot.org 18 Jul '08

18 Jul '08

Author: uwe Date: 2008-07-18 16:08:18 +0200 (Fri, 18 Jul 2008) New Revision: 3427 Modified: trunk/payloads/coreinfo/coreinfo.c trunk/payloads/coreinfo/lar_module.c Log: Random coding style fixes and simplifications (trivial). This will even reduce the final payload size a bit. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/payloads/coreinfo/coreinfo.c =================================================================== --- trunk/payloads/coreinfo/coreinfo.c 2008-07-17 19:54:06 UTC (rev 3426) +++ trunk/payloads/coreinfo/coreinfo.c 2008-07-18 14:08:18 UTC (rev 3427) @@ -77,7 +77,6 @@ } }; - static WINDOW *modwin; static WINDOW *menuwin; @@ -121,14 +120,14 @@ { struct tm tm; - while(nvram_updating()) + while (nvram_updating()) mdelay(10); rtc_read_clock(&tm); mvwprintw(menuwin, 0, 57, "%02d/%02d/%04d - %02d:%02d:%02d", - tm.tm_mon, tm.tm_mday, 1900+tm.tm_year, tm.tm_hour, - tm.tm_min, tm.tm_sec); + tm.tm_mon, tm.tm_mday, 1900+tm.tm_year, tm.tm_hour, + tm.tm_min, tm.tm_sec); } #endif @@ -184,8 +183,6 @@ ptr += sprintf(ptr, "[ %s ]", str); - - for (i = ((SCREEN_X - len) / 2) + len; i < SCREEN_X; i++) ptr += sprintf(ptr, "="); @@ -207,10 +204,8 @@ { if (key >= 'a' && key <= 'z') { int index = key - 'a'; - if (index < cat->count) { - - cat->cur = index; + cat->cur = index; redraw_module(cat); return; } @@ -296,7 +291,7 @@ wrefresh(modwin); for (i = 0; i < ARRAY_SIZE(categories); i++) { - for(j = 0; j < categories[i].count; j++) + for (j = 0; j < categories[i].count; j++) categories[i].modules[j]->init(); } @@ -306,6 +301,6 @@ return 0; } -PAYLOAD_INFO(name,"coreinfo"); -PAYLOAD_INFO(listname,"System Information"); -PAYLOAD_INFO(desc,"Display information about the system"); +PAYLOAD_INFO(name, "coreinfo"); +PAYLOAD_INFO(listname, "System Information"); +PAYLOAD_INFO(desc, "Display information about the system"); Modified: trunk/payloads/coreinfo/lar_module.c =================================================================== --- trunk/payloads/coreinfo/lar_module.c 2008-07-17 19:54:06 UTC (rev 3426) +++ trunk/payloads/coreinfo/lar_module.c 2008-07-18 14:08:18 UTC (rev 3427) @@ -22,8 +22,9 @@ #ifdef CONFIG_MODULE_LAR static struct LAR *lar; -static int lcount; +static int lcount, selected; static char **lnames; +static const char *compression_table[4] = {"none", "LZMA", "NRV2B", "zeroes"}; static int lar_module_init(void) { @@ -35,7 +36,7 @@ if (lar == NULL) return 0; - while((larent = readlar(lar))) + while ((larent = readlar(lar))) lcount++; lnames = malloc(lcount * sizeof(char *)); @@ -45,37 +46,30 @@ rewindlar(lar); - while((larent = readlar(lar))) + while ((larent = readlar(lar))) lnames[index++] = strdup((const char *) larent->name); return 0; } -static int selected; - static int lar_module_redraw(WINDOW *win) { - int i; - int row = 2; + int i, row = 2; struct larstat stat; print_module_title(win, "LAR Listing"); if (lar == 0) { - mvwprintw(win, 11, 61/2, "Bad or missing LAR"); + mvwprintw(win, 11, 61 / 2, "Bad or missing LAR"); return 0; } - /* Draw a line down the middle */ + /* Draw a line down the middle. */ + for (i = 2; i < 21; i++) + mvwaddch(win, i, 30, '\263'); - for(i = 2; i < 20; i++) { - wmove(win, i, 30); - waddch(win, '\263'); - } - - /* Draw the names down the left side */ - - for(i = 0; i < lcount; i++) { + /* Draw the names down the left side. */ + for (i = 0; i < lcount; i++) { if (i == selected) wattrset(win, COLOR_PAIR(3) | A_BOLD); else @@ -84,8 +78,7 @@ mvwprintw(win, 2 + i, 1, "%.25s", lnames[i]); } - /* Get the information for the LAR */ - + /* Get the information for the LAR. */ if (larstat(lar, lnames[selected], &stat)) { printf("larstat failed\n"); return 0; @@ -96,26 +89,17 @@ mvwprintw(win, row++, 32, "Offset: 0x%x", stat.offset); if (stat.compression) { - switch(stat.compression) { - case ALGO_LZMA: - mvwprintw(win, row++, 32, "Compression: LZMA"); - break; - case ALGO_NRV2B: - mvwprintw(win, row++, 32, "Compression: NRV2B"); - break; - case ALGO_ZEROES: - mvwprintw(win, row++, 32, "Compression: zeroes"); - break; - } - + mvwprintw(win, row++, 32, "Compression: %s", + compression_table[stat.compression]); mvwprintw(win, row++, 32, "Compressed length: %d", stat.len); - mvwprintw(win, row++, 32, "Compressed checksum: 0x%x", stat.compchecksum); + mvwprintw(win, row++, 32, "Compressed checksum: 0x%x", + stat.compchecksum); } mvwprintw(win, row++, 32, "Length: %d", stat.reallen); mvwprintw(win, row++, 32, "Checksum: 0x%x", stat.checksum); - mvwprintw(win, row++, 32, "Load Address: 0x%llx", stat.loadaddress); - mvwprintw(win, row++, 32, "Entry Point: 0x%llx", stat.entry); + mvwprintw(win, row++, 32, "Load address: 0x%llx", stat.loadaddress); + mvwprintw(win, row++, 32, "Entry point: 0x%llx", stat.entry); return 0; } @@ -151,13 +135,10 @@ .redraw = lar_module_redraw, .handle = lar_module_handle }; + #else struct coreinfo_module lar_module = { }; #endif - - - -

1 0

Super IO: Winbond W83697HF Support
by Sean Nelson 18 Jul '08

18 Jul '08

Here's a patch for coreboot v2 for Winbond W83697HF Support. Patch Attached.

2 1

Re: [coreboot] NEOWARE EON 4000S
by Uwe Hermann 18 Jul '08

18 Jul '08

[forwarding to the mailing list] On Tue, Jul 15, 2008 at 09:20:47PM +0200, Hannes Hegewald wrote: > Hey, I applied the patch, built a new 2.6.26 kernel an ran getpir again. > Two things changed: > /* IRQs devoted exclusively to PCI usage */ and the /* u8 checksum. > The new file is attached. > I also have already tried the new irq_tables.c file by placing it in > src/mainboard/asi/mb_5blgp and running the ./buildtarget script again. > unfortunately nothing changed. > > Thanks, Hannes > > /* This file was generated by getpir.c, do not modify! > * (but if you do, please run checkpir on it to verify) > * > * Contains the IRQ Routing Table dumped directly from your > * memory, which BIOS sets up. > * > * Documentation at: http://www.microsoft.com/whdc/archive/pciirq.mspx > */ > > #ifdef GETPIR > #include "pirq_routing.h" > #else > #include <arch/pirq_routing.h> > #endif > > const struct irq_routing_table intel_irq_routing_table = { > PIRQ_SIGNATURE, /* u32 signature */ > PIRQ_VERSION, /* u16 version */ > 32+16*3, /* There can be total 3 devices on the bus */ > 0x00, /* Where the interrupt router lies (bus) */ > (0x12<<3)|0x0, /* Where the interrupt router lies (dev) */ > 0x8c00, /* IRQs devoted exclusively to PCI usage */ > 0x1078, /* Vendor */ > 0x2, /* Device */ > 0, /* Crap (miniport) */ > { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ > 0x92, /* u8 checksum. This has to be set to some > value that would give 0 after the sum of all > bytes for this structure (including checksum) */ > { > /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ > {0x00,(0x07<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0}, > {0x00,(0x0f<<3)|0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x2, 0x0}, > {0x00,(0x13<<3)|0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, > } > }; > > unsigned long write_pirq_routing_table(unsigned long addr) > { > return copy_pirq_routing_table(addr); > } Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

1 0

HT credits and the Opteron
by Myles Watson 18 Jul '08

18 Jul '08

Anyone with detailed knowledge of (or more manuals than I have for) the Opteron, I just noticed that the Nvidia ck804 reduces the amount of credits which the Opteron gives it (probably due to an errata.) Does that mean that there should be more credits available for the other HT links? Is buffer space per link or does the CPU share it all between all the links? What if a link is disabled? Should you give its credits to the others? In the BKDG for the Opteron it says that you shouldn't change the values in general, because software picks the right values, but that's us. It doesn't say how you should pick new values. Thanks, Myles

2 3

[RFC] coreboot and embedded controllers, for example OLPC and its OpenEC code
by Ken.Fuchs＠bench.com 18 Jul '08

18 Jul '08

Embedded controllers are being put on mainboards to add functionality that the chipset and other support chips can't easily provide. The most common application is keyboard handling on laptops. Another example is the embedded controllers added to servers for various management features. Embedded controllers seem to be showing up now for many Intel PC board designs for such things as power management and LPC to SPI interfacing to support SPI NOR flash booting of the BIOS/firmware. I'm looking for an open source micro-controller project that could be adapted to for use on PC embedded controllers as described above. What happened with the OLPC's OpenEC code? Was that ever completed? Did the name change to something else? Is it currently being developed? Is there a viable alternative to OpenEC for embedded controller code? Will it work with coreboot or appropriate payloads? Any comments regarding coreboot and embedded controllers? Sincerely, Ken Fuchs

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coreboot July 2008