coreboot June 2008

coreboot@coreboot.org

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[PATCH] flashrom: clean up SPI probing, bus handling
by Stefan Reinauer 29 Jun '08

29 Jun '08

See patch. It's a first attempt, but I think we should get this in in small enough step by step improvements. -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 First attempt to clean up SPI probing and create a common construct: the flash bus. At some point the flash bus will be part of struct flashchip. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Index: flash.h =================================================================== --- flash.h (revision 3393) +++ flash.h (working copy) @@ -370,10 +370,18 @@ /* chipset_enable.c */ int chipset_flash_enable(void); void print_supported_chipsets(void); -extern int ich7_detected; -extern int ich9_detected; -extern void *ich_spibar; +typedef enum { + BUS_TYPE_LPC, + BUS_TYPE_ICH7_SPI, + BUS_TYPE_ICH9_SPI, + BUS_TYPE_IT87XX_SPI, + BUS_TYPE_VIA_SPI +} flashbus_t; + +extern flashbus_t flashbus; +extern void *spibar; + /* Physical memory mapping device */ #if defined (__sun) && (defined(__i386) || defined(__amd64)) # define MEM_DEV "/dev/xsvc" Index: it87spi.c =================================================================== --- it87spi.c (revision 3393) +++ it87spi.c (working copy) @@ -3,6 +3,7 @@ * * Copyright (C) 2007, 2008 Carl-Daniel Hailfinger * Copyright (C) 2008 Ronald Hoogenboom <ronald(a)zonnet.nl> + * Copyright (C) 2008 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -112,8 +113,13 @@ int it87xx_probe_spi_flash(const char *name) { it8716f_flashport = find_ite_spi_flash_port(ITE_SUPERIO_PORT1); + if (!it8716f_flashport) it8716f_flashport = find_ite_spi_flash_port(ITE_SUPERIO_PORT2); + + if (it8716f_flashport) + flashbus = BUS_TYPE_IT87XX_SPI; + return (!it8716f_flashport); } Index: spi.c =================================================================== --- spi.c (revision 3393) +++ spi.c (working copy) @@ -34,13 +34,15 @@ int spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { - if (it8716f_flashport) + switch (flashbus) { + case BUS_TYPE_IT87XX_SPI: return it8716f_spi_command(writecnt, readcnt, writearr, readarr); - else if (ich7_detected) + case BUS_TYPE_ICH7_SPI: + case BUS_TYPE_ICH9_SPI: return ich_spi_command(writecnt, readcnt, writearr, readarr); - else if (ich9_detected) - return ich_spi_command(writecnt, readcnt, writearr, readarr); - printf_debug("%s called, but no SPI chipset detected\n", __FUNCTION__); + default: + printf_debug("%s called, but no SPI chipset/strapping detected\n", __FUNCTION__); + } return 1; } @@ -299,11 +301,17 @@ void spi_page_program(int block, uint8_t *buf, uint8_t *bios) { - if (it8716f_flashport) { + switch (flashbus) { + case BUS_TYPE_IT87XX_SPI: it8716f_spi_page_program(block, buf, bios); - return; + break; + case BUS_TYPE_ICH7_SPI: + case BUS_TYPE_ICH9_SPI: + printf_debug("%s called, but not implemented for ICH\n", __FUNCTION__); + break; + default: + printf_debug("%s called, but no SPI chipset/strapping detected\n", __FUNCTION__); } - printf_debug("%s called, but no SPI chipset detected\n", __FUNCTION__); } /* @@ -358,25 +366,32 @@ int spi_chip_read(struct flashchip *flash, uint8_t *buf) { - if (it8716f_flashport) + + switch (flashbus) { + case BUS_TYPE_IT87XX_SPI: return it8716f_spi_chip_read(flash, buf); - else if (ich7_detected) - return ich_spi_read(flash, buf); - else if (ich9_detected) + case BUS_TYPE_ICH7_SPI: + case BUS_TYPE_ICH9_SPI: return ich_spi_read(flash, buf); - printf_debug("%s called, but no SPI chipset detected\n", __FUNCTION__); + default: + printf_debug("%s called, but no SPI chipset/strapping detected\n", __FUNCTION__); + } + return 1; } int spi_chip_write(struct flashchip *flash, uint8_t *buf) { - if (it8716f_flashport) + switch (flashbus) { + case BUS_TYPE_IT87XX_SPI: return it8716f_spi_chip_write(flash, buf); - else if (ich7_detected) - return ich_spi_write(flash, buf); - else if (ich9_detected) + case BUS_TYPE_ICH7_SPI: + case BUS_TYPE_ICH9_SPI: return ich_spi_write(flash, buf); - printf_debug("%s called, but no SPI chipset detected\n", __FUNCTION__); + default: + printf_debug("%s called, but no SPI chipset/strapping detected\n", __FUNCTION__); + } + return 1; } Index: chipset_enable.c =================================================================== --- chipset_enable.c (revision 3393) +++ chipset_enable.c (working copy) @@ -35,6 +35,17 @@ #include <unistd.h> #include "flash.h" +/** + * flashrom defaults to LPC flash devices. If a known SPI controller is found + * and the SPI strappings are set, this will be overwritten by the probing code. + * + * Eventually, this will become an array when multiple flash support works. + */ + +flashbus_t flashbus = BUS_TYPE_LPC; +void *spibar = NULL; + + static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name) { uint8_t tmp; @@ -124,7 +135,7 @@ * Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA. * Set bit 2: BIOSCS# Write Enable (1=enable, 0=disable). */ - new = old | 0x2c4; + new = old | 0x02c4; if (new == old) return 0; @@ -185,68 +196,106 @@ return enable_flash_ich(dev, name, 0xdc); } -void *ich_spibar = NULL; +#define ICH_STRAP_RSVD 0x00 +#define ICH_STRAP_SPI 0x01 +#define ICH_STRAP_PCI 0x02 +#define ICH_STRAP_LPC 0x03 -static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, unsigned long spibar) +static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, int ich_generation) { + int ret, i; uint8_t old, new, bbs, buc; + uint16_t spibar_offset; uint32_t tmp, gcs; void *rcrb; + static const char *straps_names[] = { "reserved", "SPI", "PCI", "LPC" }; + + /* Enable Flash Writes */ + ret = enable_flash_ich_dc(dev, name); - /* Read the Root Complex Base Address Register (RCBA) */ - tmp = pci_read_long(dev, 0xf0); + /* Get physical address of Root Complex Register Block */ + tmp = pci_read_long(dev, 0xf0) & 0xffffc000; + printf_debug("\nRoot Complex Register Block address = 0x%x\n", tmp); - /* Calculate the Root Complex Register Block address */ - tmp &= 0xffffc000; - printf_debug("\nRoot Complex Register Block address = 0x%x\n", tmp); + /* Map RCBA to virtual memory */ rcrb = mmap(0, 0x4000, PROT_READ | PROT_WRITE, MAP_SHARED, fd_mem, (off_t)tmp); if (rcrb == MAP_FAILED) { perror("Can't mmap memory using " MEM_DEV); exit(1); } - printf_debug("GCS address = 0x%x\n", tmp + 0x3410); + gcs = *(volatile uint32_t *)(rcrb + 0x3410); printf_debug("GCS = 0x%x: ", gcs); printf_debug("BIOS Interface Lock-Down: %sabled, ", (gcs & 0x1) ? "en" : "dis"); bbs = (gcs >> 10) & 0x3; - printf_debug("BOOT BIOS Straps: 0x%x (%s)\n", bbs, - (bbs == 0x3) ? "LPC" : ((bbs == 0x2) ? "PCI" : "SPI")); + printf_debug("BOOT BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]); buc = *(volatile uint8_t *)(rcrb + 0x3414); printf_debug("Top Swap : %s\n", (buc & 1)?"enabled (A16 inverted)":"not enabled"); + if (bbs == ICH_STRAP_LPC) { + /* No further SPI initialization required */ + return ret; + } + + switch (ich_generation) { + case 7: + flashbus = BUS_TYPE_ICH7_SPI; + spibar_offset = 0x3020; + break; + case 8: + flashbus = BUS_TYPE_ICH9_SPI; + spibar_offset = 0x3020; + break; + case 9: + default: /* Future version might behave the same */ + flashbus = BUS_TYPE_ICH9_SPI; + spibar_offset = 0x3800; + break; + } + /* SPIBAR is at RCRB+0x3020 for ICH[78] and RCRB+0x3800 for ICH9. */ - printf_debug("SPIBAR = 0x%x + 0x%04x\n", tmp, (uint16_t)spibar); + printf_debug("SPIBAR = 0x%x + 0x%04x\n", tmp, spibar_offset); - // Assign Virtual Address - ich_spibar = rcrb + spibar; + /* Assign Virtual Address */ + spibar = rcrb + spibar_offset; - if (ich7_detected) { - int i; - printf_debug("0x00: 0x%04x (SPIS)\n", *(uint16_t *)(ich_spibar + 0)); - printf_debug("0x02: 0x%04x (SPIC)\n", *(uint16_t *)(ich_spibar + 2)); - printf_debug("0x04: 0x%08x (SPIA)\n", *(uint32_t *)(ich_spibar + 4)); + switch (flashbus) { + case BUS_TYPE_ICH7_SPI: + printf_debug("0x00: 0x%04x (SPIS)\n", *(uint16_t *)(spibar + 0)); + printf_debug("0x02: 0x%04x (SPIC)\n", *(uint16_t *)(spibar + 2)); + printf_debug("0x04: 0x%08x (SPIA)\n", *(uint32_t *)(spibar + 4)); for (i=0; i < 8; i++) { int offs; offs = 8 + (i * 8); - printf_debug("0x%02x: 0x%08x (SPID%d)\n", offs, *(uint32_t *)(ich_spibar + offs), i); - printf_debug("0x%02x: 0x%08x (SPID%d+4)\n", offs+4, *(uint32_t *)(ich_spibar + offs +4), i); + printf_debug("0x%02x: 0x%08x (SPID%d)\n", offs, *(uint32_t *)(spibar + offs), i); + printf_debug("0x%02x: 0x%08x (SPID%d+4)\n", offs+4, *(uint32_t *)(spibar + offs +4), i); } - printf_debug("0x50: 0x%08x (BBAR)\n", *(uint32_t *)(ich_spibar + 0x50)); - printf_debug("0x54: 0x%04x (PREOP)\n", *(uint16_t *)(ich_spibar + 0x54)); - printf_debug("0x56: 0x%04x (OPTYPE)\n", *(uint16_t *)(ich_spibar + 0x56)); - printf_debug("0x58: 0x%08x (OPMENU)\n", *(uint32_t *)(ich_spibar + 0x58)); - printf_debug("0x5c: 0x%08x (OPMENU+4)\n", *(uint32_t *)(ich_spibar + 0x5c)); + printf_debug("0x50: 0x%08x (BBAR)\n", *(uint32_t *)(spibar + 0x50)); + printf_debug("0x54: 0x%04x (PREOP)\n", *(uint16_t *)(spibar + 0x54)); + printf_debug("0x56: 0x%04x (OPTYPE)\n", *(uint16_t *)(spibar + 0x56)); + printf_debug("0x58: 0x%08x (OPMENU)\n", *(uint32_t *)(spibar + 0x58)); + printf_debug("0x5c: 0x%08x (OPMENU+4)\n", *(uint32_t *)(spibar + 0x5c)); for (i=0; i < 4; i++) { int offs; offs = 0x60 + (i * 4); - printf_debug("0x%02x: 0x%08x (PBR%d)\n", offs, *(uint32_t *)(ich_spibar + offs), i); + printf_debug("0x%02x: 0x%08x (PBR%d)\n", offs, *(uint32_t *)(spibar + offs), i); } printf_debug("\n"); - if ( (*(uint16_t *)ich_spibar) & (1 << 15)) { + if ( (*(uint16_t *)spibar) & (1 << 15)) { printf("WARNING: SPI Configuration Lockdown activated.\n"); } + break; + case BUS_TYPE_ICH9_SPI: + /* TODO: Add dumping function for ICH8/ICH9, or drop the + * whole SPIBAR dumping from chipset_enable.c - There's + * inteltool for this task already. + */ + break; + default: + /* Nothing */ + break; } old = pci_read_byte(dev, 0xdc); @@ -257,37 +306,30 @@ case 1: case 2: printf_debug("prefetching %sabled, caching %sabled, ", - (new & 0x2) ? "en" : "dis", (new & 0x1) ? "dis" : "en"); + (new & 0x2) ? "en" : "dis", + (new & 0x1) ? "dis" : "en"); break; default: printf_debug("invalid prefetching/caching settings, "); break; } - return enable_flash_ich_dc(dev, name); + + return ret; } -/* Flag for ICH7 SPI register block */ -int ich7_detected = 0; - static int enable_flash_ich7(struct pci_dev *dev, const char *name) { - ich7_detected = 1; - return enable_flash_ich_dc_spi(dev, name, 0x3020); + return enable_flash_ich_dc_spi(dev, name, 7); } -/* Flag for ICH8/ICH9 SPI register block */ -int ich9_detected = 0; - static int enable_flash_ich8(struct pci_dev *dev, const char *name) { - ich9_detected = 1; - return enable_flash_ich_dc_spi(dev, name, 0x3020); + return enable_flash_ich_dc_spi(dev, name, 8); } static int enable_flash_ich9(struct pci_dev *dev, const char *name) { - ich9_detected = 1; - return enable_flash_ich_dc_spi(dev, name, 0x3800); + return enable_flash_ich_dc_spi(dev, name, 9); } static int enable_flash_vt823x(struct pci_dev *dev, const char *name) Index: ichspi.c =================================================================== --- ichspi.c (revision 3393) +++ ichspi.c (working copy) @@ -123,20 +123,20 @@ static inline uint32_t REGREAD32(int X) { volatile uint32_t regval; - regval = *(volatile uint32_t *) ((uint8_t *) ich_spibar + X); + regval = *(volatile uint32_t *) ((uint8_t *) spibar + X); return regval; } static inline uint16_t REGREAD16(int X) { volatile uint16_t regval; - regval = *(volatile uint16_t *) ((uint8_t *) ich_spibar + X); + regval = *(volatile uint16_t *) ((uint8_t *) spibar + X); return regval; } -#define REGWRITE32(X,Y) (*(uint32_t *)((uint8_t *)ich_spibar+X)=Y) -#define REGWRITE16(X,Y) (*(uint16_t *)((uint8_t *)ich_spibar+X)=Y) -#define REGWRITE8(X,Y) (*(uint8_t *)((uint8_t *)ich_spibar+X)=Y) +#define REGWRITE32(X,Y) (*(uint32_t *)((uint8_t *)spibar+X)=Y) +#define REGWRITE16(X,Y) (*(uint16_t *)((uint8_t *)spibar+X)=Y) +#define REGWRITE8(X,Y) (*(uint8_t *)((uint8_t *)spibar+X)=Y) /* Common SPI functions */ static int program_opcodes(OPCODES * op); @@ -167,58 +167,50 @@ int program_opcodes(OPCODES * op) { uint8_t a; - uint16_t temp16; - uint32_t temp32; + uint16_t preop, optype; + uint32_t opmenu[2]; /* Program Prefix Opcodes */ - temp16 = 0; + preop = 0; /* 0:7 Prefix Opcode 1 */ - temp16 = (op->preop[0]); + preop = (op->preop[0]); /* 8:16 Prefix Opcode 2 */ - temp16 |= ((uint16_t) op->preop[1]) << 8; - if (ich7_detected) { - REGWRITE16(ICH7_REG_PREOP, temp16); - } else if (ich9_detected) { - REGWRITE16(ICH9_REG_PREOP, temp16); - } - + preop |= ((uint16_t) op->preop[1]) << 8; + /* Program Opcode Types 0 - 7 */ - temp16 = 0; + optype = 0; for (a = 0; a < 8; a++) { - temp16 |= ((uint16_t) op->opcode[a].spi_type) << (a * 2); + optype |= ((uint16_t) op->opcode[a].spi_type) << (a * 2); } - - if (ich7_detected) { - REGWRITE16(ICH7_REG_OPTYPE, temp16); - } else if (ich9_detected) { - REGWRITE16(ICH9_REG_OPTYPE, temp16); - } - - + /* Program Allowable Opcodes 0 - 3 */ - temp32 = 0; + opmenu[0] = 0; for (a = 0; a < 4; a++) { - temp32 |= ((uint32_t) op->opcode[a].opcode) << (a * 8); + opmenu[0] |= ((uint32_t) op->opcode[a].opcode) << (a * 8); } - if (ich7_detected) { - REGWRITE32(ICH7_REG_OPMENU, temp32); - } else if (ich9_detected) { - REGWRITE32(ICH9_REG_OPMENU, temp32); - } - - /*Program Allowable Opcodes 4 - 7 */ - temp32 = 0; + opmenu[1] = 0; for (a = 4; a < 8; a++) { - temp32 |= - ((uint32_t) op->opcode[a].opcode) << ((a - 4) * 8); + opmenu[1] |= ((uint32_t) op->opcode[a].opcode) << ((a - 4) * 8); } - if (ich7_detected) { - REGWRITE32(ICH7_REG_OPMENU + 4, temp32); - } else if (ich9_detected) { - REGWRITE32(ICH9_REG_OPMENU + 4, temp32); + switch (flashbus) { + case BUS_TYPE_ICH7_SPI: + REGWRITE16(ICH7_REG_PREOP, preop); + REGWRITE16(ICH7_REG_OPTYPE, optype); + REGWRITE32(ICH7_REG_OPMENU, opmenu[0]); + REGWRITE32(ICH7_REG_OPMENU + 4, opmenu[1]); + break; + case BUS_TYPE_ICH9_SPI: + REGWRITE16(ICH9_REG_PREOP, preop); + REGWRITE16(ICH9_REG_OPTYPE, optype); + REGWRITE32(ICH9_REG_OPMENU, opmenu[0]); + REGWRITE32(ICH9_REG_OPMENU + 4, opmenu[1]); + break; + default: + printf_debug("%s: unsupported chipset\n", __FUNCTION__); + return -1; } return 0; @@ -332,6 +324,7 @@ uint8_t datalength, uint8_t * data) { int write_cmd = 0; + int timeout; uint32_t temp32; uint32_t a; @@ -402,10 +395,13 @@ REGWRITE32(ICH9_REG_SSFS, temp32); /*wait for cycle complete */ - while ((REGREAD32(ICH9_REG_SSFS) & SSFS_CDS) == 0) { - /*TODO; Do something that this can't lead into an endless loop. but some - * commands may cause this to be last more than 30 seconds */ + timeout = 1000 * 60; // 60s is a looong timeout. + while (((REGREAD32(ICH9_REG_SSFS) & SSFS_CDS) == 0) && --timeout) { + myusec_delay(1000); } + if (!timeout) { + printf_debug("timeout\n"); + } if ((REGREAD32(ICH9_REG_SSFS) & SSFS_FCERR) != 0) { printf_debug("Transaction error!\n"); @@ -430,10 +426,13 @@ static int run_opcode(uint8_t nr, OPCODE op, uint32_t offset, uint8_t datalength, uint8_t * data) { - if (ich7_detected) + switch (flashbus) { + case BUS_TYPE_ICH7_SPI: return ich7_run_opcode(nr, op, offset, datalength, data); - else if (ich9_detected) { + case BUS_TYPE_ICH9_SPI: return ich9_run_opcode(nr, op, offset, datalength, data); + default: + printf_debug("%s: unsupported chipset\n", __FUNCTION__); } /* If we ever get here, something really weird happened */

2 7

r3397 - trunk/util/flashrom
by svn＠coreboot.org 29 Jun '08

29 Jun '08

Author: hailfinger Date: 2008-06-29 12:57:13 +0200 (Sun, 29 Jun 2008) New Revision: 3397 Modified: trunk/util/flashrom/ichspi.c Log: Add a debug marker after ICH SPI opcode programming. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/util/flashrom/ichspi.c =================================================================== --- trunk/util/flashrom/ichspi.c 2008-06-29 06:41:12 UTC (rev 3396) +++ trunk/util/flashrom/ichspi.c 2008-06-29 10:57:13 UTC (rev 3397) @@ -581,9 +581,10 @@ /* program opcodes if not already done */ if (curopcodes == NULL) { - printf_debug("Programming OPCODES\n"); + printf_debug("Programming OPCODES... "); curopcodes = &O_ST_M25P; program_opcodes(curopcodes); + printf_debug("done\n"); } /* find cmd in opcodes-table */

1 0

flashrom doesn't work?
by Star Liu 29 Jun '08

29 Jun '08

I learned that flashrom can save an image of the old BIOS and write it to a new BIOS chip. so i installed it on my Debian lenny AMD64, and execute it this way "flashrom -r AMIBIOS", but the output is: ----------------------------------------------- StarLiuLenny64:~# flashrom -r AMIBIOS Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel ICH7/ICH7R", enabling flash write... OK. No EEPROM/flash device found. ----------------------------------------------------- no AMIBIOS created. is it a bug of flashrom? -- ------------------------------------------------------------------------------------------------------------------------ Homepage: http://starliu.9966.org, about Buddha, x86_64 CPU, Debian GNU/Linux, UEFI/BIOS ------------------------------------------------------------------------------------------------------------------------

1 0

[PATCHes][v2][v3] baud rate in serial entries in lbtable (and console entries in lbtable for v3)
by Patrick Georgi 29 Jun '08

29 Jun '08

Hi, two patches this time, one for cbv2, one for cbv3: patch-20080628-1-baud-in-serial-cbv2 adds an entry to the serial port descriptor about the configured line speed. this is compatible, as the field size is stored with the entry, and data was only appended. so well-behaving clients that skip based on entry size (and not based on their own local idea of how large entries are) automatically do the right thing. patch-20080628-2-consoles-in-cbv3-lbtable implements the console and serial lbtable entries compatible to cbv2+above patch for cbv3 Signed-off-bys are at the header of each patch. Regards, Patrick Georgi Signed-Off-By: Patrick Georgi <patrick(a)georgi-clan.de> Index: src/include/boot/coreboot_tables.h =================================================================== --- src/include/boot/coreboot_tables.h (revision 3393) +++ src/include/boot/coreboot_tables.h (working copy) @@ -145,6 +145,7 @@ uint32_t tag; uint32_t size; uint16_t ioport; + uint32_t baud; }; #define LB_TAG_CONSOLE 0x0010 Index: src/arch/i386/boot/coreboot_table.c =================================================================== --- src/arch/i386/boot/coreboot_table.c (revision 3393) +++ src/arch/i386/boot/coreboot_table.c (working copy) @@ -84,6 +84,7 @@ serial->tag = LB_TAG_SERIAL; serial->size = sizeof(*serial); serial->ioport = TTYS0_BASE; + serial->baud = TTYS0_BAUD; return serial; #else return header; Signed-Off-By: Patrick Georgi <patrick(a)georgi-clan.de> Index: include/tables.h =================================================================== --- include/tables.h (revision 690) +++ include/tables.h (working copy) @@ -175,6 +175,28 @@ u32 dev_root_ptr; /* Pointer to the root device */ }; +#define LB_TAG_SERIAL 0x000f +struct lb_serial { + u32 tag; + u32 size; + u16 ioport; + u32 baud; +}; + +#define LB_TAG_CONSOLE 0x0010 +struct lb_console { + u32 tag; + u32 size; + u16 type; +}; + +#define LB_TAG_CONSOLE_SERIAL8250 0 +#define LB_TAG_CONSOLE_VGA 1 +#define LB_TAG_CONSOLE_BTEXT 2 +#define LB_TAG_CONSOLE_LOGBUF 3 +#define LB_TAG_CONSOLE_SROM 4 +#define LB_TAG_CONSOLE_EHCI 5 + /* The following structures are for the cmos definitions table */ #define LB_TAG_CMOS_OPTION_TABLE 200 /* cmos header record */ Index: arch/x86/coreboot_table.c =================================================================== --- arch/x86/coreboot_table.c (revision 690) +++ arch/x86/coreboot_table.c (working copy) @@ -25,6 +25,7 @@ #include <device/device.h> #include <tables.h> #include <mc146818rtc.h> +#include <uart8250.h> #include <lib.h> //#include <cpu/cpu.h> //#include <pirq_routing.h> @@ -98,6 +99,45 @@ return mem; } +struct lb_serial *lb_serial(struct lb_header *header) +{ +#if defined(TTYSx_BASE) + struct lb_record *rec; + struct lb_serial *serial; + rec = lb_new_record(header); + serial = (struct lb_serial *)rec; + serial->tag = LB_TAG_SERIAL; + serial->size = sizeof(*serial); + serial->ioport = TTYSx_BASE; + serial->baud = TTYSx_BAUD; + return serial; +#else + return header; +#endif +} + +void add_console(struct lb_header *header, u16 consoletype) +{ + struct lb_record *rec; + struct lb_console *console; + rec = lb_new_record(header); + console = (struct lb_console *)lb_new_record(header); + console->tag = LB_TAG_CONSOLE; + console->size = sizeof(*console); + console->type = consoletype; +} + +void lb_console(struct lb_header *header) +{ +#ifdef CONFIG_CONSOLE_SERIAL + add_console(header, LB_TAG_CONSOLE_SERIAL8250); +#endif +/* FIXME when we have a proper vga console ourself */ +#ifdef CONFIG_PCI_OPTION_ROM_RUN + add_console(header, LB_TAG_CONSOLE_VGA); +#endif +} + struct lb_mainboard *lb_mainboard(struct lb_header *header) { struct lb_record *rec; @@ -454,6 +494,12 @@ /* Record our motherboard */ lb_mainboard(head); + /* Record the serial port, if present */ + lb_serial(head); + + /* Record our console setup */ + lb_console(head); + /* Record our various random string information */ lb_strings(head);

2 2

r691 - in coreboot-v3: arch/x86 include
by svn＠coreboot.org 29 Jun '08

29 Jun '08

Author: oxygene Date: 2008-06-29 08:43:01 +0200 (Sun, 29 Jun 2008) New Revision: 691 Modified: coreboot-v3/arch/x86/coreboot_table.c coreboot-v3/include/tables.h Log: Implements console and serial lbtable records compatible to cbv2 as of r3396 Signed-Off-By: Patrick Georgi <patrick(a)georgi-clan.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: coreboot-v3/arch/x86/coreboot_table.c =================================================================== --- coreboot-v3/arch/x86/coreboot_table.c 2008-06-06 20:47:42 UTC (rev 690) +++ coreboot-v3/arch/x86/coreboot_table.c 2008-06-29 06:43:01 UTC (rev 691) @@ -25,6 +25,7 @@ #include <device/device.h> #include <tables.h> #include <mc146818rtc.h> +#include <uart8250.h> #include <lib.h> //#include <cpu/cpu.h> //#include <pirq_routing.h> @@ -98,6 +99,45 @@ return mem; } +struct lb_serial *lb_serial(struct lb_header *header) +{ +#if defined(TTYSx_BASE) + struct lb_record *rec; + struct lb_serial *serial; + rec = lb_new_record(header); + serial = (struct lb_serial *)rec; + serial->tag = LB_TAG_SERIAL; + serial->size = sizeof(*serial); + serial->ioport = TTYSx_BASE; + serial->baud = TTYSx_BAUD; + return serial; +#else + return header; +#endif +} + +void add_console(struct lb_header *header, u16 consoletype) +{ + struct lb_record *rec; + struct lb_console *console; + rec = lb_new_record(header); + console = (struct lb_console *)lb_new_record(header); + console->tag = LB_TAG_CONSOLE; + console->size = sizeof(*console); + console->type = consoletype; +} + +void lb_console(struct lb_header *header) +{ +#ifdef CONFIG_CONSOLE_SERIAL + add_console(header, LB_TAG_CONSOLE_SERIAL8250); +#endif +/* FIXME when we have a proper vga console ourself */ +#ifdef CONFIG_PCI_OPTION_ROM_RUN + add_console(header, LB_TAG_CONSOLE_VGA); +#endif +} + struct lb_mainboard *lb_mainboard(struct lb_header *header) { struct lb_record *rec; @@ -454,6 +494,12 @@ /* Record our motherboard */ lb_mainboard(head); + /* Record the serial port, if present */ + lb_serial(head); + + /* Record our console setup */ + lb_console(head); + /* Record our various random string information */ lb_strings(head); Modified: coreboot-v3/include/tables.h =================================================================== --- coreboot-v3/include/tables.h 2008-06-06 20:47:42 UTC (rev 690) +++ coreboot-v3/include/tables.h 2008-06-29 06:43:01 UTC (rev 691) @@ -175,6 +175,28 @@ u32 dev_root_ptr; /* Pointer to the root device */ }; +#define LB_TAG_SERIAL 0x000f +struct lb_serial { + u32 tag; + u32 size; + u16 ioport; + u32 baud; +}; + +#define LB_TAG_CONSOLE 0x0010 +struct lb_console { + u32 tag; + u32 size; + u16 type; +}; + +#define LB_TAG_CONSOLE_SERIAL8250 0 +#define LB_TAG_CONSOLE_VGA 1 +#define LB_TAG_CONSOLE_BTEXT 2 +#define LB_TAG_CONSOLE_LOGBUF 3 +#define LB_TAG_CONSOLE_SROM 4 +#define LB_TAG_CONSOLE_EHCI 5 + /* The following structures are for the cmos definitions table */ #define LB_TAG_CMOS_OPTION_TABLE 200 /* cmos header record */

1 0

r3396 - in trunk/coreboot-v2/src: arch/i386/boot include/boot
by svn＠coreboot.org 29 Jun '08

29 Jun '08

Author: oxygene Date: 2008-06-29 08:41:12 +0200 (Sun, 29 Jun 2008) New Revision: 3396 Modified: trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c trunk/coreboot-v2/src/include/boot/coreboot_tables.h Log: Adds a field to the serial port descriptor about the configured line speed. Signed-Off-By: Patrick Georgi <patrick(a)georgi-clan.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c 2008-06-29 01:30:41 UTC (rev 3395) +++ trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c 2008-06-29 06:41:12 UTC (rev 3396) @@ -84,6 +84,7 @@ serial->tag = LB_TAG_SERIAL; serial->size = sizeof(*serial); serial->ioport = TTYS0_BASE; + serial->baud = TTYS0_BAUD; return serial; #else return header; Modified: trunk/coreboot-v2/src/include/boot/coreboot_tables.h =================================================================== --- trunk/coreboot-v2/src/include/boot/coreboot_tables.h 2008-06-29 01:30:41 UTC (rev 3395) +++ trunk/coreboot-v2/src/include/boot/coreboot_tables.h 2008-06-29 06:41:12 UTC (rev 3396) @@ -145,6 +145,7 @@ uint32_t tag; uint32_t size; uint16_t ioport; + uint32_t baud; }; #define LB_TAG_CONSOLE 0x0010

1 0

r3395 - trunk/util/flashrom
by svn＠coreboot.org 29 Jun '08

29 Jun '08

Author: stuge Date: 2008-06-29 03:30:41 +0200 (Sun, 29 Jun 2008) New Revision: 3395 Modified: trunk/util/flashrom/chipset_enable.c trunk/util/flashrom/ichspi.c Log: flashrom: Fix ICH7 non-SPI that broke in r3393 r3393 assumed that ICH7 always used SPI. This patch resets ich7_detected back to 0 when BOOT BIOS Straps indicate something else than SPI. Also fixes a build error in ichspi.c with gcc 4.2.2. Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/util/flashrom/chipset_enable.c =================================================================== --- trunk/util/flashrom/chipset_enable.c 2008-06-28 23:02:22 UTC (rev 3394) +++ trunk/util/flashrom/chipset_enable.c 2008-06-29 01:30:41 UTC (rev 3395) @@ -212,6 +212,8 @@ bbs = (gcs >> 10) & 0x3; printf_debug("BOOT BIOS Straps: 0x%x (%s)\n", bbs, (bbs == 0x3) ? "LPC" : ((bbs == 0x2) ? "PCI" : "SPI")); + if (bbs >= 2) + ich7_detected = 0; buc = *(volatile uint8_t *)(rcrb + 0x3414); printf_debug("Top Swap : %s\n", (buc & 1)?"enabled (A16 inverted)":"not enabled"); Modified: trunk/util/flashrom/ichspi.c =================================================================== --- trunk/util/flashrom/ichspi.c 2008-06-28 23:02:22 UTC (rev 3394) +++ trunk/util/flashrom/ichspi.c 2008-06-29 01:30:41 UTC (rev 3395) @@ -229,7 +229,7 @@ { int write_cmd = 0; int timeout; - uint32_t temp32; + uint32_t temp32 = 0; uint16_t temp16; uint32_t a;

1 0

[PATCH] flashrom: Use symbolic constants for PCI subsystem probing
by Carl-Daniel Hailfinger 29 Jun '08

29 Jun '08

Use symbolic constants for PCI subsystem probing in flashrom. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom.c =================================================================== --- flashrom.c (Revision 3393) +++ flashrom.c (Arbeitskopie) @@ -74,8 +74,8 @@ for (temp = pacc->devices; temp; temp = temp->next) if (pci_filter_match(&filter, temp)) { - if ((card_vendor == pci_read_word(temp, 0x2C)) && - (card_device == pci_read_word(temp, 0x2E))) + if ((card_vendor == pci_read_word(temp, PCI_SUBSYSTEM_VENDOR_ID)) && + (card_device == pci_read_word(temp, PCI_SUBSYSTEM_ID))) return temp; } -- http://www.hailfinger.org/

2 2

r3394 - trunk/util/flashrom
by svn＠coreboot.org 29 Jun '08

29 Jun '08

Author: hailfinger Date: 2008-06-29 01:02:22 +0200 (Sun, 29 Jun 2008) New Revision: 3394 Modified: trunk/util/flashrom/flashrom.c Log: Use symbolic constants for PCI subsystem probing in flashrom. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/util/flashrom/flashrom.c =================================================================== --- trunk/util/flashrom/flashrom.c 2008-06-27 16:28:34 UTC (rev 3393) +++ trunk/util/flashrom/flashrom.c 2008-06-28 23:02:22 UTC (rev 3394) @@ -74,8 +74,8 @@ for (temp = pacc->devices; temp; temp = temp->next) if (pci_filter_match(&filter, temp)) { - if ((card_vendor == pci_read_word(temp, 0x2C)) && - (card_device == pci_read_word(temp, 0x2E))) + if ((card_vendor == pci_read_word(temp, PCI_SUBSYSTEM_VENDOR_ID)) && + (card_device == pci_read_word(temp, PCI_SUBSYSTEM_ID))) return temp; }

1 0

[PATCH][v3] read actual memory size in qemu-i386
by Patrick Georgi 29 Jun '08

29 Jun '08

Hi, attached is an update to my patch from 2008-06-05. The only change so far was a clean up in copyright statements, the other two pending issues were: 1. What to do with doc/design/newboot.lyx, which refers to a value I delete (ramsize), but which I can't edit without lyx (on win32) 2. Where to put inb_cmos, which so far is only used in nvramtool, a userspace app. Regards, Patrick Georgi Signed-Off-By: Patrick Georgi <patrick(a)georgi-clan.de> Index: northbridge/intel/i440bxemulation/domain =================================================================== --- northbridge/intel/i440bxemulation/domain (revision 690) +++ northbridge/intel/i440bxemulation/domain (working copy) @@ -19,6 +19,5 @@ */ { - ramsize = "128"; device_operations = "i440bx_domain"; }; Index: northbridge/intel/i440bxemulation/i440bx.c =================================================================== --- northbridge/intel/i440bxemulation/i440bx.c (revision 690) +++ northbridge/intel/i440bxemulation/i440bx.c (working copy) @@ -3,6 +3,7 @@ * * Copyright (C) 2000 Ron Minnich, Advanced Computing Lab, LANL * Copyright (C) 2007 Ronald G. Minnich <rminnich(a)gmail.com> + * Copyright (C) 2008 Patrick Georgi <patrick(a)georgi-clan.de> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -43,19 +44,30 @@ #include <device/device.h> #include <device/pci.h> #include <string.h> +#include <io.h> #include "i440bx.h" #include "statictree.h" /* Here are the ops for 440BX as a PCI domain. */ +static int inb_cmos(int port) +{ + outb(port, 0x70); + return inb(0x71); +} + static void pci_domain_set_resources(struct device *dev) { struct device *mc_dev; u32 tolmk; /* Top of low mem, Kbytes. */ int idx; - struct northbridge_intel_i440bxemulation_domain_config *device_configuration = - dev->device_configuration; - tolmk = device_configuration->ramsize * 1024; + /* read large mem memory descriptor + for <16 MB read the more detailed small mem descriptor + all values in kbytes */ + tolmk = ((inb_cmos(0x35)<<8) |inb_cmos(0x34)) * 64; + if (tolmk <= 16 * 1024) { + tolmk = (inb_cmos(0x31)<<8) |inb_cmos(0x30); + } mc_dev = dev->link[0].children; if (mc_dev) { idx = 10;

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coreboot June 2008