by Rudolf Marek
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
Hi all,
Today I managed to boot kernel and userspace on the Asus M2V-MX SE
(K8M890 VT8237S AMD am2 socket + SPI flash in socket)
What works:
1) IDE
2) serial line
3) USB
4) APCI poweroff with halt command + some basic ACPI powerbutton event
5) APICs are routing irqs
I will test more stuff later.
Known issues:
1) slow boot, perhaps SPI timming is too low
2) cpu freq change does not work
3) sata seems not to work
4) PCI IRQ routing does not work for external cards
5) v-link set to 8 bit (default)
Attached patch is mine WIP state of the tree.
Rudolf
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by Carl-Daniel Hailfinger
Convert stage2 and initram makefile rules from object to source files.
This creates a clearer distinction between source files in the source
tree we want to have compiled and indirectly created object/source files
in the object tree.
It also will make enable us to move to whole-program
optimization/compilation which should yield substantial size savings.
Then again, we may be able to do that without the makefile conversion as
well.
This is a RFC, not to be applied immediately.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net>
Index: LinuxBIOSv3-makefilerewrite/southbridge/amd/cs5536/Makefile
===================================================================
--- LinuxBIOSv3-makefilerewrite/southbridge/amd/cs5536/Makefile (Revision 626)
+++ LinuxBIOSv3-makefilerewrite/southbridge/amd/cs5536/Makefile (Arbeitskopie)
@@ -21,7 +21,7 @@
ifeq ($(CONFIG_SOUTHBRIDGE_AMD_CS5536),y)
-STAGE2_CHIPSET_OBJ += $(obj)/southbridge/amd/cs5536/cs5536.o
+STAGE2_CHIPSET_SRC += $(src)/southbridge/amd/cs5536/cs5536.c
STAGE0_CHIPSET_OBJ += $(obj)/southbridge/amd/cs5536/stage1.o
Index: LinuxBIOSv3-makefilerewrite/southbridge/intel/i82371eb/Makefile
===================================================================
--- LinuxBIOSv3-makefilerewrite/southbridge/intel/i82371eb/Makefile (Revision 626)
+++ LinuxBIOSv3-makefilerewrite/southbridge/intel/i82371eb/Makefile (Arbeitskopie)
@@ -20,6 +20,6 @@
ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82371EB),y)
-STAGE2_CHIPSET_OBJ += $(obj)/southbridge/intel/i82371eb/i82371eb.o
+STAGE2_CHIPSET_SRC += $(src)/southbridge/intel/i82371eb/i82371eb.c
endif
Index: LinuxBIOSv3-makefilerewrite/superio/winbond/w83627hf/Makefile
===================================================================
--- LinuxBIOSv3-makefilerewrite/superio/winbond/w83627hf/Makefile (Revision 626)
+++ LinuxBIOSv3-makefilerewrite/superio/winbond/w83627hf/Makefile (Arbeitskopie)
@@ -25,6 +25,6 @@
STAGE0_CHIPSET_OBJ += $(obj)/device/pnp_raw.o
# Always add to variables, as there could be more than one Super I/O.
-STAGE2_CHIPSET_OBJ += $(obj)/superio/winbond/w83627hf/superio.o
+STAGE2_CHIPSET_SRC += $(src)/superio/winbond/w83627hf/superio.c
endif
Index: LinuxBIOSv3-makefilerewrite/superio/fintek/f71805f/Makefile
===================================================================
--- LinuxBIOSv3-makefilerewrite/superio/fintek/f71805f/Makefile (Revision 626)
+++ LinuxBIOSv3-makefilerewrite/superio/fintek/f71805f/Makefile (Arbeitskopie)
@@ -24,6 +24,6 @@
STAGE0_CHIPSET_OBJ += $(obj)/device/pnp_raw.o
# Always add to variables, as there could be more than one Super I/O.
-STAGE2_CHIPSET_OBJ += $(obj)/superio/fintek/f71805f/superio.o
+STAGE2_CHIPSET_SRC += $(src)/superio/fintek/f71805f/superio.c
endif
Index: LinuxBIOSv3-makefilerewrite/mainboard/adl/msm800sev/Makefile
===================================================================
--- LinuxBIOSv3-makefilerewrite/mainboard/adl/msm800sev/Makefile (Revision 626)
+++ LinuxBIOSv3-makefilerewrite/mainboard/adl/msm800sev/Makefile (Arbeitskopie)
@@ -21,12 +21,12 @@
STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
-INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
+INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
$(src)/northbridge/amd/geodelx/raminit.c \
$(src)/southbridge/amd/cs5536/smbus_initram.c \
$(src)/arch/x86/geodelx/geodelx.c
-STAGE2_MAINBOARD_OBJ =
+STAGE2_MAINBOARD_SRC =
$(obj)/coreboot.vpd:
$(Q)printf " BUILD DUMMY VPD\n"
Index: LinuxBIOSv3-makefilerewrite/mainboard/amd/norwich/Makefile
===================================================================
--- LinuxBIOSv3-makefilerewrite/mainboard/amd/norwich/Makefile (Revision 626)
+++ LinuxBIOSv3-makefilerewrite/mainboard/amd/norwich/Makefile (Arbeitskopie)
@@ -21,12 +21,12 @@
STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
-INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
+INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
$(src)/northbridge/amd/geodelx/raminit.c \
$(src)/southbridge/amd/cs5536/smbus_initram.c \
$(src)/arch/x86/geodelx/geodelx.c
-STAGE2_MAINBOARD_OBJ = irq_tables.o
+STAGE2_MAINBOARD_SRC = irq_tables.c
$(obj)/coreboot.vpd:
$(Q)printf " BUILD DUMMY VPD\n"
Index: LinuxBIOSv3-makefilerewrite/mainboard/artecgroup/dbe61/Makefile
===================================================================
--- LinuxBIOSv3-makefilerewrite/mainboard/artecgroup/dbe61/Makefile (Revision 626)
+++ LinuxBIOSv3-makefilerewrite/mainboard/artecgroup/dbe61/Makefile (Arbeitskopie)
@@ -21,11 +21,11 @@
STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
-INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
+INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
$(src)/northbridge/amd/geodelx/raminit.c \
$(src)/arch/x86/geodelx/geodelx.c
-STAGE2_MAINBOARD_OBJ =
+STAGE2_MAINBOARD_SRC =
$(obj)/coreboot.vpd:
$(Q)printf " BUILD DUMMY VPD\n"
Index: LinuxBIOSv3-makefilerewrite/mainboard/artecgroup/dbe62/Makefile
===================================================================
--- LinuxBIOSv3-makefilerewrite/mainboard/artecgroup/dbe62/Makefile (Revision 626)
+++ LinuxBIOSv3-makefilerewrite/mainboard/artecgroup/dbe62/Makefile (Arbeitskopie)
@@ -21,11 +21,11 @@
STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
-INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
+INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
$(src)/northbridge/amd/geodelx/raminit.c \
$(src)/arch/x86/geodelx/geodelx.c
-STAGE2_MAINBOARD_OBJ = irq_tables.o
+STAGE2_MAINBOARD_SRC = irq_tables.c
$(obj)/coreboot.vpd:
$(Q)printf " BUILD DUMMY VPD\n"
Index: LinuxBIOSv3-makefilerewrite/mainboard/pcengines/alix1c/Makefile
===================================================================
--- LinuxBIOSv3-makefilerewrite/mainboard/pcengines/alix1c/Makefile (Revision 626)
+++ LinuxBIOSv3-makefilerewrite/mainboard/pcengines/alix1c/Makefile (Arbeitskopie)
@@ -21,11 +21,11 @@
STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
-INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
+INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
$(src)/northbridge/amd/geodelx/raminit.c \
$(src)/arch/x86/geodelx/geodelx.c
-STAGE2_MAINBOARD_OBJ = irq_tables.o
+STAGE2_MAINBOARD_SRC = irq_tables.c
$(obj)/coreboot.vpd:
$(Q)printf " BUILD DUMMY VPD\n"
Index: LinuxBIOSv3-makefilerewrite/mainboard/emulation/qemu-x86/Makefile
===================================================================
--- LinuxBIOSv3-makefilerewrite/mainboard/emulation/qemu-x86/Makefile (Revision 626)
+++ LinuxBIOSv3-makefilerewrite/mainboard/emulation/qemu-x86/Makefile (Arbeitskopie)
@@ -28,10 +28,10 @@
# directory and is built from what was auto.c in v2.
#
-INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
+INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
$(src)/mainboard/$(MAINBOARDDIR)/initram_printktest.c
-STAGE2_MAINBOARD_OBJ = vga.o
+STAGE2_MAINBOARD_SRC = vga.c
#
# VPD or SIP ROM or... how does NVIDIA call it?
Index: LinuxBIOSv3-makefilerewrite/device/Makefile
===================================================================
--- LinuxBIOSv3-makefilerewrite/device/Makefile (Revision 626)
+++ LinuxBIOSv3-makefilerewrite/device/Makefile (Arbeitskopie)
@@ -24,6 +24,6 @@
$(Q)printf " CC $(subst $(shell pwd)/,,$(@))\n"
$(Q)$(CC) $(INITCFLAGS) -c $< -o $@
-STAGE2_DEVICE_OBJ = device.o device_util.o root_device.o \
- pci_device.o pci_ops.o pci_rom.o pnp_device.o pnp_raw.o
+STAGE2_DEVICE_SRC = device.c device_util.c root_device.c \
+ pci_device.c pci_ops.c pci_rom.c pnp_device.c pnp_raw.c
Index: LinuxBIOSv3-makefilerewrite/northbridge/amd/geodelx/Makefile
===================================================================
--- LinuxBIOSv3-makefilerewrite/northbridge/amd/geodelx/Makefile (Revision 626)
+++ LinuxBIOSv3-makefilerewrite/northbridge/amd/geodelx/Makefile (Arbeitskopie)
@@ -21,9 +21,9 @@
ifeq ($(CONFIG_NORTHBRIDGE_AMD_GEODELX),y)
-STAGE2_CHIPSET_OBJ += $(obj)/northbridge/amd/geodelx/geodelx.o \
- $(obj)/northbridge/amd/geodelx/vsmsetup.o \
- $(obj)/util/x86emu/vm86_gdt.o \
- $(obj)/northbridge/amd/geodelx/grphinit.o
+STAGE2_CHIPSET_SRC += $(src)/northbridge/amd/geodelx/geodelx.c \
+ $(src)/northbridge/amd/geodelx/vsmsetup.c \
+ $(src)/util/x86emu/vm86_gdt.c \
+ $(src)/northbridge/amd/geodelx/grphinit.c
endif
Index: LinuxBIOSv3-makefilerewrite/northbridge/intel/i440bxemulation/Makefile
===================================================================
--- LinuxBIOSv3-makefilerewrite/northbridge/intel/i440bxemulation/Makefile (Revision 626)
+++ LinuxBIOSv3-makefilerewrite/northbridge/intel/i440bxemulation/Makefile (Arbeitskopie)
@@ -21,6 +21,6 @@
ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I440BXEMULATION),y)
-STAGE2_CHIPSET_OBJ += $(obj)/northbridge/intel/i440bxemulation/i440bx.o
+STAGE2_CHIPSET_SRC += $(src)/northbridge/intel/i440bxemulation/i440bx.c
endif
Index: LinuxBIOSv3-makefilerewrite/arch/x86/Makefile
===================================================================
--- LinuxBIOSv3-makefilerewrite/arch/x86/Makefile (Revision 626)
+++ LinuxBIOSv3-makefilerewrite/arch/x86/Makefile (Arbeitskopie)
@@ -179,27 +179,32 @@
# TODO: This should be compressed with the default compressor.
#
-STAGE2_LIB_OBJ = stage2.o clog2.o mem.o tables.o delay.o \
- compute_ip_checksum.o string.o
+STAGE2_LIB_SRC = stage2.c clog2.c mem.c tables.c delay.c \
+ compute_ip_checksum.c string.c
-STAGE2_ARCH_X86_OBJ = archtables.o coreboot_table.o udelay_io.o
-STAGE2_ARCH_X86_OBJ += pci_ops_auto.o pci_ops_conf1.o pci_ops_conf2.o
-STAGE2_ARCH_X86_OBJ += keyboard.o i8259.o isa-dma.o
+STAGE2_ARCH_X86_SRC = archtables.c coreboot_table.c udelay_io.c
+STAGE2_ARCH_X86_SRC += pci_ops_auto.c pci_ops_conf1.c pci_ops_conf2.c
+STAGE2_ARCH_X86_SRC += keyboard.c i8259.c isa-dma.c
ifeq ($(CONFIG_PIRQ_TABLE),y)
-STAGE2_ARCH_X86_OBJ += pirq_routing.o
+STAGE2_ARCH_X86_SRC += pirq_routing.c
endif
STAGE2_DYNAMIC_OBJ = statictree.o
-STAGE2_OBJ := $(patsubst %,$(obj)/lib/%,$(STAGE2_LIB_OBJ)) \
- $(patsubst %,$(obj)/arch/x86/%,$(STAGE2_ARCH_X86_OBJ)) \
- $(patsubst %,$(obj)/device/%,$(STAGE2_DEVICE_OBJ)) \
- $(patsubst %,$(obj)/mainboard/$(MAINBOARDDIR)/%,$(STAGE2_MAINBOARD_OBJ)) \
- $(patsubst %,$(obj)/mainboard/$(MAINBOARDDIR)/%,$(STAGE2_DYNAMIC_OBJ))
+STAGE2_SRC := $(patsubst %,$(src)/lib/%,$(STAGE2_LIB_SRC)) \
+ $(patsubst %,$(src)/arch/x86/%,$(STAGE2_ARCH_X86_SRC)) \
+ $(patsubst %,$(src)/device/%,$(STAGE2_DEVICE_SRC)) \
+ $(patsubst %,$(src)/mainboard/$(MAINBOARDDIR)/%,$(STAGE2_MAINBOARD_SRC))
-STAGE2_OBJ += $(STAGE2_CHIPSET_OBJ)
+STAGE2_SRC += $(STAGE2_CHIPSET_SRC)
+STAGE2_OBJ := $(patsubst $(src)/%.c,$(obj)/%.o,$(STAGE2_SRC))
+
+# This one is special, but only due to slightly incorrect rules and dependencies.
+# Don't change the dependencies for now.
+STAGE2_OBJ += $(patsubst %,$(obj)/mainboard/$(MAINBOARDDIR)/%,$(STAGE2_DYNAMIC_OBJ))
+
ifeq ($(CONFIG_PCI_OPTION_ROM_RUN),y)
ifeq ($(CONFIG_PCI_OPTION_ROM_RUN_X86EMU),y)
# x86emu wants libgcc
@@ -215,7 +220,7 @@
STAGE2_OBJ_NEEDED = $(filter-out $(STAGE0_OBJ), $(STAGE2_OBJ))
-$(obj)/coreboot.stage2 $(obj)/coreboot.stage2.map: $(obj)/stage0.o $(STAGE2_OBJ_NEEDED)
+$(obj)/coreboot.stage2 $(obj)/coreboot.stage2.map: $(obj)/stage0.o $(STAGE2_OBJ_NEEDED) $(STAGE2_SRC)
$(Q)# leave a .o with full symbols in it for debugging.
$(Q)printf " LD $(subst $(shell pwd)/,,$(@))\n"
$(Q)$(LD) -R $(obj)/stage0.o -Ttext 0x2000 --entry=stage2 \
@@ -249,9 +254,9 @@
$(Q)printf " AS $(subst $(shell pwd)/,,$(@))\n"
$(Q)$(AS) $(obj)/arch/x86/stage0_asm.s -o $@
-$(obj)/coreboot.initram $(obj)/coreboot.initram.map: $(obj)/stage0.init $(obj)/stage0-prefixed.o $(INITRAM_OBJ)
+$(obj)/coreboot.initram $(obj)/coreboot.initram.map: $(obj)/stage0.init $(obj)/stage0-prefixed.o $(INITRAM_SRC)
$(Q)printf " CC $(subst $(shell pwd)/,,$(@)) (XIP)\n"
- $(Q)$(CC) $(INITCFLAGS) -D_SHARED -fPIE -c -combine $(INITRAM_OBJ) -o $(obj)/coreboot.initram_partiallylinked.o
+ $(Q)$(CC) $(INITCFLAGS) -D_SHARED -fPIE -c -combine $(INITRAM_SRC) -o $(obj)/coreboot.initram_partiallylinked.o
$(Q)# initram links against stage0
$(Q)printf " LD $(subst $(shell pwd)/,,$(@))\n"
$(Q)$(LD) -Ttext 0 --entry main -N -R $(obj)/stage0-prefixed.o \
--
http://www.hailfinger.org/
by Peter Stuge
The board can be modified in two ways. One is simpler and less
reliable, the other is more complex but much more robust.
Materials needed:
1x SO-8 SPI flash chip, ideally 200mil but 150mil can work too
Spansion S25FL016A is easy to get. Macronix has the 32Mbit MX25L3205.
2x 0402 100k chip resistors
1x SPTD (Single Pole Dual Throw) switch and three wires
For the better modification, you also need:
2x 0402 4k7 chip resistors (1k is OK too, 10k does not work!)
2x 0603 100k chip resistors
2x SOT-23 BC847C transistors
See http://stuge.se/m57sli/m57sli_soic_detail_labels.jpg for reference.
Common steps always needed:
1. U9: Populate flash chip
2. R509: Remove
3. R89,R130: Populate 0402 100k resistors
Simple:
NOTE: Keep wires to the switch short! Only a few centimeters/one inch.
4. Solder center contact on switch to Q4-3 or Q5-3. Either is OK.
5. Solder one side contact on switch to Q4-1.
6. Solder other side contact on switch to Q5-1.
7. DONE!
Better:
NOTE: Switch wires can be rather long. Several meters has been tested.
4. R90,R91: Populate 0402 4k7 resistors
5. R86,R389: Populate 0603 100k resistors
6. Q4,Q5: Populate SOT-23 BC847C transistors
7. Solder center contact on switch to VCC, e.g. at BC54-2.
8. Solder one side contact on switch to R86-2.
9. Solder other side contact on switch to R389-2.
10. DONE!
I am happy to sell boards pre-modified with the better modification.
Unfortunately I cannot offer these boards to consumers in all EU
member states because of EU environmental regulations, but many are
OK.
//Peter
by Ken.Fuchs＠bench.com
Embedded controllers are being put on mainboards to
add functionality that the chipset and other support
chips can't easily provide. The most common application
is keyboard handling on laptops. Another example is
the embedded controllers added to servers for various
management features. Embedded controllers seem to be
showing up now for many Intel PC board designs for
such things as power management and LPC to SPI
interfacing to support SPI NOR flash booting of the
BIOS/firmware.
I'm looking for an open source micro-controller project
that could be adapted to for use on PC embedded controllers
as described above.
What happened with the OLPC's OpenEC code? Was that
ever completed? Did the name change to something else?
Is it currently being developed?
Is there a viable alternative to OpenEC for embedded
controller code? Will it work with coreboot or
appropriate payloads?
Any comments regarding coreboot and embedded controllers?
Sincerely,
Ken Fuchs
by Tom Sylla
Add dump support for Winbond (NSC) PC87427. Dumps available from real hardware.
Signed-off-by: Tom Sylla <tsylla(a)gmail.com>
Index: nsc.c
===================================================================
--- nsc.c (revision 3358)
+++ nsc.c (working copy)
@@ -408,6 +408,65 @@
{EOT}}},
{0xf2, "PC87427", {
/* SRID[7..5] is marked as "not applicable for the PC87427". */
+ {NOLDN, NULL,
+ {0x10,0x12,0x13,0x1d,0x20,0x21,0x22,0x23,0x24,0x25,
+ 0x26,0x27,0x28,0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,
+ EOT},
+ {0x00,0x00,0x00,0x00,0xf2,0x11,0xa0,MISC,MISC,MISC,
+ 0x02,NANA,0x00,MISC,0x00,0x00,MISC,MISC,RSVD,RSVD,
+ EOT}},
+ {0x0, "Floppy",
+ {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,0xf1,EOT},
+ {0x00,0x03,0xf2,0x06,0x03,0x02,0x04,0x24,0x00,EOT}},
+ {0x2, "COM2",
+ {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT},
+ {0x00,0x02,0xf8,0x03,0x03,0x04,0x04,0x02,EOT}},
+ {0x3, "COM1",
+ {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT},
+ {0x00,0x03,0xf8,0x04,0x03,0x04,0x04,0x02,EOT}},
+ {0x4, "System wake-up control (SWC)",
+ {0x30,0x60,0x61,0x62,0x63,0x64,0x65,0x66,0x67,0x70,
+ 0x71,0x74,0x75,EOT},
+ {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x03,0x04,0x04,EOT}},
+ {0x5, "Mouse",
+ {0x30,0x70,0x71,0x74,0x75,EOT},
+ {0x00,0x0c,0x02,0x04,0x04,EOT}},
+ {0x6, "Keyboard",
+ {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0x74,0x75,0xf0,
+ EOT},
+ {0x00,0x00,0x60,0x00,0x64,0x01,0x02,0x04,0x04,0x40,
+ EOT}},
+ {0x7, "GPIO",
+ {0x30,0x50,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,0xf1,
+ 0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,EOT},
+ {0x00,0x00,0x00,0x00,0x00,0x03,0x04,0x04,0x00,MISC,
+ 0x01,0x00,0x00,0x00,0x00,0x00,0x00,EOT}},
+ {0x9, "Fan Monitor and Control (FMC)",
+ {0x30,0x50,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,0xf1,
+ EOT},
+ {0x00,0x00,0x00,0x00,0x00,0x03,0x04,0x04,0x19,0x06,
+ EOT}},
+ {0xa, "Watchdog timer (WDT)",
+ {0x30,0x50,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT},
+ {0x00,0x00,0x00,0x00,0x00,0x03,0x04,0x04,0x00,EOT}},
+ {0xf, "X-Bus",
+ {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,0xf1,0xf2,
+ 0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xfb,0xfc,
+ 0xfd,0xfe,0xff,EOT},
+ {0x00,0x00,0x00,0x00,0x00,0x04,0x04,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x00,0x80,0x10,EOT}},
+ {0x10, "Real-time clock (RTC)",
+ {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0x74,0x75,0xf0,
+ 0xf1,0xf2,0xf3,0xf6,0xf7,EOT},
+ {0x00,0x00,0x70,0x00,0x72,0x08,0x00,0x04,0x04,0x00,
+ 0x00,0x00,0x00,MISC,0x00,EOT}},
+ {0x14, "Health Monitoring and Control (HMC)",
+ {0x30,0x50,0x60,0x61,0x62,0x63,0x70,0x71,0x74,0x75,
+ 0xf0,EOT},
+ {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x04,0x04,
+ 0x05,EOT}},
{EOT}}},
{0xf3, "PC87373", {
{EOT}}},
Index: superiotool.h
===================================================================
--- superiotool.h (revision 3358)
+++ superiotool.h (working copy)
@@ -51,7 +51,7 @@
#define NANA -3 /* Not Available */
#define RSVD -4 /* Reserved */
#define MISC -5 /* Needs special comment in output */
-#define MAXLDN 0x10 /* Biggest LDN */
+#define MAXLDN 0x14 /* Biggest LDN */
#define LDNSIZE (MAXLDN + 3) /* Biggest LDN + 0 + NOLDN + EOT */
#define MAXNUMIDX 170 /* Maximum number of indexes */
#define IDXSIZE (MAXNUMIDX + 1)
by Carl-Daniel Hailfinger
Hi,
I'm not officially back yet, but here's a question I don't want to forget:
Are there any easily available USB debug cables? The NET20DC is very
difficult to get in Europe.
Can I emulate such a cable with the Geode USB target mode?
Regards,
Carl-Daniel
by Zhang Rui
Hello,
LegacyBIOS could be added to coreboot.rom by lar tool now. I modified
the Makefile in arch/x86
I am now a little lost in x86emu of coreboot v3. And I have some
questions. Please help me.
1. What is the address of post() in LegacyBIOS?
>> and then how can we call the post() function?
>
> Well, that will require some work. :-) Take a look at how the build
> exports the assembler stub "post32" (in post.c) - which calls _start()
> (also in post.c).
>
asm(
".global post32\n"
"post32:\n"
"cli\n"
"cld\n"
"lidtl " __stringify(0xf0000 | OFFSET_pmode_IDT_info) "\n"
"lgdtl " __stringify(0xf0000 | OFFSET_rombios32_gdt_48) "\n"
"movl $" __stringify(BUILD_STACK_ADDR) ", %esp\n"
"ljmp $0x10, $_start\n"
);
According to these asm codes, we should load the idt and gdt and set
the stack point esp before we jump to the start() function. But these
codes are in LegacyBIOS, so "_start" can be used to present the
address of start(). How can I call post outside LegacyBIOS but just
use the bios.bin file(copied to 0xf0000)? Can this function have a
fixed address? or is there another approach?
2. How to modify the post() method in LegacyBIOS?
post() will auto boot the system at the end. But we want it return to
coreboot. So what is the boot code at the end of the function? Is
this?
init_boot_vectors();
dprintf(1, "Scan for option roms\n");
rom_scan(0xc8000, 0xe0000);
May be we could write another funcion post_noboot() without the boot
code and have a fixed address?
3. How to get the address of idt of LegacyBIOS?
"lidtl " __stringify(0xf0000 | OFFSET_pmode_IDT_info) "\n"
"lgdtl " __stringify(0xf0000 | OFFSET_rombios32_gdt_48) "\n"
"movl $" __stringify(BUILD_STACK_ADDR) ", %esp\n"
I noticed that OFFSET_pmode_IDT_info is defined in
rom16.offset.auto.h. But this header file is generated in building
process and I do not find the rule for it in the Makefile. So I want
to know how can I get the value of OFFSET_pmode_IDT_info? So do
OFFSET_rombios32_gdt_48 and BUILD_STACK_ADDR.
Kevin, could you help me with these three questions? Thanks.
4. Where is the entrance call of util/x86emu in coreboot v3?
There are several x86EMU_XXX function exported in e86emu.h. But they
are called only in run_bios() in biosemu.c. I placed a printk at the
beginning of run_bios() but it seems not executed. How does the codes
in util/x86emu used?
Where is the entrance call of util/x86emu in coreboot v3? Where should
I place the code to extract LegacyBIOS to the memory? Should I write a
new function and export it?
Stefan, could you help me with this question? Thanks.
Best regards.
Zhang Rui
by Hannes Hegewald
hey, here's the 'lspci -tvnn', 'superiotool -dV', 'flashrom -V', getpir
and /proc/cpu output for the Neoware EON 4000S board/Thin Client.
PS: this board is very similar to this one:
http://www.coreboot.org/ASI_MB-5BLMP_Build_Tutorial
instead of the DOC and Bios Chip for example.
Good luck for your further developement.
Hannes aka hns aka rwd
root@crux:~ # lspci -tvnn
-[0000:00]-+-00.0 Cyrix Corporation PCI Master [1078:0001]
+-0f.0 Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+
[10ec:8139]
+-12.0 Cyrix Corporation 5530 Legacy [Kahlua] [1078:0100]
+-12.1 Cyrix Corporation 5530 SMI [Kahlua] [1078:0101]
+-12.2 Cyrix Corporation 5530 IDE [Kahlua] [1078:0102]
+-12.3 Cyrix Corporation 5530 Audio [Kahlua] [1078:0103]
+-12.4 Cyrix Corporation 5530 Video [Kahlua] [1078:0104]
\-13.0 Compaq Computer Corporation ZFMicro Chipset USB
[0e11:a0f8]
root@crux:~ # superiotool -dV
superiotool r
Probing for ALi Super I/O at 0x3f0...
Failed. Returned data: id=0xffff, rev=0xff
Probing for ALi Super I/O at 0x370...
Failed. Returned data: id=0xffff, rev=0xff
Probing for Fintek Super I/O at 0x2e...
Failed. Returned data: vid=0x0a03, id=0x11e2
Probing for Fintek Super I/O at 0x4e...
Failed. Returned data: vid=0xffff, id=0xffff
Probing for ITE Super I/O (init=0x87,0x01,0x55,0x55/0xaa) at 0x2e...
Failed. Returned data: id=0xe211, rev=0x0
Probing for ITE Super I/O (init=0x87,0x87) at 0x2e...
Failed. Returned data: id=0xe211, rev=0x0
Probing for ITE Super I/O (init=0x87,0x01,0x55,0x55/0xaa) at 0x4e...
Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=0x87,0x87) at 0x4e...
Failed. Returned data: id=0xffff, rev=0xf
Probing for NSC Super I/O at 0x2e...
Found NSC PC87351 (sid=0xe2, srid=0x02) at 0x2e
Register dump:
idx 20 21 22 23 24 27 2e
val e2 11 a0 03 0a 02 00
def e2 11 a1 00 MM NA RR
LDN 0x00 (Floppy)
idx 30 60 61 70 71 74 75 f0 f1
val 01 03 f0 06 03 02 04 24 00
def 00 03 f2 06 03 02 04 24 00
LDN 0x01 (Parallel port)
idx 30 60 61 70 71 74 75 f0
val 01 03 78 07 02 00 04 00
def 00 02 78 07 02 04 04 f2
LDN 0x02 (COM2)
idx 30 60 61 70 71 74 75 f0
val 01 02 f8 03 03 04 04 02
def 00 02 f8 03 03 04 04 02
LDN 0x03 (COM1)
idx 30 60 61 70 71 74 75 f0
val 01 03 f8 04 03 04 04 02
def 00 03 f8 04 03 04 04 02
LDN 0x04 (System wake-up control (SWC))
idx 30 60 61 70 71 74 75
val 01 05 00 00 03 04 04
def 00 00 00 00 03 04 04
LDN 0x05 (Mouse)
idx 30 70 71 74 75
val 00 00 02 04 04
def 00 0c 02 04 04
LDN 0x06 (Keyboard)
idx 30 60 61 62 63 70 71 74 75 f0
val 01 00 60 00 64 01 02 04 04 40
def 01 00 60 00 64 01 02 04 04 40
LDN 0x07 (GPIO)
idx 30 60 61 70 71 74 75 f0 f1
val 01 08 00 00 03 04 04 22 45
def 00 00 00 00 03 04 04 00 00
LDN 0x08 (Fan speed control)
idx 30 60 61 70 71 74 75 f0
val 01 09 00 00 00 04 04 00
def 00 00 00 00 00 04 04 00
Probing for NSC Super I/O at 0x4e...
Failed. Returned data: port=0xff, port+1=0xff
Probing for NSC Super I/O at 0x15c...
Failed. Returned data: port=0xff, port+1=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e...
Failed. Returned data: id=0xe2, rev=0x11
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e...
Failed. Returned data: id=0x00, rev=0x00
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e...
Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e...
Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e...
Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e...
Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e...
Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e...
Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0...
Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0...
Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370...
Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370...
Failed. Returned data: id=0xff, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x2e...
Failed. Returned data: id/oldid=0xe2/0x00, rev=0x11
Probing for Winbond Super I/O (init=0x89) at 0x2e...
Failed. Returned data: id/oldid=0xe2/0x00, rev=0x11
Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e...
Failed. Returned data: id/oldid=0xe2/0x00, rev=0x11
Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e...
Failed. Returned data: id/oldid=0xe2/0x00, rev=0x11
Probing for Winbond Super I/O (init=0x88) at 0x4e...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x4e...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x3f0...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x3f0...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x370...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x370...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x370...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x370...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x250...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x250...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x250...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x250...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
root@crux:~ # flashrom -V
Calibrating delay loop... 40M loops per second. OK.
No coreboot table found.
Found chipset "AMD CS5530(A)", enabling flash write... OK.
Probing for AMD Am29F016D, 2048 KB: probe_29f040b: id1 0x25, id2 0xd7
Probing for AMD Am29F040B, 512 KB: probe_29f040b: id1 0x25, id2 0xd7
Probing for AMD Am29LV040B, 512 KB: probe_29f040b: id1 0x25, id2 0xd7
Probing for ASD AE49F2008, 256 KB: probe_jedec: id1 0xbf, id2 0xb6
Probing for Atmel AT29C020, 256 KB: probe_jedec: id1 0xbf, id2 0xb6
Probing for Atmel AT29C040A, 512 KB: probe_jedec: id1 0xbf, id2 0xb6
Probing for Atmel AT49F002(N), 256 KB: probe_jedec: id1 0xbf, id2 0xb6
Probing for Atmel AT49F002(N)T, 256 KB: probe_jedec: id1 0xbf, id2 0xb6
Probing for Atmel AT25DF321, 4096 KB: spi_command called, but no SPI
chipset detected
Probing for AMIC Technology A25L40P, 512 KB: spi_command called, but no
SPI chipset detected
Probing for AMIC Technology A49LF040A, 512 KB: probe_jedec: id1 0xbf,
id2 0xb6
Probing for AMIC Technology A29040B, 512 KB: probe_29f040b: id1 0x25,
id2 0xd7
Probing for EMST F49B002UA, 256 KB: probe_jedec: id1 0xbf, id2 0xb6
Probing for EON EN29F002(A)(N)B, 256 KB: probe_jedec: id1 0xbf, id2 0xb6
Probing for EON EN29F002(A)(N)T, 256 KB: probe_jedec: id1 0xbf, id2 0xb6
Probing for Fujitsu MBM29F400TC, 512 KB: probe_m29f400bt: id1 0x25, id2 0x2d
Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0x25, id2 0xd7
Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0x25, id2 0xd7
Probing for Macronix MX25L4005, 512 KB: spi_command called, but no SPI
chipset detected
Probing for Macronix MX25L8005, 1024 KB: spi_command called, but no SPI
chipset detected
Probing for Macronix MX25L1605, 2048 KB: spi_command called, but no SPI
chipset detected
Probing for Macronix MX25L3205, 4096 KB: spi_command called, but no SPI
chipset detected
Probing for Macronix MX29F002, 256 KB: probe_29f002: id1 0xbf, id2 0xb6
Probing for PMC Pm25LV010, 128 KB: spi_command called, but no SPI
chipset detected
Probing for PMC Pm25LV016B, 2048 KB: spi_command called, but no SPI
chipset detected
Probing for PMC Pm25LV020, 256 KB: spi_command called, but no SPI
chipset detected
Probing for PMC Pm25LV040, 512 KB: spi_command called, but no SPI
chipset detected
Probing for PMC Pm25LV080B, 1024 KB: spi_command called, but no SPI
chipset detected
Probing for PMC Pm25LV512, 64 KB: spi_command called, but no SPI chipset
detected
Probing for PMC Pm49FL002, 256 KB: probe_jedec: id1 0xbf, id2 0xb6
Probing for PMC Pm49FL004, 512 KB: probe_jedec: id1 0xbf, id2 0xb6
Probing for Sharp LHF00L04, 1024 KB: probe_lhf00l04: id1 0x25, id2 0xd7
Probing for Spansion S25FL016A, 2048 KB: spi_command called, but no SPI
chipset detected
Probing for SST SST25VF016B, 2048 KB: spi_command called, but no SPI
chipset detected
Probing for SST SST25VF040B, 512 KB: spi_command called, but no SPI
chipset detected
Probing for SST SST28SF040A, 512 KB: probe_28sf040: id1 0x25, id2 0xd7
Probing for SST SST29EE010, 128 KB: probe_jedec: id1 0xbf, id2 0xb6
Probing for SST SST29LE010, 128 KB: probe_jedec: id1 0xbf, id2 0xb6
Probing for SST SST29EE020A, 256 KB: probe_jedec: id1 0xbf, id2 0xb6
Probing for SST SST29LE020, 256 KB: probe_jedec: id1 0xbf, id2 0xb6
Probing for SST SST39SF010A, 128 KB: probe_jedec: id1 0xbf, id2 0xb6
Probing for SST SST39SF020A, 256 KB: probe_jedec: id1 0xbf, id2 0xb6
Found chip "SST SST39SF020A" (256 KB) at physical address 0xfffc0000.
Probing for SST SST39SF040, 512 KB: probe_jedec: id1 0xbf, id2 0xb6
Probing for SST SST39VF512, 64 KB: probe_jedec: id1 0xbf, id2 0xb6
Probing for SST SST39VF010, 128 KB: probe_jedec: id1 0xbf, id2 0xb6
Probing for SST SST39VF020, 256 KB: probe_jedec: id1 0xbf, id2 0xb6
Probing for SST SST39VF040, 512 KB: probe_jedec: id1 0xbf, id2 0xb6
Probing for SST SST49LF002A/B, 256 KB: probe_jedec: id1 0xbf, id2 0xb6
Probing for SST SST49LF003A/B, 384 KB: probe_jedec: id1 0xbf, id2 0xb6
Probing for SST SST49LF004A/B, 512 KB: probe_jedec: id1 0xbf, id2 0xb6
Probing for SST SST49LF004C, 512 KB: probe_49lfxxxc: id1 0x25, id2 0xd7
Probing for SST SST49LF008A, 1024 KB: probe_jedec: id1 0xbf, id2 0xb6
Probing for SST SST49LF008C, 1024 KB: probe_49lfxxxc: id1 0x25, id2 0xd7
Probing for SST SST49LF016C, 2048 KB: probe_49lfxxxc: id1 0x25, id2 0xd7
Probing for SST SST49LF020A, 256 KB: probe_jedec: id1 0xbf, id2 0xb6
Probing for SST SST49LF040, 512 KB: probe_jedec: id1 0xbf, id2 0xb6
Probing for SST SST49LF040B, 512 KB: probe_jedec: id1 0xbf, id2 0xb6
Probing for SST SST49LF080A, 1024 KB: probe_jedec: id1 0xbf, id2 0xb6
Probing for SST SST49LF160C, 2048 KB: probe_49lfxxxc: id1 0x25, id2 0xd7
Probing for ST M25P05-A, 64 KB: spi_command called, but no SPI chipset
detected
Probing for ST M25P10-A, 128 KB: spi_command called, but no SPI chipset
detected
Probing for ST M25P20, 256 KB: spi_command called, but no SPI chipset
detected
Probing for ST M25P40, 512 KB: spi_command called, but no SPI chipset
detected
Probing for ST M25P40-old, 512 KB: spi_command called, but no SPI
chipset detected
Probing for ST M25P80, 1024 KB: spi_command called, but no SPI chipset
detected
Probing for ST M25P16, 2048 KB: spi_command called, but no SPI chipset
detected
Probing for ST M25P32, 4096 KB: spi_command called, but no SPI chipset
detected
Probing for ST M25P64, 8192 KB: spi_command called, but no SPI chipset
detected
Probing for ST M25P128, 16384 KB: spi_command called, but no SPI chipset
detected
Probing for ST M29F002B, 256 KB: probe_jedec: id1 0xbf, id2 0xb6
Probing for ST M29F002T/NT, 256 KB: probe_jedec: id1 0xbf, id2 0xb6
Probing for ST M29F040B, 512 KB: probe_29f040b: id1 0x25, id2 0xd7
Probing for ST M29F400BT, 512 KB: probe_m29f400bt: id1 0x25, id2 0x2d
Probing for ST M29W010B, 128 KB: probe_jedec: id1 0xbf, id2 0xb6
Probing for ST M29W040B, 512 KB: probe_jedec: id1 0xbf, id2 0xb6
Probing for ST M50FLW040A, 512 KB: probe_stm50flw0x0x: id1 0xbf, id2 0xb6
Probing for ST M50FLW040B, 512 KB: probe_stm50flw0x0x: id1 0xbf, id2 0xb6
Probing for ST M50FLW080A, 1024 KB: probe_stm50flw0x0x: id1 0xbf, id2 0xb6
Probing for ST M50FLW080B, 1024 KB: probe_stm50flw0x0x: id1 0xbf, id2 0xb6
Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0x25, id2 0xd7
Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0x25, id2 0xd7
Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0x25, id2 0xd7
Probing for ST M50LPW116, 2048 KB: probe_jedec: id1 0xbf, id2 0xb6
Probing for SyncMOS S29C31004T, 512 KB: probe_jedec: id1 0xbf, id2 0xb6
Probing for SyncMOS S29C51001T, 128 KB: probe_jedec: id1 0xbf, id2 0xb6
Probing for SyncMOS S29C51002T, 256 KB: probe_jedec: id1 0xbf, id2 0xb6
Probing for SyncMOS S29C51004T, 512 KB: probe_jedec: id1 0xbf, id2 0xb6
Probing for Winbond W25x10, 128 KB: spi_command called, but no SPI
chipset detected
Probing for Winbond W25x20, 256 KB: spi_command called, but no SPI
chipset detected
Probing for Winbond W25x40, 512 KB: spi_command called, but no SPI
chipset detected
Probing for Winbond W25x80, 1024 KB: spi_command called, but no SPI
chipset detected
Probing for Winbond W29C011, 128 KB: probe_jedec: id1 0xbf, id2 0xb6
Probing for Winbond W29C020C, 256 KB: probe_jedec: id1 0xbf, id2 0xb6
Probing for Winbond W29C040P, 512 KB: probe_jedec: id1 0xbf, id2 0xb6
Probing for Winbond W29EE011, 128 KB:
===
Probing disabled for Winbond W29EE011 because the probing sequence
puts the
AMIC A49LF040A in a funky state.
Use 'flashrom -c W29EE011' if you have a board with this chip.
===
Probing for Winbond W39V040A, 512 KB: probe_jedec: id1 0xbf, id2 0xb6
Probing for Winbond W39V040B, 512 KB: probe_jedec: id1 0xbf, id2 0xb6
Probing for Winbond W39V040FA, 512 KB: probe_jedec: id1 0xbf, id2 0xb6
Probing for Winbond W39V080A, 1024 KB: probe_jedec: id1 0xbf, id2 0xb6
Probing for Winbond W49F002U, 256 KB: probe_jedec: id1 0xbf, id2 0xb6
Probing for Winbond W49V002A, 256 KB: probe_jedec: id1 0xbf, id2 0xb6
Probing for Winbond W49V002FA, 256 KB: probe_jedec: id1 0xbf, id2 0xb6
Probing for Winbond W39V080FA, 1024 KB: probe_winbond_fwhub: vid 0xbf,
did 0xb6
Probing for Winbond W39V080FA (dual mode), 512 KB: probe_winbond_fwhub:
vid 0xbf, did 0xb6
Probing for EON unknown EON SPI chip, 0 KB: spi_command called, but no
SPI chipset detected
Probing for Macronix unknown Macronix SPI chip, 0 KB: spi_command
called, but no SPI chipset detected
Probing for PMC unknown PMC SPI chip, 0 KB: spi_command called, but no
SPI chipset detected
Probing for SST unknown SST SPI chip, 0 KB: spi_command called, but no
SPI chipset detected
Probing for ST unknown ST SPI chip, 0 KB: spi_command called, but no SPI
chipset detected
No operations were specified.
root@crux:~/coreboot-v2-3389/util/getpir # cat irq_tables.c
/* This file was generated by getpir.c, do not modify!
* (but if you do, please run checkpir on it to verify)
*
* Contains the IRQ Routing Table dumped directly from your
* memory, which BIOS sets up.
*
* Documentation at: http://www.microsoft.com/whdc/archive/pciirq.mspx
*/
#ifdef GETPIR
#include "pirq_routing.h"
#else
#include <arch/pirq_routing.h>
#endif
const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
32+16*3, /* There can be total 3 devices on the bus */
0x00, /* Where the interrupt router lies (bus) */
(0x12<<3)|0x0, /* Where the interrupt router lies (dev) */
0x8800, /* IRQs devoted exclusively to PCI usage */
0x1078, /* Vendor */
0x2, /* Device */
0, /* Crap (miniport) */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0x96, /* u8 checksum. This has to be set to some
value that would give 0 after the sum of all
bytes for this structure (including checksum) */
{
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link,
bitmap}, {link, bitmap}, slot, rfu */
{0x00,(0x07<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04,
0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0},
{0x00,(0x0f<<3)|0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01,
0xdeb8}, {0x02, 0x0deb8}}, 0x2, 0x0},
{0x00,(0x13<<3)|0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00,
0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
}
};
unsigned long write_pirq_routing_table(unsigned long addr)
{
return copy_pirq_routing_table(addr);
}
root@crux:~ # cat /proc/cpuinfo
processor : 0
vendor_id : Geode by NSC
cpu family : 5
model : 9
model name : Geode(TM) Integrated Processor by National Semi
stepping : 2
cpu MHz : 300.691
cache size : 16 KB
fdiv_bug : no
hlt_bug : no
f00f_bug : no
coma_bug : no
fpu : yes
fpu_exception : yes
cpuid level : 2
wp : yes
flags : fpu tsc msr cx8 cmov mmx cxmmx up
bogomips : 611.94
clflush size : 32
