by svn＠coreboot.org
Author: stepan
Date: 2008-07-01 01:45:22 +0200 (Tue, 01 Jul 2008)
New Revision: 3401
Modified:
trunk/util/flashrom/chipset_enable.c
trunk/util/flashrom/flash.h
trunk/util/flashrom/ichspi.c
trunk/util/flashrom/it87spi.c
trunk/util/flashrom/spi.c
Log:
First attempt to clean up SPI probing and create a common
construct: the flash bus.
At some point the flash bus will be part of struct flashchip.
Pardon me for pushing this in, but I think it is important to beware of further
decay and it will improve things for other developers in the short run.
Carl-Daniel, I will consider your suggestions in another patch. I want to keep
things from getting too much for now. The patch includes Rudolf's VIA SPI
changes though.
Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net>
Modified: trunk/util/flashrom/chipset_enable.c
===================================================================
--- trunk/util/flashrom/chipset_enable.c 2008-06-30 21:48:54 UTC (rev 3400)
+++ trunk/util/flashrom/chipset_enable.c 2008-06-30 23:45:22 UTC (rev 3401)
@@ -35,6 +35,17 @@
#include <unistd.h>
#include "flash.h"
+/**
+ * flashrom defaults to LPC flash devices. If a known SPI controller is found
+ * and the SPI strappings are set, this will be overwritten by the probing code.
+ *
+ * Eventually, this will become an array when multiple flash support works.
+ */
+
+flashbus_t flashbus = BUS_TYPE_LPC;
+void *spibar = NULL;
+
+
static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name)
{
uint8_t tmp;
@@ -124,7 +135,7 @@
* Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA.
* Set bit 2: BIOSCS# Write Enable (1=enable, 0=disable).
*/
- new = old | 0x2c4;
+ new = old | 0x02c4;
if (new == old)
return 0;
@@ -185,88 +196,131 @@
return enable_flash_ich(dev, name, 0xdc);
}
-void *ich_spibar = NULL;
+#define ICH_STRAP_RSVD 0x00
+#define ICH_STRAP_SPI 0x01
+#define ICH_STRAP_PCI 0x02
+#define ICH_STRAP_LPC 0x03
static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name) {
uint32_t mmio_base;
mmio_base = (pci_read_long(dev, 0xbc)) << 8;
printf_debug("MMIO base at = 0x%x\n", mmio_base);
- ich_spibar = mmap(NULL, 0x70, PROT_READ | PROT_WRITE, MAP_SHARED,
+ spibar = mmap(NULL, 0x70, PROT_READ | PROT_WRITE, MAP_SHARED,
fd_mem, mmio_base);
- if (ich_spibar == MAP_FAILED) {
+ if (spibar == MAP_FAILED) {
perror("Can't mmap memory using " MEM_DEV);
exit(1);
}
- printf_debug("0x6c: 0x%04x (CLOCK/DEBUG)\n", *(uint16_t *)(ich_spibar + 0x6c));
- viaspi_detected = 1;
+ printf_debug("0x6c: 0x%04x (CLOCK/DEBUG)\n", *(uint16_t *)(spibar + 0x6c));
+
+ flashbus = BUS_TYPE_VIA_SPI;
+
return 0;
}
-static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, unsigned long spibar)
+static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, int ich_generation)
{
+ int ret, i;
uint8_t old, new, bbs, buc;
+ uint16_t spibar_offset;
uint32_t tmp, gcs;
void *rcrb;
+ static const char *straps_names[] = { "reserved", "SPI", "PCI", "LPC" };
+
+ /* Enable Flash Writes */
+ ret = enable_flash_ich_dc(dev, name);
- /* Read the Root Complex Base Address Register (RCBA) */
- tmp = pci_read_long(dev, 0xf0);
+ /* Get physical address of Root Complex Register Block */
+ tmp = pci_read_long(dev, 0xf0) & 0xffffc000;
+ printf_debug("\nRoot Complex Register Block address = 0x%x\n", tmp);
- /* Calculate the Root Complex Register Block address */
- tmp &= 0xffffc000;
- printf_debug("\nRoot Complex Register Block address = 0x%x\n", tmp);
+ /* Map RCBA to virtual memory */
rcrb = mmap(0, 0x4000, PROT_READ | PROT_WRITE, MAP_SHARED, fd_mem, (off_t)tmp);
if (rcrb == MAP_FAILED) {
perror("Can't mmap memory using " MEM_DEV);
exit(1);
}
- printf_debug("GCS address = 0x%x\n", tmp + 0x3410);
+
gcs = *(volatile uint32_t *)(rcrb + 0x3410);
printf_debug("GCS = 0x%x: ", gcs);
printf_debug("BIOS Interface Lock-Down: %sabled, ",
(gcs & 0x1) ? "en" : "dis");
bbs = (gcs >> 10) & 0x3;
- printf_debug("BOOT BIOS Straps: 0x%x (%s)\n", bbs,
- (bbs == 0x3) ? "LPC" : ((bbs == 0x2) ? "PCI" : "SPI"));
- if (bbs >= 2)
- ich7_detected = 0;
+ printf_debug("BOOT BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]);
buc = *(volatile uint8_t *)(rcrb + 0x3414);
printf_debug("Top Swap : %s\n", (buc & 1)?"enabled (A16 inverted)":"not enabled");
+ /* It seems the ICH7 does not support SPI and LPC chips at the same
+ * time. At least not with our current code. So we prevent searching
+ * on ICH7 when the southbridge is strapped to LPC
+ */
+
+ if (ich_generation == 7 && bbs == ICH_STRAP_LPC) {
+ /* No further SPI initialization required */
+ return ret;
+ }
+
+ switch (ich_generation) {
+ case 7:
+ flashbus = BUS_TYPE_ICH7_SPI;
+ spibar_offset = 0x3020;
+ break;
+ case 8:
+ flashbus = BUS_TYPE_ICH9_SPI;
+ spibar_offset = 0x3020;
+ break;
+ case 9:
+ default: /* Future version might behave the same */
+ flashbus = BUS_TYPE_ICH9_SPI;
+ spibar_offset = 0x3800;
+ break;
+ }
+
/* SPIBAR is at RCRB+0x3020 for ICH[78] and RCRB+0x3800 for ICH9. */
- printf_debug("SPIBAR = 0x%x + 0x%04x\n", tmp, (uint16_t)spibar);
+ printf_debug("SPIBAR = 0x%x + 0x%04x\n", tmp, spibar_offset);
- // Assign Virtual Address
- ich_spibar = rcrb + spibar;
+ /* Assign Virtual Address */
+ spibar = rcrb + spibar_offset;
- if (ich7_detected) {
- int i;
- printf_debug("0x00: 0x%04x (SPIS)\n", *(uint16_t *)(ich_spibar + 0));
- printf_debug("0x02: 0x%04x (SPIC)\n", *(uint16_t *)(ich_spibar + 2));
- printf_debug("0x04: 0x%08x (SPIA)\n", *(uint32_t *)(ich_spibar + 4));
+ switch (flashbus) {
+ case BUS_TYPE_ICH7_SPI:
+ printf_debug("0x00: 0x%04x (SPIS)\n", *(uint16_t *)(spibar + 0));
+ printf_debug("0x02: 0x%04x (SPIC)\n", *(uint16_t *)(spibar + 2));
+ printf_debug("0x04: 0x%08x (SPIA)\n", *(uint32_t *)(spibar + 4));
for (i=0; i < 8; i++) {
int offs;
offs = 8 + (i * 8);
- printf_debug("0x%02x: 0x%08x (SPID%d)\n", offs, *(uint32_t *)(ich_spibar + offs), i);
- printf_debug("0x%02x: 0x%08x (SPID%d+4)\n", offs+4, *(uint32_t *)(ich_spibar + offs +4), i);
+ printf_debug("0x%02x: 0x%08x (SPID%d)\n", offs, *(uint32_t *)(spibar + offs), i);
+ printf_debug("0x%02x: 0x%08x (SPID%d+4)\n", offs+4, *(uint32_t *)(spibar + offs +4), i);
}
- printf_debug("0x50: 0x%08x (BBAR)\n", *(uint32_t *)(ich_spibar + 0x50));
- printf_debug("0x54: 0x%04x (PREOP)\n", *(uint16_t *)(ich_spibar + 0x54));
- printf_debug("0x56: 0x%04x (OPTYPE)\n", *(uint16_t *)(ich_spibar + 0x56));
- printf_debug("0x58: 0x%08x (OPMENU)\n", *(uint32_t *)(ich_spibar + 0x58));
- printf_debug("0x5c: 0x%08x (OPMENU+4)\n", *(uint32_t *)(ich_spibar + 0x5c));
+ printf_debug("0x50: 0x%08x (BBAR)\n", *(uint32_t *)(spibar + 0x50));
+ printf_debug("0x54: 0x%04x (PREOP)\n", *(uint16_t *)(spibar + 0x54));
+ printf_debug("0x56: 0x%04x (OPTYPE)\n", *(uint16_t *)(spibar + 0x56));
+ printf_debug("0x58: 0x%08x (OPMENU)\n", *(uint32_t *)(spibar + 0x58));
+ printf_debug("0x5c: 0x%08x (OPMENU+4)\n", *(uint32_t *)(spibar + 0x5c));
for (i=0; i < 4; i++) {
int offs;
offs = 0x60 + (i * 4);
- printf_debug("0x%02x: 0x%08x (PBR%d)\n", offs, *(uint32_t *)(ich_spibar + offs), i);
+ printf_debug("0x%02x: 0x%08x (PBR%d)\n", offs, *(uint32_t *)(spibar + offs), i);
}
printf_debug("\n");
- if ( (*(uint16_t *)ich_spibar) & (1 << 15)) {
+ if ( (*(uint16_t *)spibar) & (1 << 15)) {
printf("WARNING: SPI Configuration Lockdown activated.\n");
}
+ break;
+ case BUS_TYPE_ICH9_SPI:
+ /* TODO: Add dumping function for ICH8/ICH9, or drop the
+ * whole SPIBAR dumping from chipset_enable.c - There's
+ * inteltool for this task already.
+ */
+ break;
+ default:
+ /* Nothing */
+ break;
}
old = pci_read_byte(dev, 0xdc);
@@ -277,38 +331,30 @@
case 1:
case 2:
printf_debug("prefetching %sabled, caching %sabled, ",
- (new & 0x2) ? "en" : "dis", (new & 0x1) ? "dis" : "en");
+ (new & 0x2) ? "en" : "dis",
+ (new & 0x1) ? "dis" : "en");
break;
default:
printf_debug("invalid prefetching/caching settings, ");
break;
}
- return enable_flash_ich_dc(dev, name);
+
+ return ret;
}
-/* Flag for ICH7 SPI register block */
-int ich7_detected = 0;
-int viaspi_detected = 0;
-
static int enable_flash_ich7(struct pci_dev *dev, const char *name)
{
- ich7_detected = 1;
- return enable_flash_ich_dc_spi(dev, name, 0x3020);
+ return enable_flash_ich_dc_spi(dev, name, 7);
}
-/* Flag for ICH8/ICH9 SPI register block */
-int ich9_detected = 0;
-
static int enable_flash_ich8(struct pci_dev *dev, const char *name)
{
- ich9_detected = 1;
- return enable_flash_ich_dc_spi(dev, name, 0x3020);
+ return enable_flash_ich_dc_spi(dev, name, 8);
}
static int enable_flash_ich9(struct pci_dev *dev, const char *name)
{
- ich9_detected = 1;
- return enable_flash_ich_dc_spi(dev, name, 0x3800);
+ return enable_flash_ich_dc_spi(dev, name, 9);
}
static int enable_flash_vt823x(struct pci_dev *dev, const char *name)
Modified: trunk/util/flashrom/flash.h
===================================================================
--- trunk/util/flashrom/flash.h 2008-06-30 21:48:54 UTC (rev 3400)
+++ trunk/util/flashrom/flash.h 2008-06-30 23:45:22 UTC (rev 3401)
@@ -370,11 +370,18 @@
/* chipset_enable.c */
int chipset_flash_enable(void);
void print_supported_chipsets(void);
-extern int ich7_detected;
-extern int viaspi_detected;
-extern int ich9_detected;
-extern void *ich_spibar;
+typedef enum {
+ BUS_TYPE_LPC,
+ BUS_TYPE_ICH7_SPI,
+ BUS_TYPE_ICH9_SPI,
+ BUS_TYPE_IT87XX_SPI,
+ BUS_TYPE_VIA_SPI
+} flashbus_t;
+
+extern flashbus_t flashbus;
+extern void *spibar;
+
/* Physical memory mapping device */
#if defined (__sun) && (defined(__i386) || defined(__amd64))
# define MEM_DEV "/dev/xsvc"
Modified: trunk/util/flashrom/ichspi.c
===================================================================
--- trunk/util/flashrom/ichspi.c 2008-06-30 21:48:54 UTC (rev 3400)
+++ trunk/util/flashrom/ichspi.c 2008-06-30 23:45:22 UTC (rev 3401)
@@ -131,20 +131,20 @@
static inline uint32_t REGREAD32(int X)
{
volatile uint32_t regval;
- regval = *(volatile uint32_t *) ((uint8_t *) ich_spibar + X);
+ regval = *(volatile uint32_t *) ((uint8_t *) spibar + X);
return regval;
}
static inline uint16_t REGREAD16(int X)
{
volatile uint16_t regval;
- regval = *(volatile uint16_t *) ((uint8_t *) ich_spibar + X);
+ regval = *(volatile uint16_t *) ((uint8_t *) spibar + X);
return regval;
}
-#define REGWRITE32(X,Y) (*(uint32_t *)((uint8_t *)ich_spibar+X)=Y)
-#define REGWRITE16(X,Y) (*(uint16_t *)((uint8_t *)ich_spibar+X)=Y)
-#define REGWRITE8(X,Y) (*(uint8_t *)((uint8_t *)ich_spibar+X)=Y)
+#define REGWRITE32(X,Y) (*(uint32_t *)((uint8_t *)spibar+X)=Y)
+#define REGWRITE16(X,Y) (*(uint16_t *)((uint8_t *)spibar+X)=Y)
+#define REGWRITE8(X,Y) (*(uint8_t *)((uint8_t *)spibar+X)=Y)
/* Common SPI functions */
static int program_opcodes(OPCODES * op);
@@ -175,58 +175,51 @@
int program_opcodes(OPCODES * op)
{
uint8_t a;
- uint16_t temp16;
- uint32_t temp32;
+ uint16_t preop, optype;
+ uint32_t opmenu[2];
/* Program Prefix Opcodes */
- temp16 = 0;
+ preop = 0;
/* 0:7 Prefix Opcode 1 */
- temp16 = (op->preop[0]);
+ preop = (op->preop[0]);
/* 8:16 Prefix Opcode 2 */
- temp16 |= ((uint16_t) op->preop[1]) << 8;
- if ((ich7_detected) || (viaspi_detected)) {
- REGWRITE16(ICH7_REG_PREOP, temp16);
- } else if (ich9_detected) {
- REGWRITE16(ICH9_REG_PREOP, temp16);
- }
-
+ preop |= ((uint16_t) op->preop[1]) << 8;
+
/* Program Opcode Types 0 - 7 */
- temp16 = 0;
+ optype = 0;
for (a = 0; a < 8; a++) {
- temp16 |= ((uint16_t) op->opcode[a].spi_type) << (a * 2);
+ optype |= ((uint16_t) op->opcode[a].spi_type) << (a * 2);
}
-
- if ((ich7_detected) || (viaspi_detected)) {
- REGWRITE16(ICH7_REG_OPTYPE, temp16);
- } else if (ich9_detected) {
- REGWRITE16(ICH9_REG_OPTYPE, temp16);
- }
-
-
+
/* Program Allowable Opcodes 0 - 3 */
- temp32 = 0;
+ opmenu[0] = 0;
for (a = 0; a < 4; a++) {
- temp32 |= ((uint32_t) op->opcode[a].opcode) << (a * 8);
+ opmenu[0] |= ((uint32_t) op->opcode[a].opcode) << (a * 8);
}
- if ((ich7_detected) || (viaspi_detected)) {
- REGWRITE32(ICH7_REG_OPMENU, temp32);
- } else if (ich9_detected) {
- REGWRITE32(ICH9_REG_OPMENU, temp32);
- }
-
-
/*Program Allowable Opcodes 4 - 7 */
- temp32 = 0;
+ opmenu[1] = 0;
for (a = 4; a < 8; a++) {
- temp32 |=
- ((uint32_t) op->opcode[a].opcode) << ((a - 4) * 8);
+ opmenu[1] |= ((uint32_t) op->opcode[a].opcode) << ((a - 4) * 8);
}
- if ((ich7_detected) || (viaspi_detected)) {
- REGWRITE32(ICH7_REG_OPMENU + 4, temp32);
- } else if (ich9_detected) {
- REGWRITE32(ICH9_REG_OPMENU + 4, temp32);
+ switch (flashbus) {
+ case BUS_TYPE_ICH7_SPI:
+ case BUS_TYPE_VIA_SPI:
+ REGWRITE16(ICH7_REG_PREOP, preop);
+ REGWRITE16(ICH7_REG_OPTYPE, optype);
+ REGWRITE32(ICH7_REG_OPMENU, opmenu[0]);
+ REGWRITE32(ICH7_REG_OPMENU + 4, opmenu[1]);
+ break;
+ case BUS_TYPE_ICH9_SPI:
+ REGWRITE16(ICH9_REG_PREOP, preop);
+ REGWRITE16(ICH9_REG_OPTYPE, optype);
+ REGWRITE32(ICH9_REG_OPMENU, opmenu[0]);
+ REGWRITE32(ICH9_REG_OPMENU + 4, opmenu[1]);
+ break;
+ default:
+ printf_debug("%s: unsupported chipset\n", __FUNCTION__);
+ return -1;
}
return 0;
@@ -340,6 +333,7 @@
uint8_t datalength, uint8_t * data)
{
int write_cmd = 0;
+ int timeout;
uint32_t temp32;
uint32_t a;
@@ -410,10 +404,13 @@
REGWRITE32(ICH9_REG_SSFS, temp32);
/*wait for cycle complete */
- while ((REGREAD32(ICH9_REG_SSFS) & SSFS_CDS) == 0) {
- /*TODO; Do something that this can't lead into an endless loop. but some
- * commands may cause this to be last more than 30 seconds */
+ timeout = 1000 * 60; // 60s is a looong timeout.
+ while (((REGREAD32(ICH9_REG_SSFS) & SSFS_CDS) == 0) && --timeout) {
+ myusec_delay(1000);
}
+ if (!timeout) {
+ printf_debug("timeout\n");
+ }
if ((REGREAD32(ICH9_REG_SSFS) & SSFS_FCERR) != 0) {
printf_debug("Transaction error!\n");
@@ -438,12 +435,16 @@
static int run_opcode(uint8_t nr, OPCODE op, uint32_t offset,
uint8_t datalength, uint8_t * data)
{
- if (ich7_detected)
+ switch (flashbus) {
+ case BUS_TYPE_VIA_SPI:
+ return ich7_run_opcode(nr, op, offset, datalength, data, 16);
+ case BUS_TYPE_ICH7_SPI:
return ich7_run_opcode(nr, op, offset, datalength, data, 64);
- else if (viaspi_detected)
- return ich7_run_opcode(nr, op, offset, datalength, data, 16);
- else if (ich9_detected)
+ case BUS_TYPE_ICH9_SPI:
return ich9_run_opcode(nr, op, offset, datalength, data);
+ default:
+ printf_debug("%s: unsupported chipset\n", __FUNCTION__);
+ }
/* If we ever get here, something really weird happened */
return -1;
@@ -541,7 +542,7 @@
int page_size = flash->page_size;
int maxdata = 64;
- if (viaspi_detected) {
+ if (flashbus == BUS_TYPE_VIA_SPI) {
maxdata = 16;
}
@@ -572,7 +573,7 @@
break;
}
- if (viaspi_detected) {
+ if (flashbus == BUS_TYPE_VIA_SPI) {
maxdata = 16;
}
for (j = 0; j < erase_size / page_size; j++) {
Modified: trunk/util/flashrom/it87spi.c
===================================================================
--- trunk/util/flashrom/it87spi.c 2008-06-30 21:48:54 UTC (rev 3400)
+++ trunk/util/flashrom/it87spi.c 2008-06-30 23:45:22 UTC (rev 3401)
@@ -3,6 +3,7 @@
*
* Copyright (C) 2007, 2008 Carl-Daniel Hailfinger
* Copyright (C) 2008 Ronald Hoogenboom <ronald(a)zonnet.nl>
+ * Copyright (C) 2008 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -112,8 +113,13 @@
int it87xx_probe_spi_flash(const char *name)
{
it8716f_flashport = find_ite_spi_flash_port(ITE_SUPERIO_PORT1);
+
if (!it8716f_flashport)
it8716f_flashport = find_ite_spi_flash_port(ITE_SUPERIO_PORT2);
+
+ if (it8716f_flashport)
+ flashbus = BUS_TYPE_IT87XX_SPI;
+
return (!it8716f_flashport);
}
Modified: trunk/util/flashrom/spi.c
===================================================================
--- trunk/util/flashrom/spi.c 2008-06-30 21:48:54 UTC (rev 3400)
+++ trunk/util/flashrom/spi.c 2008-06-30 23:45:22 UTC (rev 3401)
@@ -34,13 +34,16 @@
int spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr)
{
- if (it8716f_flashport)
+ switch (flashbus) {
+ case BUS_TYPE_IT87XX_SPI:
return it8716f_spi_command(writecnt, readcnt, writearr, readarr);
- else if ((ich7_detected) || (viaspi_detected))
- return ich_spi_command(writecnt, readcnt, writearr, readarr);
- else if (ich9_detected)
- return ich_spi_command(writecnt, readcnt, writearr, readarr);
- printf_debug("%s called, but no SPI chipset detected\n", __FUNCTION__);
+ case BUS_TYPE_ICH7_SPI:
+ case BUS_TYPE_ICH9_SPI:
+ case BUS_TYPE_VIA_SPI:
+ return ich_spi_command(writecnt, readcnt, writearr, readarr);
+ default:
+ printf_debug("%s called, but no SPI chipset/strapping detected\n", __FUNCTION__);
+ }
return 1;
}
@@ -135,9 +138,16 @@
int probe_spi_rdid4(struct flashchip *flash) {
/* only some SPI chipsets support 4 bytes commands */
- if (!((ich7_detected) || (ich9_detected) || (viaspi_detected)))
- return 0;
- return probe_spi_rdid_generic(flash, 4);
+ switch (flashbus) {
+ case BUS_TYPE_ICH7_SPI:
+ case BUS_TYPE_ICH9_SPI:
+ case BUS_TYPE_VIA_SPI:
+ return probe_spi_rdid_generic(flash, 4);
+ default:
+ printf_debug("4b ID not supported on this SPI controller\n");
+ }
+
+ return 0;
}
int probe_spi_res(struct flashchip *flash)
@@ -316,11 +326,17 @@
void spi_page_program(int block, uint8_t *buf, uint8_t *bios)
{
- if (it8716f_flashport) {
+ switch (flashbus) {
+ case BUS_TYPE_IT87XX_SPI:
it8716f_spi_page_program(block, buf, bios);
- return;
+ break;
+ case BUS_TYPE_ICH7_SPI:
+ case BUS_TYPE_ICH9_SPI:
+ printf_debug("%s called, but not implemented for ICH\n", __FUNCTION__);
+ break;
+ default:
+ printf_debug("%s called, but no SPI chipset/strapping detected\n", __FUNCTION__);
}
- printf_debug("%s called, but no SPI chipset detected\n", __FUNCTION__);
}
/*
@@ -375,25 +391,34 @@
int spi_chip_read(struct flashchip *flash, uint8_t *buf)
{
- if (it8716f_flashport)
+
+ switch (flashbus) {
+ case BUS_TYPE_IT87XX_SPI:
return it8716f_spi_chip_read(flash, buf);
- else if ((ich7_detected) || (viaspi_detected))
+ case BUS_TYPE_ICH7_SPI:
+ case BUS_TYPE_ICH9_SPI:
+ case BUS_TYPE_VIA_SPI:
return ich_spi_read(flash, buf);
- else if (ich9_detected)
- return ich_spi_read(flash, buf);
- printf_debug("%s called, but no SPI chipset detected\n", __FUNCTION__);
+ default:
+ printf_debug("%s called, but no SPI chipset/strapping detected\n", __FUNCTION__);
+ }
+
return 1;
}
int spi_chip_write(struct flashchip *flash, uint8_t *buf)
{
- if (it8716f_flashport)
+ switch (flashbus) {
+ case BUS_TYPE_IT87XX_SPI:
return it8716f_spi_chip_write(flash, buf);
- else if ((ich7_detected) || (viaspi_detected))
+ case BUS_TYPE_ICH7_SPI:
+ case BUS_TYPE_ICH9_SPI:
+ case BUS_TYPE_VIA_SPI:
return ich_spi_write(flash, buf);
- else if (ich9_detected)
- return ich_spi_write(flash, buf);
- printf_debug("%s called, but no SPI chipset detected\n", __FUNCTION__);
+ default:
+ printf_debug("%s called, but no SPI chipset/strapping detected\n", __FUNCTION__);
+ }
+
return 1;
}
by svn＠coreboot.org
Author: ruik
Date: 2008-06-30 23:48:54 +0200 (Mon, 30 Jun 2008)
New Revision: 3400
Modified:
trunk/util/flashrom/flashchips.c
Log:
Mine AMIC flash chip needs 4 bytes RDID. This enables to use the new probing code.
Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz>
Acked-by: Peter Stuge <peter(a)stuge.se>
Modified: trunk/util/flashrom/flashchips.c
===================================================================
--- trunk/util/flashrom/flashchips.c 2008-06-30 21:45:17 UTC (rev 3399)
+++ trunk/util/flashrom/flashchips.c 2008-06-30 21:48:54 UTC (rev 3400)
@@ -41,7 +41,7 @@
{"Atmel", "AT49F002(N)", ATMEL_ID, AT_49F002N, 256, 256, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec},
{"Atmel", "AT49F002(N)T", ATMEL_ID, AT_49F002NT, 256, 256, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec},
{"Atmel", "AT25DF321", ATMEL_ID, AT_25DF321, 4096, 256, TEST_OK_PREW, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read},
- {"AMIC Technology","A25L40P", AMIC_ID, AMIC_A25L40P, 512, 256, TEST_UNTESTED, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read},
+ {"AMIC Technology","A25L40P", AMIC_ID, AMIC_A25L40P, 512, 256, TEST_OK_PREW, probe_spi_rdid4, spi_chip_erase_c7, spi_chip_write, spi_chip_read},
{"AMIC Technology","A49LF040A", AMIC_ID_NOPREFIX, AMIC_A49LF040A, 512, 64 * 1024, TEST_OK_PREW, probe_49fl00x, erase_49fl00x, write_49fl00x},
{"AMIC Technology","A29040B", AMIC_ID_NOPREFIX, AMIC_A29040B, 512, 64 * 1024, TEST_OK_PR, probe_29f040b, erase_29f040b, write_29f040b},
{"EMST", "F49B002UA", EMST_ID, EMST_F49B002UA, 256, 4096, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_49f002},
by svn＠coreboot.org
Author: ruik
Date: 2008-06-30 23:45:17 +0200 (Mon, 30 Jun 2008)
New Revision: 3399
Modified:
trunk/util/flashrom/flash.h
trunk/util/flashrom/spi.c
Log:
Mine AMIC flash chip needs 4 bytes RDID. Following patch adds support for that.
Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz>
Acked-by: Peter Stuge <peter(a)stuge.se>
Modified: trunk/util/flashrom/flash.h
===================================================================
--- trunk/util/flashrom/flash.h 2008-06-30 21:38:30 UTC (rev 3398)
+++ trunk/util/flashrom/flash.h 2008-06-30 21:45:17 UTC (rev 3399)
@@ -403,6 +403,7 @@
/* spi.c */
int probe_spi_rdid(struct flashchip *flash);
+int probe_spi_rdid4(struct flashchip *flash);
int probe_spi_res(struct flashchip *flash);
int spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr);
void spi_write_enable();
Modified: trunk/util/flashrom/spi.c
===================================================================
--- trunk/util/flashrom/spi.c 2008-06-30 21:38:30 UTC (rev 3398)
+++ trunk/util/flashrom/spi.c 2008-06-30 21:45:17 UTC (rev 3399)
@@ -44,11 +44,11 @@
return 1;
}
-static int spi_rdid(unsigned char *readarr)
+static int spi_rdid(unsigned char *readarr, int bytes)
{
const unsigned char cmd[JEDEC_RDID_OUTSIZE] = {JEDEC_RDID};
- if (spi_command(JEDEC_RDID_OUTSIZE, JEDEC_RDID_INSIZE, cmd, readarr))
+ if (spi_command(JEDEC_RDID_OUTSIZE, bytes, cmd, readarr))
return 1;
printf_debug("RDID returned %02x %02x %02x.\n", readarr[0], readarr[1], readarr[2]);
return 0;
@@ -80,13 +80,13 @@
spi_command(JEDEC_WRDI_OUTSIZE, JEDEC_WRDI_INSIZE, cmd, NULL);
}
-int probe_spi_rdid(struct flashchip *flash)
+static int probe_spi_rdid_generic(struct flashchip *flash, int bytes)
{
- unsigned char readarr[3];
+ unsigned char readarr[4];
uint32_t manuf_id;
uint32_t model_id;
- if (spi_rdid(readarr))
+ if (spi_rdid(readarr, bytes))
return 0;
if (!oddparity(readarr[0]))
@@ -98,6 +98,10 @@
printf_debug("RDID byte 1 parity violation.\n");
manuf_id = (readarr[0] << 8) | readarr[1];
model_id = readarr[2];
+ if (bytes > 3) {
+ model_id <<= 8;
+ model_id |= readarr[3];
+ }
} else {
manuf_id = readarr[0];
model_id = (readarr[1] << 8) | readarr[2];
@@ -123,12 +127,25 @@
return 0;
}
+int probe_spi_rdid(struct flashchip *flash) {
+ return probe_spi_rdid_generic(flash, 3);
+}
+
+/* support 4 bytes flash ID */
+int probe_spi_rdid4(struct flashchip *flash) {
+
+ /* only some SPI chipsets support 4 bytes commands */
+ if (!((ich7_detected) || (ich9_detected) || (viaspi_detected)))
+ return 0;
+ return probe_spi_rdid_generic(flash, 4);
+}
+
int probe_spi_res(struct flashchip *flash)
{
unsigned char readarr[3];
uint32_t model_id;
- if (spi_rdid(readarr))
+ if (spi_rdid(readarr, 3))
/* We couldn't issue RDID, it's pointless to try RES. */
return 0;
by svn＠coreboot.org
Author: ruik
Date: 2008-06-30 23:38:30 +0200 (Mon, 30 Jun 2008)
New Revision: 3398
Modified:
trunk/util/flashrom/chipset_enable.c
trunk/util/flashrom/flash.h
trunk/util/flashrom/ichspi.c
trunk/util/flashrom/spi.c
Log:
This patch adds support for VIA SPI controller on VT8237S. It is similar with
few documented exceptions to ICH7 SPI controller.
Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz>
Acked-by: Peter Stuge <peter(a)stuge.se>
Modified: trunk/util/flashrom/chipset_enable.c
===================================================================
--- trunk/util/flashrom/chipset_enable.c 2008-06-29 10:57:13 UTC (rev 3397)
+++ trunk/util/flashrom/chipset_enable.c 2008-06-30 21:38:30 UTC (rev 3398)
@@ -187,6 +187,24 @@
void *ich_spibar = NULL;
+static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name) {
+ uint32_t mmio_base;
+
+ mmio_base = (pci_read_long(dev, 0xbc)) << 8;
+ printf_debug("MMIO base at = 0x%x\n", mmio_base);
+ ich_spibar = mmap(NULL, 0x70, PROT_READ | PROT_WRITE, MAP_SHARED,
+ fd_mem, mmio_base);
+
+ if (ich_spibar == MAP_FAILED) {
+ perror("Can't mmap memory using " MEM_DEV);
+ exit(1);
+ }
+
+ printf_debug("0x6c: 0x%04x (CLOCK/DEBUG)\n", *(uint16_t *)(ich_spibar + 0x6c));
+ viaspi_detected = 1;
+ return 0;
+}
+
static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, unsigned long spibar)
{
uint8_t old, new, bbs, buc;
@@ -270,6 +288,7 @@
/* Flag for ICH7 SPI register block */
int ich7_detected = 0;
+int viaspi_detected = 0;
static int enable_flash_ich7(struct pci_dev *dev, const char *name)
{
@@ -660,6 +679,7 @@
{0x1106, 0x8231, "VIA VT8231", enable_flash_vt823x},
{0x1106, 0x3177, "VIA VT8235", enable_flash_vt823x},
{0x1106, 0x3227, "VIA VT8237", enable_flash_vt823x},
+ {0x1106, 0x3372, "VIA VT8237S", enable_flash_vt8237s_spi},
{0x1106, 0x8324, "VIA CX700", enable_flash_vt823x},
{0x1106, 0x0686, "VIA VT82C686", enable_flash_amd8111},
{0x1078, 0x0100, "AMD CS5530(A)", enable_flash_cs5530},
Modified: trunk/util/flashrom/flash.h
===================================================================
--- trunk/util/flashrom/flash.h 2008-06-29 10:57:13 UTC (rev 3397)
+++ trunk/util/flashrom/flash.h 2008-06-30 21:38:30 UTC (rev 3398)
@@ -371,6 +371,7 @@
int chipset_flash_enable(void);
void print_supported_chipsets(void);
extern int ich7_detected;
+extern int viaspi_detected;
extern int ich9_detected;
extern void *ich_spibar;
Modified: trunk/util/flashrom/ichspi.c
===================================================================
--- trunk/util/flashrom/ichspi.c 2008-06-29 10:57:13 UTC (rev 3397)
+++ trunk/util/flashrom/ichspi.c 2008-06-30 21:38:30 UTC (rev 3398)
@@ -41,8 +41,6 @@
#include "flash.h"
#include "spi.h"
-#define MAXDATABYTES 0x40
-
/* ICH9 controller register definition */
#define ICH9_REG_FADDR 0x08 /* 32 Bits */
#define ICH9_REG_FDATA0 0x10 /* 64 Bytes */
@@ -81,11 +79,21 @@
#define SPIS_CDS 0x00000004
#define SPIS_FCERR 0x00000008
+/* VIA SPI is compatible with ICH7, but maxdata
+ to transfer is 16 bytes.
+
+ DATA byte count on ICH7 is 8:13, on VIA 8:11
+
+ bit 12 is port select CS0 CS1
+ bit 13 is FAST READ enable
+ bit 7 is used with fast read and one shot controls CS de-assert?
+*/
+
#define ICH7_REG_SPIC 0x02 /* 16 Bits */
#define SPIC_SCGO 0x0002
#define SPIC_ACS 0x0004
#define SPIC_SPOP 0x0008
-#define SPIC_DS 0x4000
+#define SPIC_DS 0x4000
#define ICH7_REG_SPIA 0x04 /* 32 Bits */
#define ICH7_REG_SPID0 0x08 /* 64 Bytes */
@@ -143,9 +151,9 @@
static int run_opcode(uint8_t nr, OPCODE op, uint32_t offset,
uint8_t datalength, uint8_t * data);
static int ich_spi_read_page(struct flashchip *flash, uint8_t * buf,
- int offset);
+ int offset, int maxdata);
static int ich_spi_write_page(struct flashchip *flash, uint8_t * bytes,
- int offset);
+ int offset, int maxdata);
static int ich_spi_erase_block(struct flashchip *flash, int offset);
OPCODES O_ST_M25P = {
@@ -176,7 +184,7 @@
temp16 = (op->preop[0]);
/* 8:16 Prefix Opcode 2 */
temp16 |= ((uint16_t) op->preop[1]) << 8;
- if (ich7_detected) {
+ if ((ich7_detected) || (viaspi_detected)) {
REGWRITE16(ICH7_REG_PREOP, temp16);
} else if (ich9_detected) {
REGWRITE16(ICH9_REG_PREOP, temp16);
@@ -188,7 +196,7 @@
temp16 |= ((uint16_t) op->opcode[a].spi_type) << (a * 2);
}
- if (ich7_detected) {
+ if ((ich7_detected) || (viaspi_detected)) {
REGWRITE16(ICH7_REG_OPTYPE, temp16);
} else if (ich9_detected) {
REGWRITE16(ICH9_REG_OPTYPE, temp16);
@@ -201,7 +209,7 @@
temp32 |= ((uint32_t) op->opcode[a].opcode) << (a * 8);
}
- if (ich7_detected) {
+ if ((ich7_detected) || (viaspi_detected)) {
REGWRITE32(ICH7_REG_OPMENU, temp32);
} else if (ich9_detected) {
REGWRITE32(ICH9_REG_OPMENU, temp32);
@@ -215,7 +223,7 @@
((uint32_t) op->opcode[a].opcode) << ((a - 4) * 8);
}
- if (ich7_detected) {
+ if ((ich7_detected) || (viaspi_detected)) {
REGWRITE32(ICH7_REG_OPMENU + 4, temp32);
} else if (ich9_detected) {
REGWRITE32(ICH9_REG_OPMENU + 4, temp32);
@@ -225,7 +233,7 @@
}
static int ich7_run_opcode(uint8_t nr, OPCODE op, uint32_t offset,
- uint8_t datalength, uint8_t * data)
+ uint8_t datalength, uint8_t * data, int maxdata)
{
int write_cmd = 0;
int timeout;
@@ -275,7 +283,7 @@
if (datalength != 0) {
temp16 |= SPIC_DS;
- temp16 |= ((uint16_t) ((datalength - 1) & 0x3f)) << 8;
+ temp16 |= ((uint32_t) ((datalength - 1) & (maxdata - 1))) << 8;
}
/* Select opcode */
@@ -431,10 +439,11 @@
uint8_t datalength, uint8_t * data)
{
if (ich7_detected)
- return ich7_run_opcode(nr, op, offset, datalength, data);
- else if (ich9_detected) {
+ return ich7_run_opcode(nr, op, offset, datalength, data, 64);
+ else if (viaspi_detected)
+ return ich7_run_opcode(nr, op, offset, datalength, data, 16);
+ else if (ich9_detected)
return ich9_run_opcode(nr, op, offset, datalength, data);
- }
/* If we ever get here, something really weird happened */
return -1;
@@ -455,7 +464,7 @@
return 0;
}
-static int ich_spi_read_page(struct flashchip *flash, uint8_t * buf, int offset)
+static int ich_spi_read_page(struct flashchip *flash, uint8_t * buf, int offset, int maxdata)
{
int page_size = flash->page_size;
uint32_t remaining = flash->page_size;
@@ -464,8 +473,8 @@
printf_debug("ich_spi_read_page: offset=%d, number=%d, buf=%p\n",
offset, page_size, buf);
- for (a = 0; a < page_size; a += MAXDATABYTES) {
- if (remaining < MAXDATABYTES) {
+ for (a = 0; a < page_size; a += maxdata) {
+ if (remaining < maxdata) {
if (run_opcode
(1, curopcodes->opcode[1],
@@ -478,12 +487,12 @@
} else {
if (run_opcode
(1, curopcodes->opcode[1],
- offset + (page_size - remaining), MAXDATABYTES,
+ offset + (page_size - remaining), maxdata,
&buf[page_size - remaining]) != 0) {
printf_debug("Error reading");
return 1;
}
- remaining -= MAXDATABYTES;
+ remaining -= maxdata;
}
}
@@ -491,7 +500,7 @@
}
static int ich_spi_write_page(struct flashchip *flash, uint8_t * bytes,
- int offset)
+ int offset, int maxdata)
{
int page_size = flash->page_size;
uint32_t remaining = page_size;
@@ -500,8 +509,8 @@
printf_debug("ich_spi_write_page: offset=%d, number=%d, buf=%p\n",
offset, page_size, bytes);
- for (a = 0; a < page_size; a += MAXDATABYTES) {
- if (remaining < MAXDATABYTES) {
+ for (a = 0; a < page_size; a += maxdata) {
+ if (remaining < maxdata) {
if (run_opcode
(0, curopcodes->opcode[0],
offset + (page_size - remaining), remaining,
@@ -513,12 +522,12 @@
} else {
if (run_opcode
(0, curopcodes->opcode[0],
- offset + (page_size - remaining), MAXDATABYTES,
+ offset + (page_size - remaining), maxdata,
&bytes[page_size - remaining]) != 0) {
printf_debug("Error writing");
return 1;
}
- remaining -= MAXDATABYTES;
+ remaining -= maxdata;
}
}
@@ -530,10 +539,15 @@
int i, rc = 0;
int total_size = flash->total_size * 1024;
int page_size = flash->page_size;
+ int maxdata = 64;
+ if (viaspi_detected) {
+ maxdata = 16;
+ }
+
for (i = 0; (i < total_size / page_size) && (rc == 0); i++) {
rc = ich_spi_read_page(flash, (void *)(buf + i * page_size),
- i * page_size);
+ i * page_size, maxdata);
}
return rc;
@@ -545,6 +559,7 @@
int total_size = flash->total_size * 1024;
int page_size = flash->page_size;
int erase_size = 64 * 1024;
+ int maxdata = 64;
spi_disable_blockprotect();
@@ -557,9 +572,12 @@
break;
}
+ if (viaspi_detected) {
+ maxdata = 16;
+ }
for (j = 0; j < erase_size / page_size; j++) {
ich_spi_write_page(flash, (void *)(buf + (i * erase_size) + (j * page_size)),
- (i * erase_size) + (j * page_size));
+ (i * erase_size) + (j * page_size), maxdata);
}
}
Modified: trunk/util/flashrom/spi.c
===================================================================
--- trunk/util/flashrom/spi.c 2008-06-29 10:57:13 UTC (rev 3397)
+++ trunk/util/flashrom/spi.c 2008-06-30 21:38:30 UTC (rev 3398)
@@ -36,8 +36,8 @@
{
if (it8716f_flashport)
return it8716f_spi_command(writecnt, readcnt, writearr, readarr);
- else if (ich7_detected)
- return ich_spi_command(writecnt, readcnt, writearr, readarr);
+ else if ((ich7_detected) || (viaspi_detected))
+ return ich_spi_command(writecnt, readcnt, writearr, readarr);
else if (ich9_detected)
return ich_spi_command(writecnt, readcnt, writearr, readarr);
printf_debug("%s called, but no SPI chipset detected\n", __FUNCTION__);
@@ -360,8 +360,8 @@
{
if (it8716f_flashport)
return it8716f_spi_chip_read(flash, buf);
- else if (ich7_detected)
- return ich_spi_read(flash, buf);
+ else if ((ich7_detected) || (viaspi_detected))
+ return ich_spi_read(flash, buf);
else if (ich9_detected)
return ich_spi_read(flash, buf);
printf_debug("%s called, but no SPI chipset detected\n", __FUNCTION__);
@@ -372,8 +372,8 @@
{
if (it8716f_flashport)
return it8716f_spi_chip_write(flash, buf);
- else if (ich7_detected)
- return ich_spi_write(flash, buf);
+ else if ((ich7_detected) || (viaspi_detected))
+ return ich_spi_write(flash, buf);
else if (ich9_detected)
return ich_spi_write(flash, buf);
printf_debug("%s called, but no SPI chipset detected\n", __FUNCTION__);
by Rudolf Marek
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
Hello,
Mine AMIC flash chip needs 4 bytes RDID. This enables to use the new probing code.
Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz>
Thanks,
Rudolf
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.6 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org
iD8DBQFIaUbC3J9wPJqZRNURAiOuAKDXxFZd/6Y5BpDSdKVHtWVTXLsKTACgjo8+
4s2yb30CJRTUBw1BhYAZz+k=
=pA1g
-----END PGP SIGNATURE-----
by Rudolf Marek
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
Hello,
This patch adds support for VIA SPI controller on VT8237S. It is similar with
few documented exceptions to ICH7 SPI controller.
It has shorter MAXBYTES. And some bits in 0x2 reg are different.
Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz>
Thanks,
Rudolf
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.6 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org
iD8DBQFIaUX33J9wPJqZRNURAv21AKCt3NKAms41Srez4qwBw6yWb/N5tQCgwIWS
eZ+xFo7OcddiBQYg+yzafkE=
=6Q2W
-----END PGP SIGNATURE-----
by jf simon
Hi,
my understanding (sorry if wrong) is that it is not possible to run
linuxbios/corebios on intel platforms, because of lack of documentation.
i am wondering what are the problematic parts.. probably MCH controler DRAM
init? CPU init (microcode, stepping,...)?..
this is sad, as i really want to be able to use corebios..
very recently i have been assigned to porting BIOSEs to our new hardware
plaftorms. so i am working with amibios. it is partitionned into two major
pieces:
-bootblock
-post/main bios
bootblock is a 64K segment, where the CPU is configured and MCH sdram
controller is init (based on code provided by intel). then it branches to
post for devices init, pci enum...
it must be doable technically, to keep the fast, tiny bootblock and jump to
something like corebios . any comments?
i don't know if this is the place to ask but is it possible from a legal
standpoint to modify an amibios prom binary and just keep parts of it, in
case i want to use this scheme in the products of the company i work for?
thanks
eric
by Jensen Qin
Hi Eric,
Sorry for misunderstand you idea.
AMI's bootblock is only a piece of code to do the pre initializition before
POST. It can do nothing to improve the BIOS's function and compability. As
my idea, jump to coreboot from AMI's bootblock may be useless.
I don't think bootblock is a good idea for "C" based BIOS, a good
implementation of BIOS I think should have only a small and smart kernel to
schedule jobs, and others should compiled as drivers and modules to do
initial, run and post. Maybe most of the code, include northbridge,
southbridge, memory init and other chipset related code can write as driver
and modules. I have not see any BIOS archive all of this. In fact, EFI also
implement some of that, they take a way most like Microsoft's driver model,
and EFI also seperate different jobs as modules.
coreboot also take the way like modules as I see, and I think if the
coreboot can make some interface same like linux kernel, then some of
linux kernel driver can porting to coreboot smoothly.
On 6/30/08, jf simon <yeticluns(a)gmail.com> wrote:
> Hi,
> my understanding (sorry if wrong) is that it is not possible to run
> linuxbios/corebios on intel platforms, because of lack of documentation.
> i am wondering what are the problematic parts.. probably MCH controler DRAM
> init? CPU init (microcode, stepping,...)?..
> this is sad, as i really want to be able to use corebios..
>
> very recently i have been assigned to porting BIOSEs to our new hardware
> plaftorms. so i am working with amibios. it is partitionned into two major
> pieces:
> -bootblock
> -post/main bios
>
> bootblock is a 64K segment, where the CPU is configured and MCH sdram
> controller is init (based on code provided by intel). then it branches to
> post for devices init, pci enum...
>
> it must be doable technically, to keep the fast, tiny bootblock and jump to
> something like corebios . any comments?
> i don't know if this is the place to ask but is it possible from a legal
> standpoint to modify an amibios prom binary and just keep parts of it, in
> case i want to use this scheme in the products of the company i work for?
>
>
>
> thanks
> eric
>
>
>
>
>
>
> --
> coreboot mailing list
> coreboot(a)coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
by Star Liu
sorry, i thought about another question about this issue, if intel do not
tell us how to run instructions on its cpu and chipset, how could linux run
on intel architecture? I'm a newbie, do not know firmware programming very
clearly, so ask this silly question here.
thanks!
On Sat, Jun 28, 2008 at 10:51 AM, Tiago Marques <tiagomnm(a)gmail.com> wrote:
> AMD is open to sharing details and helping out - it even has two
> engineers on this mailing list, doing stuff and support. Intel? None.
> No docs, nothing.
>
> Best regards,
> Tiago Marques
>
>
> On 6/28/08, Star Liu <minxinjianxin(a)gmail.com> wrote:
> > I checked the supported motherboard page, and found that support for AMD
> > CPUs is up to quad-core Opteron, while support for Intel CPUs is only up
> to
> > PIII. Is it because we do not have enough time to develop for Intel CPUs
> or
> > we do not like to develop for Intel CPUs? It seems that, in China, Intel
> > CPUs sell better than AMD, I myself have never used AMD cpu computers, so
> > I'm a little curious. :)
> >
> > --
> > -------------------------------------------------
> > Buddha Debian GNU/Linux UEFI/BIOS
> > Homepage: http://starliu.9966.org
> > -------------------------------------------------
> > --
> > coreboot mailing list
> > coreboot(a)coreboot.org
> > http://www.coreboot.org/mailman/listinfo/coreboot
> >
>
--
------------------------------------------------------------------------------------------------------------------------
Homepage: http://starliu.9966.org , about Buddha, x86_64 CPU, Debian
GNU/Linux, UEFI/BIOS
------------------------------------------------------------------------------------------------------------------------
by Peter Stuge
On Fri, Jun 27, 2008 at 06:28:34PM +0200, svn(a)coreboot.org wrote:
> Log:
> * ICH7 SPI support
> * fix some variable names in ichspi.c (Offset -> offset)
> * Dump ICH7 SPI bar with -V
> * Improve error message in case IOPL goes wrong.
Unfortunately this patch broke flashrom on ICH7 not using SPI for at
least one user as reported on IRC just now. :(
Should we just back it out for now? Stefan, do you know what could
cause the problem? Rudolf, maybe you have an idea since you know the
chipset too?
Rudolf - if you have your ICH7 SPI patch in a version that applies to
3392, maybe the reporter should try that?
I asked the reporter to send a message to flashrom@ and I got a
promise about testing patches to fix the problem. :)
//Peter
