coreboot June 2008

coreboot@coreboot.org

75 participants
230 discussions

howto search coreboot mail archives
by 张洪忠zhz 25 Jun '08

25 Jun '08

coreboot，您好！ I want to find if there a patch to intel 852gm chipset, when I browse the mail list archives, I do not know how to make a search with key word '852gm' just like google does. is there a searchable mail archives for coreboot? thanks in advance. 　　　　　　　　致礼！　　　　　　　　张洪忠zhz 　　　　　　　　zhz(a)sh163.net 　　　　　　　　　　2008-06-25

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Support of the new Intel Menlow/Atom platform
by Christophe Niclaes 25 Jun '08

25 Jun '08

I would like to start a design based on the new Intel Atom (formerly Menlow) chipset. For those who don't know what it is, it's a new embedded CPU able to run at 1.7 GHz with only 5W power comsumption. I would like to know if someone in the coreboot community is working on the support for this processor/chipset and what's the development state. Best Regards, Christophe Niclaes --------------------------- Christophe Niclaes Operation Manager cn(a)develtech.com <mailto:cn@develtech.com> --------------------------- DEVELTECH SPRL Centre d'Affaires Dony 53 Rue de Chênée 4031 Angleur Belgium Tel : +32.4.250.54.64. Fax : +32.4.367.00.17. http://www.develtech.com <http://www.develtech.com/>

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Anybody work on Intel 5000P and ESB2 chipset ?
by freevanx 25 Jun '08

25 Jun '08

Hi, I have some board with Intel 5000P and ESB2 chipset. The superio chip is PC8374L of National Semiconductor. It support Intel 5000 series CPU. I'd like to try booting coreboot at this board, when I'm looking for the supported chipset list, nothing was founded. So, I wonder is there anybody working on porting this board? I'd like to try some porting, but I'm confused about coreboot V2 and V3, so I can't decide which version is best to start. Thanks. Best Regards.

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testbios and x86emu
by Scott D. Davilla 24 Jun '08

24 Jun '08

This there someone here willing to answer some questions about testbios and it's usage of x86emu. I'm attempting to port testbios to a bootloader in order to POST the hidden vbios in the AppleTV and gain a standard console frame buffer and video mode control. Thanks Scott

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flashrom: Cache probed id:s
by Peter Stuge 24 Jun '08

24 Jun '08

Please see attached fr.cacheprobe_goto.patch. For those who fiercly advocate against goto; please compare fr.cacheprobe_goto.patch (which I propose to commit) with the mess in fr.cacheprobe_if.patch (which is not signed off and only included for reference) - goto ftw! Timing: flashrom r3386: 1.099s flashrom r3387 (10ms patch): 1.880s flashrom r3387 + this patch: 0.882s May be considered petty to optimize away this one second, but it is quite noticeable, and not neccessary. //Peter

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r3389 - trunk/util/flashrom
by svn＠coreboot.org 24 Jun '08

24 Jun '08

Author: stuge Date: 2008-06-24 10:18:13 +0200 (Tue, 24 Jun 2008) New Revision: 3389 Modified: trunk/util/flashrom/flashchips.c Log: flashrom: Test status OK for ST M50FW040 PROBE READ Per test report from Alex Perez. Thanks Alex! Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/util/flashrom/flashchips.c =================================================================== --- trunk/util/flashrom/flashchips.c 2008-06-24 04:17:14 UTC (rev 3388) +++ trunk/util/flashrom/flashchips.c 2008-06-24 08:18:13 UTC (rev 3389) @@ -113,7 +113,7 @@ {"ST", "M50FLW080A", ST_ID, ST_M50FLW080A, 1024, 64 * 1024, TEST_OK_PREW, probe_stm50flw0x0x, erase_stm50flw0x0x, write_stm50flw0x0x}, {"ST", "M50FLW080B", ST_ID, ST_M50FLW080B, 1024, 64 * 1024, TEST_UNTESTED, probe_stm50flw0x0x, erase_stm50flw0x0x, write_stm50flw0x0x}, {"ST", "M50FW016", ST_ID, ST_M50FW016, 2048, 64 * 1024, TEST_UNTESTED, probe_82802ab, erase_82802ab, write_82802ab}, - {"ST", "M50FW040", ST_ID, ST_M50FW040, 512, 64 * 1024, TEST_UNTESTED, probe_82802ab, erase_82802ab, write_82802ab}, + {"ST", "M50FW040", ST_ID, ST_M50FW040, 512, 64 * 1024, TEST_OK_PR, probe_82802ab, erase_82802ab, write_82802ab}, {"ST", "M50FW080", ST_ID, ST_M50FW080, 1024, 64 * 1024, TEST_UNTESTED, probe_82802ab, erase_82802ab, write_82802ab}, {"ST", "M50LPW116", ST_ID, ST_M50LPW116, 2048, 64 * 1024, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, {"SyncMOS", "S29C31004T", SYNCMOS_ID, S29C31004T, 512, 128, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_49f002},

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r3388 - trunk/util/flashrom
by svn＠coreboot.org 24 Jun '08

24 Jun '08

Author: stuge Date: 2008-06-24 06:17:14 +0200 (Tue, 24 Jun 2008) New Revision: 3388 Modified: trunk/util/flashrom/flashchips.c Log: flashrom: Test status OK for Macronix MX25L8005 PROBE READ ERASE WRITE Per test report from Andrew Paprocki. Thanks Andrew! Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/util/flashrom/flashchips.c =================================================================== --- trunk/util/flashrom/flashchips.c 2008-06-24 02:09:09 UTC (rev 3387) +++ trunk/util/flashrom/flashchips.c 2008-06-24 04:17:14 UTC (rev 3388) @@ -51,7 +51,7 @@ {"Intel", "82802AB", INTEL_ID, 173, 512, 64 * 1024, TEST_OK_PREW, probe_82802ab, erase_82802ab, write_82802ab}, {"Intel", "82802AC", INTEL_ID, 172, 1024, 64 * 1024, TEST_UNTESTED, probe_82802ab, erase_82802ab, write_82802ab}, {"Macronix", "MX25L4005", MX_ID, MX_25L4005, 512, 256, TEST_OK_PREW, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, - {"Macronix", "MX25L8005", MX_ID, MX_25L8005, 1024, 256, TEST_UNTESTED, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"Macronix", "MX25L8005", MX_ID, MX_25L8005, 1024, 256, TEST_OK_PREW, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"Macronix", "MX25L1605", MX_ID, MX_25L1605, 2048, 256, TEST_UNTESTED, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"Macronix", "MX25L3205", MX_ID, MX_25L3205, 4096, 256, TEST_OK_PREW, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"Macronix", "MX29F002", MX_ID, MX_29F002, 256, 64 * 1024, TEST_UNTESTED, probe_29f002, erase_29f002, write_29f002},

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r3387 - trunk/util/flashrom
by svn＠coreboot.org 24 Jun '08

24 Jun '08

Author: stuge Date: 2008-06-24 04:09:09 +0200 (Tue, 24 Jun 2008) New Revision: 3387 Modified: trunk/util/flashrom/jedec.c Log: flashrom: Increase delay in probe_jedec() after Product ID Entry to 10ms We should follow data sheet timing, even if chips have been tested to answer faster in the field. Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/util/flashrom/jedec.c =================================================================== --- trunk/util/flashrom/jedec.c 2008-06-24 01:22:03 UTC (rev 3386) +++ trunk/util/flashrom/jedec.c 2008-06-24 02:09:09 UTC (rev 3387) @@ -100,10 +100,9 @@ myusec_delay(10); *(volatile uint8_t *)(bios + 0x5555) = 0x90; /* Older chips may need up to 100 us to respond. The ATMEL 29C020 - * needs 10 ms according to the data sheet, but it has been tested - * to work reliably with 2 ms. + * needs 10 ms according to the data sheet. */ - myusec_delay(2000); + myusec_delay(10000); /* Read product ID */ id1 = *(volatile uint8_t *)bios;

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flashrom: Slight restructure of SPI probe_ functions
by Peter Stuge 24 Jun '08

24 Jun '08

Patch attached. //Peter

2 2

r3386 - trunk/util/flashrom
by svn＠coreboot.org 24 Jun '08

24 Jun '08

Author: stuge Date: 2008-06-24 03:22:03 +0200 (Tue, 24 Jun 2008) New Revision: 3386 Modified: trunk/util/flashrom/spi.c Log: flashrom: Slight restructure of SPI probe_ functions Preparation for a probe optimization patch. This patch does not change any functionality. spi_probe_rdid was tested to still work on my M57SLI rev 2. The idea is to have error checks return error immediately when something fails, rather than having code inside an if block where the condition tests for success. This means: Less indentation, more clear what the code is checking. Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Ward Vandewege <ward(a)gnu.org> Modified: trunk/util/flashrom/spi.c =================================================================== --- trunk/util/flashrom/spi.c 2008-06-22 18:50:25 UTC (rev 3385) +++ trunk/util/flashrom/spi.c 2008-06-24 01:22:03 UTC (rev 3386) @@ -82,35 +82,41 @@ unsigned char readarr[3]; uint32_t manuf_id; uint32_t model_id; - if (!spi_rdid(readarr)) { - if (!oddparity(readarr[0])) - printf_debug("RDID byte 0 parity violation.\n"); - /* Check if this is a continuation vendor ID */ - if (readarr[0] == 0x7f) { - if (!oddparity(readarr[1])) - printf_debug("RDID byte 1 parity violation.\n"); - manuf_id = (readarr[0] << 8) | readarr[1]; - model_id = readarr[2]; - } else { - manuf_id = readarr[0]; - model_id = (readarr[1] << 8) | readarr[2]; - } - printf_debug("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__, manuf_id, model_id); - if (manuf_id == flash->manufacture_id && - model_id == flash->model_id) { - /* Print the status register to tell the - * user about possible write protection. - */ - spi_prettyprint_status_register(flash); - return 1; - } - /* Test if this is a pure vendor match. */ - if (manuf_id == flash->manufacture_id && - GENERIC_DEVICE_ID == flash->model_id) - return 1; + if (spi_rdid(readarr)) + return 0; + + if (!oddparity(readarr[0])) + printf_debug("RDID byte 0 parity violation.\n"); + + /* Check if this is a continuation vendor ID */ + if (readarr[0] == 0x7f) { + if (!oddparity(readarr[1])) + printf_debug("RDID byte 1 parity violation.\n"); + manuf_id = (readarr[0] << 8) | readarr[1]; + model_id = readarr[2]; + } else { + manuf_id = readarr[0]; + model_id = (readarr[1] << 8) | readarr[2]; } + printf_debug("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__, manuf_id, model_id); + + if (manuf_id == flash->manufacture_id && + model_id == flash->model_id) { + /* Print the status register to tell the + * user about possible write protection. + */ + spi_prettyprint_status_register(flash); + + return 1; + } + + /* Test if this is a pure vendor match. */ + if (manuf_id == flash->manufacture_id && + GENERIC_DEVICE_ID == flash->model_id) + return 1; + return 0; } @@ -118,29 +124,29 @@ { unsigned char readarr[3]; uint32_t model_id; - if (!spi_rdid(readarr)) { - /* Check if RDID returns 0xff 0xff 0xff, then we use RES. */ - if ((readarr[0] != 0xff) || (readarr[1] != 0xff) || - (readarr[2] != 0xff)) - return 0; - } else { + + if (spi_rdid(readarr)) /* We couldn't issue RDID, it's pointless to try RES. */ return 0; - } - if (!spi_res(readarr)) { - model_id = readarr[0]; - printf_debug("%s: id 0x%x\n", __FUNCTION__, model_id); - if (model_id == flash->model_id) { - /* Print the status register to tell the - * user about possible write protection. - */ - spi_prettyprint_status_register(flash); - return 1; - } - } + /* Check if RDID returns 0xff 0xff 0xff, then we use RES. */ + if ((readarr[0] != 0xff) || (readarr[1] != 0xff) || + (readarr[2] != 0xff)) + return 0; - return 0; + if (spi_res(readarr)) + return 0; + + model_id = readarr[0]; + printf_debug("%s: id 0x%x\n", __FUNCTION__, model_id); + if (model_id != flash->model_id) + return 0; + + /* Print the status register to tell the + * user about possible write protection. + */ + spi_prettyprint_status_register(flash); + return 1; } uint8_t spi_read_status_register()

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coreboot June 2008