coreboot June 2008

coreboot@coreboot.org

75 participants
230 discussions

-v2[PATCH] i82830 multiple so-dimm support
by Joseph Smith 22 Jun '08

22 Jun '08

This patch allows support for booting multiple so-dimms, single or double sided. Signed-off-by: Joseph Smith <joe(a)settoplinux.org> -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

2 3

r3380 - trunk/coreboot-v2/src/northbridge/intel/i82830
by svn＠coreboot.org 22 Jun '08

22 Jun '08

Author: linux_junkie Date: 2008-06-22 06:22:46 +0200 (Sun, 22 Jun 2008) New Revision: 3380 Modified: trunk/coreboot-v2/src/northbridge/intel/i82830/raminit.c Log: This patch allows support for multiple so-dimms, single or double sided. Signed-off-by: Joseph Smith <joe(a)settoplinux.org> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/coreboot-v2/src/northbridge/intel/i82830/raminit.c =================================================================== --- trunk/coreboot-v2/src/northbridge/intel/i82830/raminit.c 2008-06-22 02:04:49 UTC (rev 3379) +++ trunk/coreboot-v2/src/northbridge/intel/i82830/raminit.c 2008-06-22 04:22:46 UTC (rev 3380) @@ -53,7 +53,7 @@ * 0x2 for Refresh interval 7.8 us for 133MHz * 0x7 /* Refresh interval 128 Clocks. (Fast Refresh Mode) */ -#define RAM_COMMAND_REFRESH 0x2 +#define RAM_COMMAND_REFRESH 0x1 /* DRC[6:4] - SDRAM Mode Select (SMS). */ #define RAM_COMMAND_SELF_REFRESH 0x0 @@ -76,7 +76,7 @@ uint32_t addr_offset) { int i; - uint8_t reg8, reg8_2 = 0; + uint8_t dimm_start, dimm_end; uint32_t reg32; /* Configure the RAM command. */ @@ -84,28 +84,27 @@ /* Clear bits 29, 10-8, 6-4. */ reg32 &= 0xdffff88f; reg32 |= command << 4; - /* If RAM_COMMAND_NORMAL set the refresh mode and IC bit. */ - if (command == RAM_COMMAND_NORMAL) - reg32 |= ((RAM_COMMAND_REFRESH << 8) | (RAM_COMMAND_IC << 29)); pci_write_config32(ctrl->d0, DRC, reg32); - /* RAM_COMMAND_NORMAL affects only the memory controller and - doesn't need to be "sent" to the DIMMs. */ - /* if (command == RAM_COMMAND_NORMAL) return; */ + /* Send the ram command to each row of memory. + * (DIMM_SOCKETS * 2) is the maximum number of rows possible. + * Note: Each DRB defines the upper boundary address of + * each SDRAM row in 32-MB granularity. + */ + dimm_start = 0; - PRINT_DEBUG(" Sending RAM command 0x"); - PRINT_DEBUG_HEX32(reg32); - PRINT_DEBUG(" to 0x"); - PRINT_DEBUG_HEX32(0 + addr_offset); - PRINT_DEBUG("\r\n"); - - /* NOTE: Dual-sided ready. */ - read32(0 + addr_offset); - for (i = 0; i < 4; i++) { - reg8 = pci_read_config8(ctrl->d0, DRB + i); - if (reg8 != reg8_2) - read32(reg8 * 32 * 1024 * 1024); - reg8_2 = reg8; + for (i = 0; i < (DIMM_SOCKETS * 2); i++) { + dimm_end = pci_read_config8(ctrl->d0, DRB + i); + if (dimm_end > dimm_start) { + PRINT_DEBUG(" Sending RAM command 0x"); + PRINT_DEBUG_HEX32(reg32); + PRINT_DEBUG(" to 0x"); + PRINT_DEBUG_HEX32((dimm_start * 32 * 1024 * 1024) + addr_offset); + PRINT_DEBUG("\r\n"); + read32((dimm_start * 32 * 1024 * 1024) + addr_offset); + } + /* Set the start of the next DIMM. */ + dimm_start = dimm_end; } } @@ -316,38 +315,28 @@ value = spd_read_byte(device, 5); if (value == 1) { - switch (dra) { - case 2: /* 2KB */ - dra = 0xF0; - break; - case 4: /* 4KB */ - dra = 0xF1; - break; - case 8: /* 8KB */ - dra = 0xF2; - break; - case 16: /* 16KB */ - dra = 0xF3; - break; - default: + if (dra == 2) { + dra = 0xF0; /* 2KB */ + } else if (dra == 4) { + dra = 0xF1; /* 4KB */ + } else if (dra == 8) { + dra = 0xF2; /* 8KB */ + } else if (dra == 16) { + dra = 0xF3; /* 16KB */ + } else { print_err("Page size not supported\r\n"); die("HALT\r\n"); } } else if (value == 2) { - switch (dra) { - case 2: /* 2KB */ - dra = 0x00; - break; - case 4: /* 4KB */ - dra = 0x11; - break; - case 8: /* 8KB */ - dra = 0x22; - break; - case 16: /* 16KB */ - dra = 0x33; - break; - default: + if (dra == 2) { + dra = 0x00; /* 2KB */ + } else if (dra == 4) { + dra = 0x11; /* 4KB */ + } else if (dra == 8) { + dra = 0x22; /* 8KB */ + } else if (dra == 16) { + dra = 0x33; /* 16KB */ + } else { print_err("Page size not supported\r\n"); die("HALT\r\n"); } @@ -471,6 +460,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) { int i; + uint32_t reg32; /* 0. Wait until power/voltages and clocks are stable (200us). */ udelay(200); @@ -503,6 +493,12 @@ do_ram_command(ctrl, RAM_COMMAND_NORMAL, 0); udelay(1); + /* 6. Enable refresh and Set initialization complete. */ + PRINT_DEBUG("RAM Enable 6: Enable Refresh and IC\r\n"); + reg32 = pci_read_config32(ctrl->d0, DRC); + reg32 |= ((RAM_COMMAND_REFRESH << 8) | (RAM_COMMAND_IC << 29)); + pci_write_config32(ctrl->d0, DRC, reg32); + PRINT_DEBUG("Northbridge following SDRAM init:\r\n"); DUMPNORTH(); }

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RCA RM4100 vs Thomson IP1000
by Joseph Smith 22 Jun '08

22 Jun '08

Need some suggestions/help. I think I figured out why coreboot for RCA RM4100 will not work on the Thomson IP1000. The only difference is that the IP1000 only has 64MB of onboard memory and the RCA RM4100 has 128MB of onboard memory. coreboot chokes because there is no onboard spd, so the spd settings are manually set via an array (see spd_table.h). If you want to see a high res pic of the boards, they are on my site: www.settoplinux.org So I guess with that being the only difference, should we create a new target for the Thomson IP1000 ??? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

3 13

r3379 - trunk/util/flashrom
by svn＠coreboot.org 22 Jun '08

22 Jun '08

Author: stuge Date: 2008-06-22 04:04:49 +0200 (Sun, 22 Jun 2008) New Revision: 3379 Modified: trunk/util/flashrom/flashchips.c Log: flashrom: Update test status to TEST_OK_PREW for ST M50FLW080A and SST49LF008A Many thanks to Julio Cesar Costa for the test report! Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/util/flashrom/flashchips.c =================================================================== --- trunk/util/flashrom/flashchips.c 2008-06-22 02:00:39 UTC (rev 3378) +++ trunk/util/flashrom/flashchips.c 2008-06-22 02:04:49 UTC (rev 3379) @@ -90,7 +90,7 @@ {"SST", "SST49LF003A/B", SST_ID, SST_49LF003A, 384, 64 * 1024, TEST_UNTESTED, probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub}, {"SST", "SST49LF004A/B", SST_ID, SST_49LF004A, 512, 64 * 1024, TEST_OK_PREW, probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub}, {"SST", "SST49LF004C", SST_ID, SST_49LF004C, 512, 4 * 1024, TEST_UNTESTED, probe_49lfxxxc, erase_49lfxxxc, write_49lfxxxc}, - {"SST", "SST49LF008A", SST_ID, SST_49LF008A, 1024, 64 * 1024, TEST_OK_PR, probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub}, + {"SST", "SST49LF008A", SST_ID, SST_49LF008A, 1024, 64 * 1024, TEST_OK_PREW, probe_sst_fwhub, erase_sst_fwhub, write_sst_fwhub}, {"SST", "SST49LF008C", SST_ID, SST_49LF008C, 1024, 4 * 1024, TEST_UNTESTED, probe_49lfxxxc, erase_49lfxxxc, write_49lfxxxc}, {"SST", "SST49LF016C", SST_ID, SST_49LF016C, 2048, 4 * 1024, TEST_UNTESTED, probe_49lfxxxc, erase_49lfxxxc, write_49lfxxxc}, {"SST", "SST49LF020A", SST_ID, SST_49LF020A, 256, 16 * 1024, TEST_UNTESTED, probe_jedec, erase_49lf040, write_49lf040}, @@ -116,7 +116,7 @@ {"ST", "M29W040B", ST_ID, ST_M29W040B, 512, 64 * 1024, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, {"ST", "M50FLW040A", ST_ID, ST_M50FLW040A, 512, 64 * 1024, TEST_UNTESTED, probe_stm50flw0x0x, erase_stm50flw0x0x, write_stm50flw0x0x}, {"ST", "M50FLW040B", ST_ID, ST_M50FLW040B, 512, 64 * 1024, TEST_UNTESTED, probe_stm50flw0x0x, erase_stm50flw0x0x, write_stm50flw0x0x}, - {"ST", "M50FLW080A", ST_ID, ST_M50FLW080A, 1024, 64 * 1024, TEST_UNTESTED, probe_stm50flw0x0x, erase_stm50flw0x0x, write_stm50flw0x0x}, + {"ST", "M50FLW080A", ST_ID, ST_M50FLW080A, 1024, 64 * 1024, TEST_OK_PREW, probe_stm50flw0x0x, erase_stm50flw0x0x, write_stm50flw0x0x}, {"ST", "M50FLW080B", ST_ID, ST_M50FLW080B, 1024, 64 * 1024, TEST_UNTESTED, probe_stm50flw0x0x, erase_stm50flw0x0x, write_stm50flw0x0x}, {"ST", "M50FW016", ST_ID, ST_M50FW016, 2048, 64 * 1024, TEST_UNTESTED, probe_82802ab, erase_82802ab, write_82802ab}, {"ST", "M50FW040", ST_ID, ST_M50FW040, 512, 64 * 1024, TEST_UNTESTED, probe_82802ab, erase_82802ab, write_82802ab},

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r3378 - trunk/util/flashrom
by svn＠coreboot.org 22 Jun '08

22 Jun '08

Author: stuge Date: 2008-06-22 04:00:39 +0200 (Sun, 22 Jun 2008) New Revision: 3378 Modified: trunk/util/flashrom/Makefile Log: flashrom: Some Makefile cleaning Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/util/flashrom/Makefile =================================================================== --- trunk/util/flashrom/Makefile 2008-06-21 04:39:17 UTC (rev 3377) +++ trunk/util/flashrom/Makefile 2008-06-22 02:00:39 UTC (rev 3378) @@ -46,11 +46,11 @@ $(CC) -c $(CFLAGS) $(SVNDEF) $(CPPFLAGS) $< -o $@ clean: - rm -f *.o *~ + rm -f $(PROGRAM) *.o *~ distclean: clean - rm -f $(PROGRAM) .dependencies - + rm -f .dependencies + dep: @$(CC) -MM *.c > .dependencies @@ -68,11 +68,10 @@ @rm -f .test.c .test install: $(PROGRAM) - $(INSTALL) flashrom $(PREFIX)/sbin + $(INSTALL) $(PROGRAM) $(PREFIX)/sbin mkdir -p $(PREFIX)/share/man/man8 $(INSTALL) $(PROGRAM).8 $(PREFIX)/share/man/man8 .PHONY: all clean distclean dep pciutils -include .dependencies -

1 0

r49 - in trunk/filo-0.5: drivers include main
by svn＠coreboot.org 22 Jun '08

22 Jun '08

Author: stuge Date: 2008-06-22 03:53:33 +0200 (Sun, 22 Jun 2008) New Revision: 49 Modified: trunk/filo-0.5/drivers/ide.c trunk/filo-0.5/include/pci.h trunk/filo-0.5/main/pci.c Log: FILO: find_ide_controller_compat(): Skip over PCI devices in native mode find_ide_controller_compat() would assume that all controllers were using legacy ports, even SATA and IDE controllers in native PCI mode. On a system with these PCI ids: pci_init: 00:0f.0 1106:3149 0101 8f /* SATA native with 2 channels */ pci_init: 00:0f.1 1106:0571 0101 8a /* PATA legacy with 2 channels */ The SATA device has io resources above 0x1000. The PATA device is without proper io resources, but is configured to listen on the first and second legacy IDE ports 0x1f0 and 0x170. find_ide_controller_compat() would incorrectly assume that the SATA device used ports 0x1f0 and 0x170, and that the PATA device used 0x1e8 and 0x168. This teaches find_ide_controller_compat() to skip devices in native mode. Tested to not change anything on PATA-only boards and tested to allow SATA+PATA boards to correctly boot from PATA drives. Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Bari Ari <bari(a)onelabs.com> Modified: trunk/filo-0.5/drivers/ide.c =================================================================== --- trunk/filo-0.5/drivers/ide.c 2008-05-03 15:03:45 UTC (rev 48) +++ trunk/filo-0.5/drivers/ide.c 2008-06-22 01:53:33 UTC (rev 49) @@ -1078,8 +1078,13 @@ static int find_ide_controller_compat(struct controller *ctrl, int index) { +#ifdef SUPPORT_PCI + int skip, i, pci_index = index / 2; + struct pci_dev *dev; +#else if (index >= IDE_MAX_CONTROLLERS) return -1; +#endif #ifdef PCMCIA_CF if (index == 2) { ctrl->cmd_base = 0x1e0; @@ -1087,6 +1092,31 @@ return 0; } #endif +#ifdef SUPPORT_PCI + /* skip any SATA and PATA PCI controllers in native mode */ + for (skip = i = 0; i < pci_index && index; i++) { + /* look for i:th ata (IDE/other storage really) device */ + dev = pci_find_ata_device(-1, -1, -1, i); + if (!dev) + break; + /* only IDE can be in compat mode so skip all others */ + if (0x0101 != dev->devclass) { + /* other storage (SATA) always has two channels */ + skip += 2; + continue; + } + /* primary in native mode? then skip it. */ + if (1 == (dev->prog_if & 1)) + skip++; + /* secondary in native mode? then skip it. */ + if (index && 4 == (dev->prog_if & 4)) + skip++; + } + index = skip <= index ? index - skip : 0; + debug("skipping %d native PCI controllers, new index=%d\n", skip, index); + if (index >= IDE_MAX_CONTROLLERS) + return -1; +#endif ctrl->cmd_base = ide_base[index]; ctrl->ctrl_base = ide_base[index] + IDE_REG_EXTENDED_OFFSET; return 0; Modified: trunk/filo-0.5/include/pci.h =================================================================== --- trunk/filo-0.5/include/pci.h 2008-05-03 15:03:45 UTC (rev 48) +++ trunk/filo-0.5/include/pci.h 2008-06-22 01:53:33 UTC (rev 49) @@ -32,5 +32,6 @@ void pci_init(void); struct pci_dev *pci_find_device(int vendor, int device, int devclass, int prog_if, int index); +struct pci_dev *pci_find_ata_device(int vendor, int device, int prog_if, int index); #endif /* PCI_H */ Modified: trunk/filo-0.5/main/pci.c =================================================================== --- trunk/filo-0.5/main/pci.c 2008-05-03 15:03:45 UTC (rev 48) +++ trunk/filo-0.5/main/pci.c 2008-06-22 01:53:33 UTC (rev 49) @@ -107,3 +107,20 @@ } return NULL; } + +struct pci_dev *pci_find_ata_device(int vendor, int device, int prog_if, int index) +{ + struct pci_dev *dev; + + for (dev = dev_list; dev < dev_list + n_devs; dev++) { + if (vendor < 0 || vendor==dev->vendor) + if (device < 0 || device==dev->device) + if (0x0180 == dev->devclass || 0x0101 == dev->devclass) + if (prog_if < 0 || prog_if==dev->prog_if) { + if (index == 0) + return dev; + index--; + } + } + return NULL; +}

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Updating Mailman
by Gregg C Levine 21 Jun '08

21 Jun '08

Hello! Ron, Stefan, everyone: I am currently subscribed via the address in my signature. And as it happens my Google Mail address. I chose to do that so I could work on different aspects of Coreboot, and post the appropriate contents of build logs and other necessary text files to the list so as to properly describe any errors. However every time a message arrives I need to check it to see if it was for my signature address or my Google Mail one, and that's done by reading the headers. The version of Mailman being used by GNU itself for its lists actually displays the subscribed address as part of its displayed items in the To: and From: blocks. Can this be done for the version used on this list? Incidentally this happens every time my mail program collapses and retrieves everything from both locations. -- Gregg C Levine hansolofalcon(a)worldnet.att.net "The Force will be with you always." Obi-Wan Kenobi

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flashrom verify fails, CK804, MCP55
by Tiago Marques 21 Jun '08

21 Jun '08

On two boards, one MCP55 based and another CK804, if I flash the proprietary BIOS with: flasrom -wv bios.bin Verification fails and if I try to boot, it doesn't. Have to flash the BIOS in another board based on K8T890 that I have. In that one all works fine, with both BIOS chips I have - one winbond and a PMC. Haven't tried flashing coreboot due to lack of support. Since the chipsets are support, this isn't supposed to happen, right? Best regards, Tiago Marques On 1/27/08, Stefan Reinauer <stepan(a)coresystems.de> wrote: > * Tiago Marques <tiagomnm(a)gmail.com> [080127 16:21]: > > Hi. > > Both failed, tried with two different BIOS chips. > > Flashing with AWDFlash works fine though. > > Had to flash it again in a VIA K8T890 board, which works flawlessly. > > Any ideas, fix? > > What's the problem? > > -- > coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. > Tel.: +49 761 7668825 • Fax: +49 761 7664613 > Email: info(a)coresystems.de • http://www.coresystems.de/ > Registergericht: Amtsgericht Freiburg • HRB 7656 > Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 >

4 13

r3377 - trunk/util/flashrom
by svn＠coreboot.org 21 Jun '08

21 Jun '08

Author: stuge Date: 2008-06-21 06:39:17 +0200 (Sat, 21 Jun 2008) New Revision: 3377 Modified: trunk/util/flashrom/Makefile Log: flashrom: Fix OBJS in Makefile to compile stm50flw0x0x.c like the others Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/util/flashrom/Makefile =================================================================== --- trunk/util/flashrom/Makefile 2008-06-21 04:23:10 UTC (rev 3376) +++ trunk/util/flashrom/Makefile 2008-06-21 04:39:17 UTC (rev 3377) @@ -24,7 +24,7 @@ LDFLAGS += -L/usr/local/lib endif -OBJS = chipset_enable.o board_enable.o udelay.o jedec.o stm50flw0x0x.c \ +OBJS = chipset_enable.o board_enable.o udelay.o jedec.o stm50flw0x0x.o \ sst28sf040.o am29f040b.o mx29f002.o sst39sf020.o m29f400bt.o \ w49f002u.o 82802ab.o msys_doc.o pm49fl00x.o sst49lf040.o \ sst49lfxxxc.o sst_fwhub.o layout.o cbtable.o flashchips.o \

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r3376 - trunk/util/flashrom
by svn＠coreboot.org 21 Jun '08

21 Jun '08

Author: stuge Date: 2008-06-21 06:23:10 +0200 (Sat, 21 Jun 2008) New Revision: 3376 Modified: trunk/util/flashrom/flashchips.c Log: flashrom: Uppercase AMIC since that's what they write in datasheets. Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/util/flashrom/flashchips.c =================================================================== --- trunk/util/flashrom/flashchips.c 2008-06-21 01:02:20 UTC (rev 3375) +++ trunk/util/flashrom/flashchips.c 2008-06-21 04:23:10 UTC (rev 3376) @@ -44,9 +44,9 @@ {"Atmel", "AT49F002(N)", ATMEL_ID, AT_49F002N, 256, 256, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, {"Atmel", "AT49F002(N)T", ATMEL_ID, AT_49F002NT, 256, 256, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, {"Atmel", "AT25DF321", ATMEL_ID, AT_25DF321, 4096, 256, TEST_OK_PREW, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, - {"Amic Technology","A25L40P", AMIC_ID, AMIC_A25L40P, 512, 256, TEST_UNTESTED, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, + {"AMIC Technology","A25L40P", AMIC_ID, AMIC_A25L40P, 512, 256, TEST_UNTESTED, probe_spi_rdid, spi_chip_erase_c7, spi_chip_write, spi_chip_read}, {"AMIC Technology","A49LF040A", AMIC_ID_NOPREFIX, AMIC_A49LF040A, 512, 64 * 1024, TEST_OK_PREW, probe_49fl00x, erase_49fl00x, write_49fl00x}, - {"Amic Technology","A29040B", AMIC_ID_NOPREFIX, AMIC_A29040B, 512, 64 * 1024, TEST_OK_PR, probe_29f040b, erase_29f040b, write_29f040b}, + {"AMIC Technology","A29040B", AMIC_ID_NOPREFIX, AMIC_A29040B, 512, 64 * 1024, TEST_OK_PR, probe_29f040b, erase_29f040b, write_29f040b}, {"EMST", "F49B002UA", EMST_ID, EMST_F49B002UA, 256, 4096, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_49f002}, {"EON", "EN29F002(A)(N)B", EON_ID, EN_29F002B, 256, 256, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec}, {"EON", "EN29F002(A)(N)T", EON_ID, EN_29F002T, 256, 256, TEST_UNTESTED, probe_jedec, erase_chip_jedec, write_jedec},

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coreboot June 2008