coreboot June 2008

coreboot@coreboot.org

75 participants
230 discussions

Xorg.conf for LX
by ron minnich 04 Jun '08

04 Jun '08

I've got this lovely LX framebuffer but am a little unclear on how to set up my X11 config. any hints welcome. I know that newer Xorg just sorta "gets it right" but my ubuntu appears not to be that new. ron

3 4

buildrom
by qchwu 04 Jun '08

04 Jun '08

The "buildrom" is downloaded with SVN. When i build the ROM for AMD DB800 with FILO as payload,two error appear. 1./bios/buildrom/buildrom-devel/work/coreboot/svn/targets/: the file or folder is not found. 2.[/bios/buildrom/buildrom-devel/work/coreboot/stamps/.configured-db800] error 127. After the make,i check the folder "/bios/buildrom/buildrom-devel/work/coreboot/svn/",the "targets"floder is not existing.The "SVN" folder and it's sub-folder are build by make,and can be cleaned by "make distclean".why the "targets"folder is not created by the make process? When i check the "/bios/buildrom/buildrom-devel/work/coreboot/stamps",the ".configured-db800 " is not existing. here is the file? How can i clear the errors? Thanks! chenghu

2 1

LinuxTag 2008 Status
by Joseph Smith 04 Jun '08

04 Jun '08

How is LinuxTag 2008 going Peter, Paul, and Carl-Daniel? Are you getting alot of people excited about coreboot? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

6 15

r689 - coreboot-v3/southbridge/amd/cs5536
by svn＠coreboot.org 04 Jun '08

04 Jun '08

Author: rminnich Date: 2008-06-04 16:36:35 +0200 (Wed, 04 Jun 2008) New Revision: 689 Modified: coreboot-v3/southbridge/amd/cs5536/cs5536.c coreboot-v3/southbridge/amd/cs5536/dts Log: This change adds some debug prints, and a comment warning to dts on cs5536. Most importantly it fixes a simple programming error which made it so most of the sets on the USB were not doing anything. The bug is also in V2. With this fix, the DBE62 USB ports all work! If someone clones the fix to V2, it will also fix V2. Or, we can just convince you to move forward to V3 :-) Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: coreboot-v3/southbridge/amd/cs5536/cs5536.c =================================================================== --- coreboot-v3/southbridge/amd/cs5536/cs5536.c 2008-06-03 15:22:16 UTC (rev 688) +++ coreboot-v3/southbridge/amd/cs5536/cs5536.c 2008-06-04 14:36:35 UTC (rev 689) @@ -395,18 +395,19 @@ } } -#define HCCPARAMS 0x08 -#define IPREG04 0xA0 +/* the /sizeof(u32) is to convert byte offsets into u32 offsets */ +#define HCCPARAMS (0x08/sizeof(u32)) +#define IPREG04 (0xA0/sizeof(u32)) #define USB_HCCPW_SET (1 << 1) #define UOCCAP 0x00 #define APU_SET (1 << 15) -#define UOCMUX 0x04 +#define UOCMUX (0x04/sizeof(u32)) #define PMUX_HOST 0x02 #define PMUX_DEVICE 0x03 #define PUEN_SET (1 << 2) -#define UDCDEVCTL 0x404 +#define UDCDEVCTL (0x404/sizeof(u32)) #define UDC_SD_SET (1 << 10) -#define UOCCTL 0x0C +#define UOCCTL (0x0C/sizeof(u32)) #define PADEN_SET (1 << 7) /** @@ -445,6 +446,8 @@ if (dev) { bar = (u32 *) pci_read_config32(dev, PCI_BASE_ADDRESS_0); + printk(BIOS_DEBUG, "UOCMUX is %x\n", *(bar + UOCMUX)); + *(bar + UOCMUX) &= PUEN_SET; /* Host or Device? */ @@ -463,6 +466,7 @@ *(bar + UOCCAP) |= sb->pph; } printk(BIOS_DEBUG, "UOCCAP is %x\n", *(bar + UOCCAP)); + printk(BIOS_DEBUG, "UOCMUX is %x\n", *(bar + UOCMUX)); } @@ -489,6 +493,8 @@ } } + printk(BIOS_DEBUG, "UOCCTL is %x\n", *(bar + UOCCTL)); + /* Disable virtual PCI UDC and OTG headers. The kernel never * sees a header for this device. It used to provide an OS * visible device, but that was defeatured. There are still Modified: coreboot-v3/southbridge/amd/cs5536/dts =================================================================== --- coreboot-v3/southbridge/amd/cs5536/dts 2008-06-03 15:22:16 UTC (rev 688) +++ coreboot-v3/southbridge/amd/cs5536/dts 2008-06-04 14:36:35 UTC (rev 689) @@ -66,6 +66,10 @@ pph = "0"; /* 0:off, xxxx:overcurrent setting, e.g. 0x3FEA. * See CS5536 - Data Book (pages 380-381). + * And don't just set this to "1". You have to set it + * to values that make sense for the register. Do not set this + * for your mainboard unless you have made sure of the register + * settings! */ enable_USBP4_overcurrent = "0";

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Epia-CN USB Does Not init Properly with LAB
by bari 04 Jun '08

04 Jun '08

The epia-cn works fine with FILO, except for the lack of VGA console. X however works fine. When you drop out of X the screen is left with vertical bars until X restarts. The PS2 keyboard is still responsive when out of X. The epia-cn does not init the usb controler properly with LAB. Does anyone have any idea what the kernel in LAB may be getting wrong? Serial debug output with LAB: http://pastebin.com/m3320b15f The kernel is built with buildrom along with kexec and the initrd. Linux version 2.6.22.2BuildROML-A-BV1.0 Coreboot is used to build coreboot and the config.lb uses the elf.lzma from buildrom as a payload. # cat interrupts CPU0 0: 173636 XT-PIC-XT timer 2: 0 XT-PIC-XT cascade 4: 65 XT-PIC-XT serial 9: 0 XT-PIC-XT acpi 10: 100000 XT-PIC-XT uhci_hcd:usb3, uhci_hcd:usb4 11: 100000 XT-PIC-XT uhci_hcd:usb1, uhci_hcd:usb2 14: 1 XT-PIC-XT ide0 15: 1 XT-PIC-XT ide1 NMI: 0 LOC: 0 ERR: 0 MIS: 0 # cat ioports 0000-001f : dma1 0020-0021 : pic1 0040-0043 : timer0 0050-0053 : timer1 0060-006f : keyboard 0080-008f : dma page reg 00a0-00a1 : pic2 00c0-00df : dma2 00f0-00ff : fpu 0170-0177 : 0000:00:0f.0 0170-0177 : ide1 01f0-01f7 : 0000:00:0f.0 01f0-01f7 : ide0 0376-0376 : 0000:00:0f.0 0376-0376 : ide1 03f6-03f6 : 0000:00:0f.0 03f6-03f6 : ide0 03f8-03ff : serial 0400-047f : pnp 00:02 0400-0403 : ACPI PM1a_EVT_BLK 0404-0405 : ACPI PM1a_CNT_BLK 0408-040b : ACPI PM_TMR 0410-0415 : ACPI CPU throttle 0420-0423 : ACPI GPE0_BLK 0500-050f : pnp 00:02 0500-0507 : vt596_smbus 0cf8-0cff : PCI conf1 1000-10ff : 0000:00:11.5 1400-14ff : 0000:00:12.0 1400-14ff : via-rhine 1800-181f : 0000:00:10.0 1800-181f : uhci_hcd 1820-183f : 0000:00:10.1 1820-183f : uhci_hcd 1840-185f : 0000:00:10.2 1840-185f : uhci_hcd 1860-187f : 0000:00:10.3 1860-187f : uhci_hcd 1880-188f : 0000:00:0f.0 1880-1887 : ide0 1888-188f : ide1 d000-dfff : PCI Bus #01 # cat devices Character devices: 1 mem 2 pty 3 ttyp 4 /dev/vc/0 4 tty 4 ttyS 5 /dev/tty 5 /dev/console 5 /dev/ptmx 7 vcs 10 misc 13 input 128 ptm 136 pts 180 usb 189 usb_device 254 usb_endpoint Block devices: 1 ramdisk 3 ide0 7 loop 8 sd 22 ide1 65 sd 66 sd 67 sd 68 sd 69 sd 70 sd 71 sd 128 sd 129 sd 130 sd 131 sd 132 sd 133 sd 134 sd 135 sd # cat mounts rootfs / rootfs rw 0 0 proc /proc proc rw 0 0 usbfs /proc/bus/usb usbfs rw 0 0 # cat meminfo MemTotal: 907084 kB MemFree: 902840 kB Buffers: 0 kB Cached: 484 kB SwapCached: 0 kB Active: 352 kB Inactive: 256 kB SwapTotal: 0 kB SwapFree: 0 kB Dirty: 0 kB Writeback: 0 kB AnonPages: 144 kB Mapped: 172 kB Slab: 0 kB SReclaimable: 0 kB SUnreclaim: 0 kB PageTables: 36 kB NFS_Unstable: 0 kB Bounce: 0 kB CommitLimit: 453540 kB Committed_AS: 412 kB VmallocTotal: 122576 kB VmallocUsed: 0 kB VmallocChunk: 122576 kB # cat stat cpu 1 0 106 75454 0 210 28 0 cpu0 1 0 106 75454 0 210 28 0 intr 389895 189491 0 0 0 402 0 0 0 0 0 100000 100000 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ctxt 6514 btime 1212515072 processes 859 procs_running 2 procs_blocked 0 # cat version Linux version 2.6.22.2BuildROML-A-BV1.0 (ly@ly-d) (gcc version 4.1.3 20070929 (prerelease) (Ubuntu 4.1.2-16ubuntu2)) #8 PREEMPT Tue Jun 3 12:18:28 CDT 2008 -Bari

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memtest x86 64-bit issues
by Joseph Smith 03 Jun '08

03 Jun '08

Hello, I can't seem to build memtest on my 64-bit version of FC8. Can someone just send me a 32-bit memtest elf file? Here is the error: [joe@localhost memtest86-3.4]$ make as -o head.o head.s head.S: Assembler messages: head.S:44: Error: 8-byte relocation cannot be applied to 4-byte field head.S:53: Error: 8-byte relocation cannot be applied to 4-byte field head.S:56: Error: 8-byte relocation cannot be applied to 4-byte field head.S:57: Error: 8-byte relocation cannot be applied to 4-byte field head.S:58: Error: 8-byte relocation cannot be applied to 4-byte field head.S:59: Error: 8-byte relocation cannot be applied to 4-byte field head.S:73: Error: 8-byte relocation cannot be applied to 4-byte field head.S:76: Error: 8-byte relocation cannot be applied to 4-byte field head.S:77: Error: 8-byte relocation cannot be applied to 4-byte field head.S:83: Error: 8-byte relocation cannot be applied to 4-byte field head.S:89: Error: 8-byte relocation cannot be applied to 4-byte field head.S:98: Error: 8-byte relocation cannot be applied to 4-byte field head.S:105: Error: 8-byte relocation cannot be applied to 4-byte field head.S:107: Error: 8-byte relocation cannot be applied to 4-byte field head.S:115: Error: 8-byte relocation cannot be applied to 4-byte field head.S:123: Error: 8-byte relocation cannot be applied to 4-byte field head.S:131: Error: 8-byte relocation cannot be applied to 4-byte field head.S:139: Error: 8-byte relocation cannot be applied to 4-byte field head.S:147: Error: 8-byte relocation cannot be applied to 4-byte field head.S:155: Error: 8-byte relocation cannot be applied to 4-byte field head.S:163: Error: 8-byte relocation cannot be applied to 4-byte field head.S:171: Error: 8-byte relocation cannot be applied to 4-byte field head.S:179: Error: 8-byte relocation cannot be applied to 4-byte field head.S:187: Error: 8-byte relocation cannot be applied to 4-byte field head.S:195: Error: 8-byte relocation cannot be applied to 4-byte field head.S:203: Error: 8-byte relocation cannot be applied to 4-byte field head.S:211: Error: 8-byte relocation cannot be applied to 4-byte field head.S:219: Error: 8-byte relocation cannot be applied to 4-byte field head.S:227: Error: 8-byte relocation cannot be applied to 4-byte field head.S:235: Error: 8-byte relocation cannot be applied to 4-byte field head.S:243: Error: 8-byte relocation cannot be applied to 4-byte field head.S:251: Error: 8-byte relocation cannot be applied to 4-byte field head.S:259: Error: 8-byte relocation cannot be applied to 4-byte field head.S:268: Error: 8-byte relocation cannot be applied to 4-byte field head.S:269: Error: 8-byte relocation cannot be applied to 4-byte field head.S:270: Error: 8-byte relocation cannot be applied to 4-byte field head.S:274: Error: 8-byte relocation cannot be applied to 4-byte field head.S:446: Error: 8-byte relocation cannot be applied to 4-byte field head.S:692: Error: 8-byte relocation cannot be applied to 4-byte field head.S:697: Error: 8-byte relocation cannot be applied to 4-byte field head.S:700: Error: 8-byte relocation cannot be applied to 4-byte field head.S:701: Error: 8-byte relocation cannot be applied to 4-byte field head.S:716: Error: 8-byte relocation cannot be applied to 4-byte field head.S:717: Error: 8-byte relocation cannot be applied to 4-byte field head.S:718: Error: 8-byte relocation cannot be applied to 4-byte field head.S:719: Error: 8-byte relocation cannot be applied to 4-byte field head.S:720: Error: 8-byte relocation cannot be applied to 4-byte field head.S:721: Error: 8-byte relocation cannot be applied to 4-byte field head.S:722: Error: 8-byte relocation cannot be applied to 4-byte field head.S:723: Error: 8-byte relocation cannot be applied to 4-byte field head.S:726: Error: 8-byte relocation cannot be applied to 4-byte field head.S:727: Error: 8-byte relocation cannot be applied to 4-byte field head.S:729: Error: 8-byte relocation cannot be applied to 4-byte field head.S:742: Error: 8-byte relocation cannot be applied to 4-byte field head.S:744: Error: 8-byte relocation cannot be applied to 4-byte field head.S:945: Error: 8-byte relocation cannot be applied to 4-byte field make: *** [head.o] Error 1 [joe@localhost memtest86-3.4]$ -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

3 7

Newbie questions
by Richard Green 03 Jun '08

03 Jun '08

Hi, I'm looking to build a headless system, mainly for messing around with Linux which I'd like to access remotely and via a serial console without the need for a keyboard and monitor. Unfortunately I don't really have the budget to buy a server motherboard and the kind of processor that goes with it (I already have a core 2 duo, so just plan to get a suitable motherboard for that), and so wont be able to run it headless and get a serial console from boot. I do realise that Linux can provide a serial console from grub, but I'd like to be able to reinstall and do everything without a monitor in the house. My question is; If I got a supported motherboard and installed coreboot upon it, would I be able to configure it so that all output from power-on was redirected to a serial port on the motherboard, and all configuration could be completed using this method so that I could boot and install operating systems from CD, etc using just the serial console? Would it be completely supported by Linux or would there be any noticeable difference to, say using a standard motherboard with a standard BIOS? Thanks for your help, Rich

2 1

patch: clean up cx5536 power handling, get power working on usb port 3 on dbe62
by ron minnich 03 Jun '08

03 Jun '08

attached who knows why I can't get port 4 to go .... mystery so far. ron

3 7

r688 - in coreboot-v3: mainboard/artecgroup/dbe62 southbridge/amd/cs5536
by svn＠coreboot.org 03 Jun '08

03 Jun '08

Author: rminnich Date: 2008-06-03 17:22:16 +0200 (Tue, 03 Jun 2008) New Revision: 688 Modified: coreboot-v3/mainboard/artecgroup/dbe62/dts coreboot-v3/southbridge/amd/cs5536/cs5536.c coreboot-v3/southbridge/amd/cs5536/dts Log: This patch gets usb port 3 on dbe62 working and sets up a dts-based way to map USB EHCI power control registers to power enables pins 1 and 2. Why doesn't port 4 work? Who knows. That's a problem for another day. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: coreboot-v3/mainboard/artecgroup/dbe62/dts =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe62/dts 2008-05-28 01:00:36 UTC (rev 687) +++ coreboot-v3/mainboard/artecgroup/dbe62/dts 2008-06-03 15:22:16 UTC (rev 688) @@ -52,6 +52,8 @@ com2_address = "0x3f8"; /* Set com2 IRQ to be what is usually COM1 */ com2_irq = "4"; + /* USB Port Power Handling setting. */ + pph = "0xf5"; }; pci@15,2 { /config/("southbridge/amd/cs5536/ide"); Modified: coreboot-v3/southbridge/amd/cs5536/cs5536.c =================================================================== --- coreboot-v3/southbridge/amd/cs5536/cs5536.c 2008-05-28 01:00:36 UTC (rev 687) +++ coreboot-v3/southbridge/amd/cs5536/cs5536.c 2008-06-03 15:22:16 UTC (rev 688) @@ -454,8 +454,16 @@ *(bar + UOCMUX) |= PMUX_HOST; /* Overcurrent configuration */ + printk(BIOS_DEBUG, "UOCCAP is %x\n", *(bar + UOCCAP)); if (sb->enable_USBP4_overcurrent) *(bar + UOCCAP) |= sb->enable_USBP4_overcurrent; + /* power control. see comment in the dts for these bits */ + if (sb->pph) { + *(bar + UOCCAP) &= ~0xff; + *(bar + UOCCAP) |= sb->pph; + } + printk(BIOS_DEBUG, "UOCCAP is %x\n", *(bar + UOCCAP)); + } /* PBz#6466: If the UOC(OTG) device, port 4, is configured as a @@ -481,7 +489,17 @@ } } - /* Disable virtual PCI UDC and OTG headers. */ + /* Disable virtual PCI UDC and OTG headers. The kernel never + * sees a header for this device. It used to provide an OS + * visible device, but that was defeatured. There are still + * some registers in the block that are useful for the firmware + * to setup, but nothing that a kernel level driver would need + * to consume. + * + * As you can see above, VSA does provide the header under + * device ID PCI_DEVICE_ID_AMD_CS5536_OTG, but it is hidden + * when 0xDEADBEEF is written to config space register 0x7C. + */ dev = dev_find_pci_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_UDC, 0); if (dev) Modified: coreboot-v3/southbridge/amd/cs5536/dts =================================================================== --- coreboot-v3/southbridge/amd/cs5536/dts 2008-05-28 01:00:36 UTC (rev 687) +++ coreboot-v3/southbridge/amd/cs5536/dts 2008-06-03 15:22:16 UTC (rev 688) @@ -36,9 +36,34 @@ /* 0:IDE 1:FLASH, if you are using NAND flash instead of IDE drive. */ enable_ide_nand_flash = "0"; - /* Enable USB Port 4 (0:host 1:device). */ + /* Enable USB Port 4 (0:host 1:device). + * This means that the board or whatever would be a "gadget", i.e. + * you connect it to a computer and it looks like a storage or camera + * or printer. + */ enable_USBP4_device = "0"; + /* This is a tad confusing, but it's hard to make it easy. + * These are the PPH bits (port power handling) in the + * USB Option Capability register. They are 4 2-bit fields + * that correspond to the four ports. This chip has two PWR ENABLE + * pins, and what you can do is, for each of the four fields, + * map which port controls which pin. It is common to map + * ports 1&2 to PWR_EN_1, and ports 3&4 to PWR_EN_2. + * The two bit fields are as follows: + * 00 -- no power ever + * 01 -- power control in EHCI will turn on both. + * 10 -- power control will turn on EN1 + * 11 -- power control will turn on EN2 + * This is all very wiring dependent, + * and there is a default hardware value (0xea), + * meaning port 4 is EN2 and the rest are EN1. + * So we let this default to 0, which to the driver means "do nothing", + * but if the mainboard sets it, then it will be set into the UOCCAP. + * for reference, DBE62 seems to want xx111010 -- xx because we + * can get port 3 to work, but not port 4. + */ + pph = "0"; /* 0:off, xxxx:overcurrent setting, e.g. 0x3FEA. * See CS5536 - Data Book (pages 380-381). */

1 0

[PATCH][v3] add consoles to v3 lbtable
by Patrick Georgi 03 Jun '08

03 Jun '08

Hi, when doing the patch for cbv2 to add console information, I promised to provide a compatible facility for v3, too. Sorry it took so long, but here it is. It currently uses the pci rom init config variable to decide if to add a vgatext console, because that's the best we have in v3. Better ideas are welcome. Regards, Patrick Georgi Signed-Off-By: Patrick Georgi <patrick(a)georgi-clan.de> Index: include/tables.h =================================================================== --- include/tables.h (revision 687) +++ include/tables.h (working copy) @@ -175,6 +175,27 @@ u32 dev_root_ptr; /* Pointer to the root device */ }; +#define LB_TAG_SERIAL 0x000f +struct lb_serial { + u32 tag; + u32 size; + u16 ioport; +}; + +#define LB_TAG_CONSOLE 0x0010 +struct lb_console { + u32 tag; + u32 size; + u16 type; +}; + +#define LB_TAG_CONSOLE_SERIAL8250 0 +#define LB_TAG_CONSOLE_VGA 1 +#define LB_TAG_CONSOLE_BTEXT 2 +#define LB_TAG_CONSOLE_LOGBUF 3 +#define LB_TAG_CONSOLE_SROM 4 +#define LB_TAG_CONSOLE_EHCI 5 + /* The following structures are for the cmos definitions table */ #define LB_TAG_CMOS_OPTION_TABLE 200 /* cmos header record */ Index: arch/x86/coreboot_table.c =================================================================== --- arch/x86/coreboot_table.c (revision 687) +++ arch/x86/coreboot_table.c (working copy) @@ -25,6 +25,7 @@ #include <device/device.h> #include <tables.h> #include <mc146818rtc.h> +#include <uart8250.h> #include <lib.h> //#include <cpu/cpu.h> //#include <pirq_routing.h> @@ -98,6 +99,44 @@ return mem; } +struct lb_serial *lb_serial(struct lb_header *header) +{ +#if defined(TTYSx_BASE) + struct lb_record *rec; + struct lb_serial *serial; + rec = lb_new_record(header); + serial = (struct lb_serial *)rec; + serial->tag = LB_TAG_SERIAL; + serial->size = sizeof(*serial); + serial->ioport = TTYSx_BASE; + return serial; +#else + return header; +#endif +} + +void add_console(struct lb_header *header, u16 consoletype) +{ + struct lb_record *rec; + struct lb_console *console; + rec = lb_new_record(header); + console = (struct lb_console *)lb_new_record(header); + console->tag = LB_TAG_CONSOLE; + console->size = sizeof(*console); + console->type = consoletype; +} + +void lb_console(struct lb_header *header) +{ +#ifdef CONFIG_CONSOLE_SERIAL + add_console(header, LB_TAG_CONSOLE_SERIAL8250); +#endif +/* FIXME when we have a proper vga console ourself */ +#ifdef CONFIG_PCI_OPTION_ROM_RUN + add_console(header, LB_TAG_CONSOLE_VGA); +#endif +} + struct lb_mainboard *lb_mainboard(struct lb_header *header) { struct lb_record *rec; @@ -454,6 +493,12 @@ /* Record our motherboard */ lb_mainboard(head); + /* Record the serial port, if present */ + lb_serial(head); + + /* Record our console setup */ + lb_console(head); + /* Record our various random string information */ lb_strings(head);

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coreboot June 2008