coreboot June 2008

coreboot@coreboot.org

75 participants
230 discussions

Re: [coreboot] flashrom and list of computers
by Carl-Daniel Hailfinger 10 Jun '08

10 Jun '08

Hi, does anybody have an idea what to do if ICH6 BIOS Lock is enabled and BIOS Write is disabled? Removing the lock bit seems to fail according to flashrom. On 06.06.2008 16:55, walter harms wrote: > Carl-Daniel Hailfinger wrote: > >> On 06.06.2008 09:10, walter harms wrote: >> >>> my idea was to use dmidecode that i can get informations like that: >>> >>> Handle 0x0100 >>> DMI type 1, 25 bytes. >>> System Information >>> Manufacturer: Dell Inc. >>> Product Name: OptiPlex GX280 >>> Version: Not Specified >>> >>> >>> >> Sometimes dmidecode also has information on BIOS size. Having that info >> as well would be nice. >> > > Handle 0x0000 > DMI type 0, 20 bytes. > BIOS Information > Vendor: Dell Inc. > ROM Size: 512 kB > > >> If there are machines where flashrom does not find a flash chip, please >> run flashrom -V. >> >> > attached > Thanks. Found chipset "Intel ICH6/ICH6R", enabling flash write... BIOS Lock Enable: enabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x2 tried to set 0xdc to 0x3 on Intel ICH6/ICH6R failed (WARNING ONLY) FAILED! Dell has locked the BIOS against writing. We try to unlock it, but we fail. Does the BIOS have any settings like "BIOS/Flash write protection" or something similar? > note: please understand that i have no intention to run ./flashrom -w before i am totaly > sure that i can revert that. > OK. Good decision. Regards, Carl-Daniel

3 4

V2 Orders of Initialization of Devices
by bari 10 Jun '08

10 Jun '08

Does the order of the devices in /src/maniboard/../../Config.lb actually effect the order in which the devices are initialized in coreboot? If not, what is the preferred method if one device or register needs to be set before others? -Bari

5 17

memory init on ASUS M2V-MX SE
by Rudolf Marek 10 Jun '08

10 Jun '08

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello all, I'm trying to get the Asus M2V-MX SE working (K8T890/VT8237S) it has AM2 socket. CPU is semperon model 127 fam f Currently there is some problem with memory, I have attached the log. I have no clue what might be wrong. The module is 512MB 533MHz single DDR2 with CAS4. The FIDVID changing and fidvid setup is disabled, reset of HT is disabled. It seems to fall down the drain on very same place. Any clue? Maybe I have some options wrong? What should I check please? I checked I2C reading and they are correct (I verified with EEPROM dump) I dont understand why: ... Setting variable MTRR 02, base: 0000MB, range: 0200MB, type WB ... The range is only to 200MB ??? export MEM_TRAIN_SEQ:=0 I have no other DDR2 module to check. Thanks, Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.6 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iD8DBQFITYmF3J9wPJqZRNURAj/iAJ9wmNn9okVbF9Wn+xHNlTpfSBPrIQCfXqxG e8VpRhnd12QDnPFxg4jRSWk= =Sioj -----END PGP SIGNATURE----- coreboot-2.0.0.0Fallback Po èen 9 21:25:28 CEST 2008 starting... now booting... fallback coreboot-2.0.0.0Normal Po èen 9 21:25:06 CEST 2008 starting... now booting... real_main Enabling routing table for node 00 done. Enabling UP settings Disabling read/write/fill probes for UP... done. coherent_ht_finalize done core0 started: now booting... Core0 started started ap apicid: SBLink=00 NC node|link=00 0001K8T890 found at LDT 00 Agreed on width: 01 CPU programmed to HT freq: 05 VIA HT caps: 0075 HT between CPU and NB OK, not requesting reset 0101ht reset - NO reset after smbus after memreset Ram1.00 setting up CPU00 northbridge registers done. Ram2.00 Device error Device error Device error Unbuffered 1 min_cycle_time:00000250 i:00000000 latencies:00000038 index:00000000 latency:00000003 value1:00000050 value2:00000500 new_cycle_time:00000500 new_latency:00000003 index:00000001 latency:00000004 value1:0000003d value2:00000375 new_cycle_time:00000375 new_latency:00000004 index:00000002 latency:00000005 value1:0000003d value2:00000375 new_cycle_time:00000375 new_latency:00000004 2 min_cycle_time:00000375 2 min_latency:00000004 3 min_cycle_time:00000375 3 min_latency:00000004 4 min_cycle_time:00000375 266Mhz 266Mhz dimm socket: 00000000 trc trcd trrd tras update_dimm_Tras: 0 value=0000002d update_dimm_Tras: 1 value=00000708 update_dimm_Tras: divisor=000000c8 update_dimm_Tras: clocks=00000009 trp trtp twr tref twtr trfc XRAM: 0x00080000 KB Ram3 dimm_mask = 00000001 x4_mask = 00000000 x16_mask = 00000000 single_rank_mask = 00000001 ODC = 00111222 Addr Timing= 002f2f00 Initializing memory: done sysinfo tom_k 00080000Setting variable MTRR 02, base: 0000MB, range: 0200MB, type WB DQS Training:RcvrEn:Pass1: 00 train_DqsRcvrEn: begin ctrl 00000000 TrainRcvEn: 0 ctrl00000000 TrainRcvEn51: channel 00000000 TrainRcvEn52: index 00000010 TrainRcvEn53: TestAddr0B 00005000 TrainRcvEn541: RcvrEnDly 00000000 QW0.lo : test_buf= fffb0bfc value = aaaaaaaa QW0.lo : addr_lo = 00100000 value = aaaaaaaa QW0.hi : test_buf= fffb0c00 value = aaaaaaaa QW0.hi : addr_lo = 00100004 value = aa8aaaaa TrainRcvEn542: Test0 00000001 TrainRcvEn55: RcvrEnDly 00000000 TrainRcvEn56: RcvrEnDly 00000000 TrainRcvEn541: RcvrEnDly 00000001 QW0.lo : test_buf= fffb0bbc value = 55555555 QW0.lo : addr_lo = 00500000 value = 55555555 QW0.hi : test_buf= fffb0bc0 value = 55555555 QW0.hi : addr_lo = 00500004 value = 55855555 TrainRcvEn542: Test0 00000001 TrainRcvEn55: RcvrEnDly 00000001 TrainRcvEn56: RcvrEnDly 00000001 TrainRcvEn541: RcvrEnDly 00000002 QW0.lo : test_buf= fffb0bfc value = aaaaaaaa QW0.lo : addr_lo = 00100000 value = aaaaaaaa QW0.hi : test_buf= fffb0c00 value = aaaaaaaa QW0.hi : addr_lo = 00100004 value = a58aaaaa TrainRcvEn542: Test0 00000001 TrainRcvEn55: RcvrEnDly 00000002 TrainRcvEn56: RcvrEnDly 00000002 TrainRcvEn541: RcvrEnDly 00000003 QW0.lo : test_buf= fffb0bbc value = 55555555 QW0.lo : addr_lo = 00500000 value = 55555555 QW0.hi : test_buf= fffb0bc0 value = 55555555 QW0.hi : addr_lo = 00500004 value = 55555555 TrainRcvEn542: Test0 00000000 QW0.lo : test_buf= fffb0bfc value = aaaaaaaa QW0.lo : addr_lo = 00100000 value = aaaaaaaa QW0.hi : test_buf= fffb0c00 value = aaaaaaaa QW0.hi : addr_lo = 00100004 value = aaaaaaaa TrainRcvEn543: Test1 00000000 TrainRcvEn55: RcvrEnDly 00000003 TrainRcvEn61: RcvrEnDly 00000003 TrainRcvEn63: RcvrEnDly 00000003 TrainRcvEn64: CTLRMaxDelay 00000003 TrainRcvEn52: index 00000013 TrainRcvEn52: index 00000016 TrainRcvEn52: index 00000019 TrainRcvEn51: channel 00000001 TrainRcvEn52: index 00000010 TrainRcvEn52: index 00000013 TrainRcvEn52: index 00000016 TrainRcvEn52: index 00000019 TrainRcvEn65: CTLRMaxDelay 00000003 CTLRMaxDelay=03 train_DqsRcvrEn: end ctrl 00000000 done DQS Training:DQSPos: 00 train_DqsPos: begin ctrl 00000000 TrainDQSRdWrPos: 0 ctrl 00000000 TrainDQSRdWrPos: 1 channel 00000000 TrainDQSRdWrPos: 21 DQSWrDelay 00000000 TrainReadPos00000000 TrainDQSPos begin 00000000 TrainDQSPos: 11 ChipSel 00000000 TrainDQSPos: 12 TestAddr 00001000 TrainDQSPos: 13 for read so write at first00000000 TrainDQSPos: 141 DQSDelay 00000000 TrainDQSPos: 142 MutualCSPassW 000000ff TrainDQSPos: 144 Pattern 00000000 TrainDQSPos: 145 MutualCSPassW 000000ff test_buf= 000cea20 value = 00000000 taddr_lo = 00100000 value = ffffefff bitmap = 000000f0 test_buf= 000cea24 value = 00000000 taddr_lo = 00100004 value = dfffdfff bitmap = 00000000 test_buf= 000cea28 value = ffffffff taddr_lo = 00100008 value = ffffefff bitmap = 00000000 test_buf= 000cea2c value = ffffffff taddr_lo = 0010000c value = dfffdfff bitmap = 00000000 test_buf= 000cea30 value = 00000000 taddr_lo = 00100010 value = ffffffff bitmap = 00000000 test_buf= 000cea34 value = 00000000 taddr_lo = 00100014 value = ffffffff bitmap = 00000000 test_buf= 000cea38 value = 00000000 taddr_lo = 00100018 value = 00000000 bitmap = 00000000 test_buf= 000cea3c value = 00000000 taddr_lo = 0010001c value = 00000000 bitmap = 00000000 test_buf= 000cea40 value = 00000000 taddr_lo = 00100020 value = 00000000 bitmap = 00000000 test_buf= 000cea44 value = 00000000 taddr_lo = 00100024 value = 00000000 bitmap = 00000000 test_buf= 000cea48 value = ffffffff taddr_lo = 00100028 value = ffffefff bitmap = 00000000 test_buf= 000cea4c value = ffffffff taddr_lo = 0010002c value = dfffdfdf bitmap = 00000000 test_buf= 000cea50 value = 00000000 taddr_lo = 00100030 value = ffffffff bitmap = 00000000 test_buf= 000cea54 value = 00000000 taddr_lo = 00100034 value = ffffffff bitmap = 00000000 test_buf= 000cea58 value = 00000000 coreboot-2.0.0.0Fallback Po èen 9 21:25:28 CEST 2008 starting... now booting... fallback coreboot-2.0.0.0Normal Po èen 9 21:25:06 CEST 2008 starting... now booting... real_main Enabling routing table for node 00 done. Enabling UP settings Disabling read/write/fill probes for UP... done. coherent_ht_finalize done core0 started: now booting... Core0 started started ap apicid: SBLink=00 NC node|link=00 0001K8T890 found at LDT 00 Agreed on width: 01 CPU programmed to HT freq: 05 VIA HT caps: 0075 HT between CPU and NB OK, not requesting reset 0101ht reset - NO reset after smbus after memreset Ram1.00 setting up CPU00 northbridge registers done. Ram2.00 Device error Device error Device error Unbuffered 1 min_cycle_time:00000250 i:00000000 latencies:00000038 index:00000000 latency:00000003 value1:00000050 value2:00000500 new_cycle_time:00000500 new_latency:00000003 index:00000001 latency:00000004 value1:0000003d value2:00000375 new_cycle_time:00000375 new_latency:00000004 index:00000002 latency:00000005 value1:0000003d value2:00000375 new_cycle_time:00000375 new_latency:00000004 2 min_cycle_time:00000375 2 min_latency:00000004 3 min_cycle_time:00000375 3 min_latency:00000004 4 min_cycle_time:00000375 266Mhz 266Mhz dimm socket: 00000000 trc trcd trrd tras update_dimm_Tras: 0 value=0000002d update_dimm_Tras: 1 value=00000708 update_dimm_Tras: divisor=000000c8 update_dimm_Tras: clocks=00000009 trp trtp twr tref twtr trfc XRAM: 0x00080000 KB Ram3 dimm_mask = 00000001 x4_mask = 00000000 x16_mask = 00000000 single_rank_mask = 00000001 ODC = 00111222 Addr Timing= 002f2f00 Initializing memory: done sysinfo tom_k 00080000Setting variable MTRR 02, base: 0000MB, range: 0200MB, type WB DQS Training:RcvrEn:Pass1: 00 train_DqsRcvrEn: begin ctrl 00000000 TrainRcvEn: 0 ctrl00000000 TrainRcvEn51: channel 00000000 TrainRcvEn52: index 00000010 TrainRcvEn53: TestAddr0B 00005000 TrainRcvEn541: RcvrEnDly 00000000 QW0.lo : test_buf= fffb0bfc value = aaaaaaaa QW0.lo : addr_lo = 00100000 value = aaaaaaaa QW0.hi : test_buf= fffb0c00 value = aaaaaaaa QW0.hi : addr_lo = 00100004 value = aa8aaaaa TrainRcvEn542: Test0 00000001 TrainRcvEn55: RcvrEnDly 00000000 TrainRcvEn56: RcvrEnDly 00000000 TrainRcvEn541: RcvrEnDly 00000001 QW0.lo : test_buf= fffb0bbc value = 55555555 QW0.lo : addr_lo = 00500000 value = 55555555 QW0.hi : test_buf= fffb0bc0 value = 55555555 QW0.hi : addr_lo = 00500004 value = 55855555 TrainRcvEn542: Test0 00000001 TrainRcvEn55: RcvrEnDly 00000001 TrainRcvEn56: RcvrEnDly 00000001 TrainRcvEn541: RcvrEnDly 00000002 QW0.lo : test_buf= fffb0bfc value = aaaaaaaa QW0.lo : addr_lo = 00100000 value = aaaaaaaa QW0.hi : test_buf= fffb0c00 value = aaaaaaaa QW0.hi : addr_lo = 00100004 value = aa8aaaaa TrainRcvEn542: Test0 00000001 TrainRcvEn55: RcvrEnDly 00000002 TrainRcvEn56: RcvrEnDly 00000002 TrainRcvEn541: RcvrEnDly 00000003 QW0.lo : test_buf= fffb0bbc value = 55555555 QW0.lo : addr_lo = 00500000 value = 55555555 QW0.hi : test_buf= fffb0bc0 value = 55555555 QW0.hi : addr_lo = 00500004 value = 55555555 TrainRcvEn542: Test0 00000000 QW0.lo : test_buf= fffb0bfc value = aaaaaaaa QW0.lo : addr_lo = 00100000 value = aaaaaaaa QW0.hi : test_buf= fffb0c00 value = aaaaaaaa QW0.hi : addr_lo = 00100004 value = aaaaaaaa TrainRcvEn543: Test1 00000000 TrainRcvEn55: RcvrEnDly 00000003 TrainRcvEn61: RcvrEnDly 00000003 TrainRcvEn63: RcvrEnDly 00000003 TrainRcvEn64: CTLRMaxDelay 00000003 TrainRcvEn52: index 00000013 TrainRcvEn52: index 00000016 TrainRcvEn52: index 00000019 TrainRcvEn51: channel 00000001 TrainRcvEn52: index 00000010 TrainRcvEn52: index 00000013 TrainRcvEn52: index 00000016 TrainRcvEn52: index 00000019 TrainRcvEn65: CTLRMaxDelay 00000003 CTLRMaxDelay=03 train_DqsRcvrEn: end ctrl 00000000 done DQS Training:DQSPos: 00 train_DqsPos: begin ctrl 00000000 TrainDQSRdWrPos: 0 ctrl 00000000 TrainDQSRdWrPos: 1 channel 00000000 TrainDQSRdWrPos: 21 DQSWrDelay 00000000 TrainReadPos00000000 TrainDQSPos begin 00000000 TrainDQSPos: 11 ChipSel 00000000 TrainDQSPos: 12 TestAddr 00001000 TrainDQSPos: 13 for read so write at first00000000 TrainDQSPos: 141 DQSDelay 00000000 TrainDQSPos: 142 MutualCSPassW 000000ff TrainDQSPos: 144 Pattern 00000000 TrainDQSPos: 145 MutualCSPassW 000000ff test_buf= 000cea20 value = 00000000 taddr_lo = 00100000 value = ffffefff bitmap = 000000f0 test_buf= 000cea24 value = 00000000 taddr_lo = 00100004 value = dfffdfff bitmap = 00000000 test_buf= 000cea28 value = ffffffff taddr_lo = 00100008 value = ffffefff bitmap = 00000000 test_buf= 000cea2c value = ffffffff taddr_lo = 0010000c value = dfffdfff bitmap = 00000000 test_buf= 000cea30 value = 00000000 taddr_lo = 00100010 value = ffffffff bitmap = 00000000 test_buf= 000cea34 value = 00000000 taddr_lo = 00100014 value = ffffffff bitmap = 00000000 test_buf= 000cea38 value = 00000000 taddr_lo = 00100018 value = 00000000 bitmap = 00000000 test_buf= 000cea3c value = 00000000 taddr_lo = 0010001c value = 00000000 bitmap = 00000000 test_buf= 000cea40 value = 00000000 taddr_lo = 00100020 value = 00000000 bitmap = 00000000 test_buf= 000cea44 value = 00000000 taddr_lo = 00100024 value = 00000000 bitmap = 00000000 test_buf= 000cea48 value = ffffffff taddr_lo = 00100028 value = ffffefff bitmap = 00000000 test_buf= 000cea4c value = ffffffff taddr_lo = 0010002c value = dfffdfdf bitmap = 00000000 test_buf= 000cea50 value = 00000000 taddr_lo = 00100030 value = ffffffff bitmap = 00000000 test_buf= 000cea54 value = 00000000 taddr_lo = 00100034 value = ffffffff bitmap = 00000000 test_buf= 000cea58 value = 00000000 coreboot-2.0.0.0Fallback Po èen 9 21:25:28 CEST 2008 starting... now booting... fallback coreboot-2.0.0.0Normal Po èen 9 21:25:06 CEST 2008 starting... now booting... real_main Enabling routing table for node 00 done. Enabling UP settings Disabling read/write/fill probes for UP... done. coherent_ht_finalize done core0 started: now booting... Core0 started started ap apicid: SBLink=00 NC node|link=00 0001K8T890 found at LDT 00 Agreed on width: 01 CPU programmed to HT freq: 05 VIA HT caps: 0075 HT between CPU and NB OK, not requesting reset 0101ht reset - NO reset after smbus after memreset Ram1.00 setting up CPU00 northbridge registers done. Ram2.00 Device error Device error Device error Unbuffered 1 min_cycle_time:00000250 i:00000000 latencies:00000038 index:00000000 latency:00000003 value1:00000050 value2:00000500 new_cycle_time:00000500 new_latency:00000003 index:00000001 latency:00000004 value1:0000003d value2:00000375 new_cycle_time:00000375 new_latency:00000004 index:00000002 latency:00000005 value1:0000003d value2:00000375 new_cycle_time:00000375 new_latency:00000004 2 min_cycle_time:00000375 2 min_latency:00000004 3 min_cycle_time:00000375 3 min_latency:00000004 4 min_cycle_time:00000375 266Mhz 266Mhz dimm socket: 00000000 trc trcd trrd tras update_dimm_Tras: 0 value=0000002d update_dimm_Tras: 1 value=00000708 update_dimm_Tras: divisor=000000c8 update_dimm_Tras: clocks=00000009 trp trtp twr tref twtr trfc XRAM: 0x00080000 KB Ram3 dimm_mask = 00000001 x4_mask = 00000000 x16_mask = 00000000 single_rank_mask = 00000001 ODC = 00111222 Addr Timing= 002f2f00 Initializing memory: done sysinfo tom_k 00080000Setting variable MTRR 02, base: 0000MB, range: 0200MB, type WB DQS Training:RcvrEn:Pass1: 00 train_DqsRcvrEn: begin ctrl 00000000 TrainRcvEn: 0 ctrl00000000 TrainRcvEn51: channel 00000000 TrainRcvEn52: index 00000010 TrainRcvEn53: TestAddr0B 00005000 TrainRcvEn541: RcvrEnDly 00000000 QW0.lo : test_buf= fffb0bfc value = aaaaaaaa QW0.lo : addr_lo = 00100000 value = aaaaaac1 TrainRcvEn542: Test0 00000001 TrainRcvEn55: RcvrEnDly 00000000 TrainRcvEn56: RcvrEnDly 00000000 TrainRcvEn541: RcvrEnDly 00000001 QW0.lo : test_buf= fffb0bbc value = 55555555 QW0.lo : addr_lo = 00500000 value = 55555551 TrainRcvEn542: Test0 00000001 TrainRcvEn55: RcvrEnDly 00000001 TrainRcvEn56: RcvrEnDly 00000001 TrainRcvEn541: RcvrEnDly 00000002 QW0.lo : test_buf= fffb0bfc value = aaaaaaaa QW0.lo : addr_lo = 00100000 value = aaaaaa51 TrainRcvEn542: Test0 00000001 TrainRcvEn55: RcvrEnDly 00000002 TrainRcvEn56: RcvrEnDly 00000002 TrainRcvEn541: RcvrEnDly 00000003 QW0.lo : test_buf= fffb0bbc value = 55555555 QW0.lo : addr_lo = 00500000 value = 55555555 QW0.hi : test_buf= fffb0bc0 value = 55555555 QW0.hi : addr_lo = 00500004 value = 55555555 TrainRcvEn542: Test0 00000000 QW0.lo : test_buf= fffb0bfc value = aaaaaaaa QW0.lo : addr_lo = 00100000 value = aaaaaaaa QW0.hi : test_buf= fffb0c00 value = aaaaaaaa QW0.hi : addr_lo = 00100004 value = aaaaaaaa TrainRcvEn543: Test1 00000000 TrainRcvEn55: RcvrEnDly 00000003 TrainRcvEn61: RcvrEnDly 00000003 TrainRcvEn63: RcvrEnDly 00000003 TrainRcvEn64: CTLRMaxDelay 00000003 TrainRcvEn52: index 00000013 TrainRcvEn52: index 00000016 TrainRcvEn52: index 00000019 TrainRcvEn51: channel 00000001 TrainRcvEn52: index 00000010 TrainRcvEn52: index 00000013 TrainRcvEn52: index 00000016 TrainRcvEn52: index 00000019 TrainRcvEn65: CTLRMaxDelay 00000003 CTLRMaxDelay=03 train_DqsRcvrEn: end ctrl 00000000 done DQS Training:DQSPos: 00 train_DqsPos: begin ctrl 00000000 TrainDQSRdWrPos: 0 ctrl 00000000 TrainDQSRdWrPos: 1 channel 00000000 TrainDQSRdWrPos: 21 DQSWrDelay 00000000 TrainReadPos00000000 TrainDQSPos begin 00000000 TrainDQSPos: 11 ChipSel 00000000 Tra

3 6

Some Notes On Building gPXE for Coreboot
by Chris Kilgour 09 Jun '08

09 Jun '08

http://www.whiterocker.com/gpxe/ FYI - At this point I don't plan to submit any patches to gPXE as my approach is rather hackish and still experimental. Any comments/suggestions welcome. Chris.

4 5

Makefile generation patch for non-native GNU make
by Pierre Pronchery 09 Jun '08

09 Jun '08

Changes Makefile generation so that recursive "make" calls read "$(MAKE)" instead, as GNU make (or "gmake") is currently necessary to build. Signed-off-by: Pierre Pronchery <khorben(a)defora.org> --- HTH, -- khorben Index: util/ADLO/Makefile =================================================================== --- util/ADLO/Makefile (revision 3362) +++ util/ADLO/Makefile (working copy) @@ -40,7 +40,7 @@ #------------------------------------------------- bios: - ( cd ${BOCHS_B} ; make ) + ( cd ${BOCHS_B} ; $(MAKE) ) sync #------------------------------------------------- @@ -101,7 +101,7 @@ clean: rm -rf *.o ${PAYLOAD} - (cd ${BOCHS_B} ; make clean ) + (cd ${BOCHS_B} ; $(MAKE) clean ) distclean: clean rm -rf ${BOCHS_C} Index: util/newconfig/config.g =================================================================== --- util/newconfig/config.g (revision 3362) +++ util/newconfig/config.g (working copy) @@ -2158,7 +2158,7 @@ for i, o in romimages.items(): file.write("%s/coreboot.rom:\n" % o.getname()) file.write("\tif (cd %s; \\\n" % o.getname()) - file.write("\t\tmake coreboot.rom)\\\n") + file.write("\t\t$(MAKE) coreboot.rom)\\\n") file.write("\tthen true; else exit 1; fi;\n\n") file.write("clean: ") for i in romimages.keys(): @@ -2166,7 +2166,7 @@ file.write("\n\n") for i, o in romimages.items(): file.write("%s-clean:\n" % o.getname()) - file.write("\t(cd %s; make clean)\n\n" % o.getname()) + file.write("\t(cd %s; $(MAKE) clean)\n\n" % o.getname()) for i in buildroms: file.write("%s:" % i.name)

2 1

r3363 - in trunk/coreboot-v2/util: ADLO newconfig
by svn＠coreboot.org 09 Jun '08

09 Jun '08

Author: stepan Date: 2008-06-09 01:05:24 +0200 (Mon, 09 Jun 2008) New Revision: 3363 Modified: trunk/coreboot-v2/util/ADLO/Makefile trunk/coreboot-v2/util/newconfig/config.g Log: Changes Makefile generation so that recursive "make" calls read "$(MAKE)" instead, as GNU make (or "gmake") is currently necessary to build. Signed-off-by: Pierre Pronchery <khorben(a)defora.org> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/coreboot-v2/util/ADLO/Makefile =================================================================== --- trunk/coreboot-v2/util/ADLO/Makefile 2008-06-07 12:35:11 UTC (rev 3362) +++ trunk/coreboot-v2/util/ADLO/Makefile 2008-06-08 23:05:24 UTC (rev 3363) @@ -40,7 +40,7 @@ #------------------------------------------------- bios: - ( cd ${BOCHS_B} ; make ) + ( cd ${BOCHS_B} ; $(MAKE) ) sync #------------------------------------------------- @@ -101,7 +101,7 @@ clean: rm -rf *.o ${PAYLOAD} - (cd ${BOCHS_B} ; make clean ) + (cd ${BOCHS_B} ; $(MAKE) clean ) distclean: clean rm -rf ${BOCHS_C} Modified: trunk/coreboot-v2/util/newconfig/config.g =================================================================== --- trunk/coreboot-v2/util/newconfig/config.g 2008-06-07 12:35:11 UTC (rev 3362) +++ trunk/coreboot-v2/util/newconfig/config.g 2008-06-08 23:05:24 UTC (rev 3363) @@ -2158,7 +2158,7 @@ for i, o in romimages.items(): file.write("%s/coreboot.rom:\n" % o.getname()) file.write("\tif (cd %s; \\\n" % o.getname()) - file.write("\t\tmake coreboot.rom)\\\n") + file.write("\t\t$(MAKE) coreboot.rom)\\\n") file.write("\tthen true; else exit 1; fi;\n\n") file.write("clean: ") for i in romimages.keys(): @@ -2166,7 +2166,7 @@ file.write("\n\n") for i, o in romimages.items(): file.write("%s-clean:\n" % o.getname()) - file.write("\t(cd %s; make clean)\n\n" % o.getname()) + file.write("\t(cd %s; $(MAKE) clean)\n\n" % o.getname()) for i in buildroms: file.write("%s:" % i.name)

1 0

Offline notice
by Carl-Daniel Hailfinger 08 Jun '08

08 Jun '08

Hi all, I regret to tell you that I'll probably be offline (and very slow to respond to mail) until June 30th due to university sucking up every hour of my days and nights. If you all continue working on coreboot like you did before (I don't doubt that), I'll come back and will be surprised by lots of great news. :-) Have fun and good luck! Regards, Carl-Daniel

1 0

r3362 build service
by coreboot information 07 Jun '08

07 Jun '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "stepan" checked in revision 3362 to the coreboot source repository and caused the following changes: Change Log: fix via epia cn abuild. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of via:epia-cn has been fixed If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

r3362 - trunk/coreboot-v2/targets/via/epia-cn
by svn＠coreboot.org 07 Jun '08

07 Jun '08

Author: stepan Date: 2008-06-07 14:35:11 +0200 (Sat, 07 Jun 2008) New Revision: 3362 Added: trunk/coreboot-v2/targets/via/epia-cn/Config-abuild.lb Log: fix via epia cn abuild. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Added: trunk/coreboot-v2/targets/via/epia-cn/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/via/epia-cn/Config-abuild.lb (rev 0) +++ trunk/coreboot-v2/targets/via/epia-cn/Config-abuild.lb 2008-06-07 12:35:11 UTC (rev 3362) @@ -0,0 +1,20 @@ +# This will make a target directory of ./VENDOR_MAINBOARD + +target VENDOR_MAINBOARD +mainboard VENDOR/MAINBOARD + +option CC="CROSSCC" +option CROSS_COMPILE="CROSS_PREFIX" +option HOSTCC="CROSS_HOSTCC" + +__COMPRESSION__ + +option ROM_SIZE=512*1024 + +romimage "fallback" + option USE_FALLBACK_IMAGE=1 + option ROM_IMAGE_SIZE=0x20000 + option COREBOOT_EXTRA_VERSION=".0-fallback" + payload __PAYLOAD__ +end +buildrom ./coreboot.rom ROM_SIZE "fallback"

1 0

r3361 build service
by coreboot information 07 Jun '08

07 Jun '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "stuge" checked in revision 3361 to the coreboot source repository and caused the following changes: Change Log: Add dump support for Winbond (NSC) PC87427. Dumps available from real hardware. Signed-off-by: Tom Sylla <tsylla(a)gmail.com> Acked-by: Peter Stuge <peter(a)stuge.se> Build Log: Compilation of via:epia-cn is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3361&device=epia-cn&vendor… If something broke during this checkin please be a pain in stuge's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

← Newer
1
...
15
16
17
18
19
20
21
22
23
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot June 2008