coreboot June 2008

coreboot@coreboot.org

75 participants
230 discussions

openbios on tyan s2895
by m-a daneau 06 Jun '08

06 Jun '08

hi, surprisingly, my mother board is fully supported by openbios. i'm now searching a way to install ubuntu and xp on a raid1 with sata. do you think that an openbios could help in some way? thank you m-a _________________________________________________________________

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Coreboot, BSD, Makefiles and trac
by Pierre Pronchery 06 Jun '08

06 Jun '08

Hello, I'm trying to use the ticket system in trac, but keep being rejected as a spammer: "500 Internal Server Error (Submission rejected as potential spam)" Anyway, what I wanted to report is that Coreboot requires changes to compile on BSD (in my case NetBSD). What I wanted to get committed so far is quite trivial actually: recursive "make" calls should be changed to "$(MAKE)", as GNU make (or "gmake") is apparently necessary to build. The attached patch is for ADLO, but the generic build system would need to be fixed as well. HTH, -- khorben Index: util/ADLO/Makefile =================================================================== --- util/ADLO/Makefile (revision 3359) +++ util/ADLO/Makefile (working copy) @@ -40,7 +40,7 @@ #------------------------------------------------- bios: - ( cd ${BOCHS_B} ; make ) + ( cd ${BOCHS_B} ; $(MAKE) ) sync #------------------------------------------------- @@ -101,7 +101,7 @@ clean: rm -rf *.o ${PAYLOAD} - (cd ${BOCHS_B} ; make clean ) + (cd ${BOCHS_B} ; $(MAKE) clean ) distclean: clean rm -rf ${BOCHS_C}

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[RFC] Porting coreboot to Intel Atom (Silverthorne) & SCH US15W (Poulsbo) chipset
by Ken.Fuchs＠bench.com 06 Jun '08

06 Jun '08

Thanks to everyone suggesting AMD processor alternatives (Geode LX) a while back. However, we have decided to stay with Intel Atom (due to its much faster clock speed as well low power requirements). Which version of coreboot (v2 or v3) would be better to port to Intel Atom? We want a fast boot up to both Linux and at least one Microsoft OS (maybe CE). Based on Carl-Daniel Hailfinger's recent post regarding "Open Firmware", v3 would probably be much faster than v2. I helped do an (Opteron) nVidia nForce4 LinuxBIOS port a few years ago, but I don't think it will be much help in porting coreboot to the Intel Atom. Which coreboot chipset might be the best starting point for a port to Intel Atom? Any other opinions about firmware development on the Atom would be welcome ... It seems like an American Arium ECM-XDP3 with SourcePoint would be well worth the price for a large porting effort such as this. (It will provide both assembly and C level JTAG debugging.) Is there a cheaper JTAG debugger that might be viable on Atom/Poulsbo? The firmware will be stored on a SPI NOR flash via LPC and an embedded controller rather than FWH. I have two major concerns about this port: 1) I may not have enough time/resources to complete it. So I may end up optimizing a commercial UEFI solution. 2) I'm not sure I will be able to contribute my source code changes back to the coreboot project due to NDA restrictions/ambiguities. Sincerely, Ken Fuchs

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Acer Opens Up...
by Nathanael D. Noblet 05 Jun '08

05 Jun '08

Just came across this... http://www.itnews.com.au/News/77636,acer-bets-big-on-linux.aspx I'm wondering if they are using or know of coreboot?? Perhaps an opportunity to get in with a vendor, if they haven't already contacted you guys... -- Nathanael d. Noblet Gnat Solutions, Inc T: 403.875.4613

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ram init help on the i82830
by Joseph Smith 05 Jun '08

05 Jun '08

Hello, Now that I got coreboot running on the IP1000, I finally am able to test out the so-dimm socket. I maxed out the slot with a big 512MB so-dimm. I don't think the "for" statement we came up with is working correctly: /* NOTE: Dual-sided ready. */ read32(0 + addr_offset); for (i = 0; i < 4; i++) { reg8 = pci_read_config8(ctrl->d0, DRB + i); if (reg8 != reg8_2) read32(reg8 * 32 * 1024 * 1024); reg8_2 = reg8; } The memory is detecting correctly, but I don't think coreboot can find the end of the side of the so-dimm, thus causing a lockup after Jumping to coreboot. I think I need to setup something more like the E7501 do_ram_command() but I want to keep it simple. Here is the bootlog, Help?? coreboot-2.0.0_IP1000 Tue May 27 21:18:23 EDT 2008 starting... Setting initial registers.... Initial registers have been set. Found DIMM in slot 00 DIMM is 0x0100 on side 1 DIMM is 0x0100 on side 2 DRB 0x60 has been set to 0x08 DRB1 0x61 has been set to 0x10 Found DIMM in slot 01 DIMM is 0x0040 on side 1 DIMM is 0x0000 on side 2 DRB2 0x62 has been set to 0x12 DRB3 0x63 has been set to 0x12 Found DIMM in slot 00, setting DRA... DRA 0x70 has been set to 0x08 Found DIMM in slot 01, setting DRA... DRA 0x71 has been set to 0xf1 RAM Enable 1: Apply NOP Sending RAM command 0x00000010 to 0x00000000 RAM Enable 2: Precharge all Sending RAM command 0x00000020 to 0x00000000 RAM Enable 3: CBR Sending RAM command 0x00000060 to 0x00000000 Sending RAM command 0x00000060 to 0x00000000 Sending RAM command 0x00000060 to 0x00000000 Sending RAM command 0x00000060 to 0x00000000 Sending RAM command 0x00000060 to 0x00000000 Sending RAM command 0x00000060 to 0x00000000 Sending RAM command 0x00000060 to 0x00000000 Sending RAM command 0x00000060 to 0x00000000 RAM Enable 4: Mode register set Sending RAM command 0x00000030 to 0x000001d0 RAM Enable 5: Normal operation Sending RAM command 0x20000270 to 0x00000000 Northbridge following SDRAM init: PCI: 00:00.00 00: 86 80 75 35 06 00 10 20 04 00 00 06 00 00 00 00 10: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00 40: 09 00 05 01 00 00 00 00 00 00 00 00 02 28 00 0e 50: 72 a0 40 00 00 00 00 00 00 30 33 33 33 33 33 33 60: 08 10 12 12 12 12 00 00 00 00 00 00 00 00 00 00 70: 08 f1 ff ff 00 00 00 00 10 00 00 00 70 02 00 20 80: 00 00 00 00 00 00 00 00 80 60 33 09 00 00 00 00 90: 02 38 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 02 00 20 00 17 02 00 1f 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 54 0e 41 a2 99 01 00 c0 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 1b 49 9b fc f0: 11 11 01 00 00 00 0b 05 35 d0 2c cf 22 cd 1d cc Copying coreboot to RAM. Jumping to coreboot. <----LOCKS UP HERE----> -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

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Re: [coreboot] r201 - buildrom-devel/config/payloads
by Myles Watson 05 Jun '08

05 Jun '08

> Author: jcrouse > Date: 2008-06-05 16:54:13 +0200 (Thu, 05 Jun 2008) > New Revision: 201 > > Modified: > buildrom-devel/config/payloads/Config.in > Log: > DIsable LZMA on Geode for coreboot-v2 since we don't have a Config-lab.lb > that is appropriate for Geode platforms. Trivial. Why not add the Config-lab.lb instead? I realize that it maybe should be Config-lzma.lb, but it seems like Geode users might want compression too. Thanks, Myles

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r201 - buildrom-devel/config/payloads
by svn＠coreboot.org 05 Jun '08

05 Jun '08

Author: jcrouse Date: 2008-06-05 16:54:13 +0200 (Thu, 05 Jun 2008) New Revision: 201 Modified: buildrom-devel/config/payloads/Config.in Log: DIsable LZMA on Geode for coreboot-v2 since we don't have a Config-lab.lb that is appropriate for Geode platforms. Trivial. Signed-off-by: Jordan Crouse <jordan.crouse(a)amd.com> Acked-by: Jordan Crouse <jordan.crouse(a)amd.com> Modified: buildrom-devel/config/payloads/Config.in =================================================================== --- buildrom-devel/config/payloads/Config.in 2008-06-02 16:14:55 UTC (rev 200) +++ buildrom-devel/config/payloads/Config.in 2008-06-05 14:54:13 UTC (rev 201) @@ -5,6 +5,7 @@ config USE_LZMA bool "Enable LZMA compression" + depends COREBOOT_V3 || (COREBOOT_V2 && !PLATFORM_GEODE) default y help Precompress the payload with LZMA when using coreboot v2. This changes

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Re: [coreboot] Unprotecting 29F002BT
by Ludwig Jaffe 05 Jun '08

05 Jun '08

a a schrieb: > Ludwig Jaffe wrote: > > Hi > > > > yes, I will check the jumper to unprotect the flash. > > Accourding to an1122 this should be the "temporary unprotect" > > by rising pin1 to 12V=VID. > > The block-unprotect algorithm (protect all blocks, then unprotect all) > > should be added to flashrom aswell so we can permanently unprotect the > > flash. > > jep done that .. but i think you did also ? No, not yet. That is work to do. Soldering-in the jumper is not the big deal btw. > > > > Greetings > > > > LuJa > > > > > > > > a a schrieb: > >> Ludwig Jaffe wrote: > >>> Hi, > >>> > >>> looking for the unprotect-algorithm I found the AN1122 from ST. > >>> The figure 4 shows a way to do this, but, how do we put VID=12V to > >> Pin#1? > >>> Does anybody know how this is done or if we should use the > >>> programmer-mode/way instaed of insystem/mode/way? > >>> > >>> Thanks for your comments. > >>> > >>> Attached the application-note, and the datasheet of st29F002B series. > >>> > >>> > >>> Greetings > >>> > >>> LuJa > >>> > >>> > >> from the other tread i assume you are talking about the > >> compaq deskpro en sff 600n motherboard which has a jumper (P34 but not > >> mounted only pads) to connect pin1 to 12Vdc > >> > >> > >> > ------------------------------------------------------------------------ > >> Express yourself instantly with MSN Messenger! MSN Messenger > >> > > > > > > > > > > ------------------------------------------------------------------------ > Express yourself instantly with MSN Messenger! MSN Messenger > <http://clk.atdmt.com/AVE/go/onm00200471ave/direct/01/>

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Fix M57SLI interrupts, again
by Torsten Duwe 05 Jun '08

05 Jun '08

Please test, especially on v2.x

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patch: fix USB ports on DBE62, and other cs5536-based platforms
by ron minnich 04 Jun '08

04 Jun '08

This change adds some debug prints, and a comment warning to dts on cs5536. Most importantly it fixes a simple programming error which made it so most of the sets on the USB were not doing anything. The bug is also in V2. With this fix, the DBE62 USB ports all work! If someone clones the fix to V2, it will also fix V2. Or, we can just convince you to move forward to V3 :-) Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Also, please note, my remaining issue is to fix X11 on DBE62, then I believe we are done. Has someone tested audio however?

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coreboot June 2008