coreboot June 2008

coreboot@coreboot.org

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230 discussions

r3361 - trunk/util/superiotool
by svn＠coreboot.org 07 Jun '08

07 Jun '08

Author: stuge Date: 2008-06-07 13:36:30 +0200 (Sat, 07 Jun 2008) New Revision: 3361 Modified: trunk/util/superiotool/nsc.c trunk/util/superiotool/superiotool.h Log: Add dump support for Winbond (NSC) PC87427. Dumps available from real hardware. Signed-off-by: Tom Sylla <tsylla(a)gmail.com> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/util/superiotool/nsc.c =================================================================== --- trunk/util/superiotool/nsc.c 2008-06-03 00:22:00 UTC (rev 3360) +++ trunk/util/superiotool/nsc.c 2008-06-07 11:36:30 UTC (rev 3361) @@ -408,6 +408,65 @@ {EOT}}}, {0xf2, "PC87427", { /* SRID[7..5] is marked as "not applicable for the PC87427". */ + {NOLDN, NULL, + {0x10,0x12,0x13,0x1d,0x20,0x21,0x22,0x23,0x24,0x25, + 0x26,0x27,0x28,0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f, + EOT}, + {0x00,0x00,0x00,0x00,0xf2,0x11,0xa0,MISC,MISC,MISC, + 0x02,NANA,0x00,MISC,0x00,0x00,MISC,MISC,RSVD,RSVD, + EOT}}, + {0x0, "Floppy", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,0xf1,EOT}, + {0x00,0x03,0xf2,0x06,0x03,0x02,0x04,0x24,0x00,EOT}}, + {0x2, "COM2", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, + {0x00,0x02,0xf8,0x03,0x03,0x04,0x04,0x02,EOT}}, + {0x3, "COM1", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, + {0x00,0x03,0xf8,0x04,0x03,0x04,0x04,0x02,EOT}}, + {0x4, "System wake-up control (SWC)", + {0x30,0x60,0x61,0x62,0x63,0x64,0x65,0x66,0x67,0x70, + 0x71,0x74,0x75,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x03,0x04,0x04,EOT}}, + {0x5, "Mouse", + {0x30,0x70,0x71,0x74,0x75,EOT}, + {0x00,0x0c,0x02,0x04,0x04,EOT}}, + {0x6, "Keyboard", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0x74,0x75,0xf0, + EOT}, + {0x00,0x00,0x60,0x00,0x64,0x01,0x02,0x04,0x04,0x40, + EOT}}, + {0x7, "GPIO", + {0x30,0x50,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,0xf1, + 0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x03,0x04,0x04,0x00,MISC, + 0x01,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x9, "Fan Monitor and Control (FMC)", + {0x30,0x50,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,0xf1, + EOT}, + {0x00,0x00,0x00,0x00,0x00,0x03,0x04,0x04,0x19,0x06, + EOT}}, + {0xa, "Watchdog timer (WDT)", + {0x30,0x50,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x03,0x04,0x04,0x00,EOT}}, + {0xf, "X-Bus", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,0xf1,0xf2, + 0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xfb,0xfc, + 0xfd,0xfe,0xff,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x04,0x04,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x80,0x10,EOT}}, + {0x10, "Real-time clock (RTC)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0x74,0x75,0xf0, + 0xf1,0xf2,0xf3,0xf6,0xf7,EOT}, + {0x00,0x00,0x70,0x00,0x72,0x08,0x00,0x04,0x04,0x00, + 0x00,0x00,0x00,MISC,0x00,EOT}}, + {0x14, "Health Monitoring and Control (HMC)", + {0x30,0x50,0x60,0x61,0x62,0x63,0x70,0x71,0x74,0x75, + 0xf0,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x04,0x04, + 0x05,EOT}}, {EOT}}}, {0xf3, "PC87373", { {EOT}}}, Modified: trunk/util/superiotool/superiotool.h =================================================================== --- trunk/util/superiotool/superiotool.h 2008-06-03 00:22:00 UTC (rev 3360) +++ trunk/util/superiotool/superiotool.h 2008-06-07 11:36:30 UTC (rev 3361) @@ -51,7 +51,7 @@ #define NANA -3 /* Not Available */ #define RSVD -4 /* Reserved */ #define MISC -5 /* Needs special comment in output */ -#define MAXLDN 0x10 /* Biggest LDN */ +#define MAXLDN 0x14 /* Biggest LDN */ #define LDNSIZE (MAXLDN + 3) /* Biggest LDN + 0 + NOLDN + EOT */ #define MAXNUMIDX 170 /* Maximum number of indexes */ #define IDXSIZE (MAXNUMIDX + 1)

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[flashrom] layout.c: couple of nitpicks
by Andriy Gapon 07 Jun '08

07 Jun '08

It seems that in show_id() type of 'walk' variable should of fixed size (i.e. uint32_t) for x86_64 portability. Also, it looks suspicious that two legacy bios checks (nvidia and general) are exactly the same: if ((*walk) == 0 || ((*walk) & 0x3ff) != 0) { /* We might have an Nvidia chipset bios ... } if ((*walk) == 0 || ((*walk) & 0x3ff) != 0) { printf("Flash image seems to be a legacy BIOS. Disabling checks.\n"); ... -- Andriy Gapon

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[patch][v2] cs5536 usb port4 configuration
by Marc Jones 07 Jun '08

07 Jun '08

This patch uses byte pointer and the MMIO read and write functions. Marc -- Marc Jones Senior Firmware Engineer (970) 226-9684 Office mailto:Marc.Jones@amd.com http://www.amd.com/embeddedprocessors Correctly access MMIO for cs5536 USB port4 configuration. Signed-off-by: Marc Jones <marc.jones(a)amd.com> Index: coreboot-v2/src/southbridge/amd/cs5536/cs5536.c =================================================================== --- coreboot-v2.orig/src/southbridge/amd/cs5536/cs5536.c 2008-06-04 11:33:26.000000000 -0600 +++ coreboot-v2/src/southbridge/amd/cs5536/cs5536.c 2008-06-04 11:00:25.000000000 -0600 @@ -409,7 +409,7 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb) { - uint32_t *bar; + uint8_t *bar; msr_t msr; device_t dev; @@ -425,32 +425,33 @@ /* write to clear diag register */ wrmsr(USB2_SB_GLD_MSR_DIAG, rdmsr(USB2_SB_GLD_MSR_DIAG)); - bar = (uint32_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0); + bar = (uint8_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0); /* Make HCCPARAMS writeable */ - *(bar + IPREG04) |= USB_HCCPW_SET; + writel(readl(bar + IPREG04) | USB_HCCPW_SET, bar + IPREG04); /* ; EECP=50h, IST=01h, ASPC=1 */ - *(bar + HCCPARAMS) = 0x00005012; + writel(0x00005012, bar + HCCPARAMS); } dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_OTG, 0); if (dev) { - bar = (uint32_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0); + bar = (uint8_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0); - *(bar + UOCMUX) &= PUEN_SET; + writel(readl(bar + UOCMUX) & PUEN_SET, bar + UOCMUX); /* Host or Device? */ if (sb->enable_USBP4_device) { - *(bar + UOCMUX) |= PMUX_DEVICE; + writel(readl(bar + UOCMUX) | PMUX_DEVICE, bar + UOCMUX); } else { - *(bar + UOCMUX) |= PMUX_HOST; + writel(readl(bar + UOCMUX) | PMUX_HOST, bar + UOCMUX); } /* Overcurrent configuration */ if (sb->enable_USBP4_overcurrent) { - *(bar + UOCCAP) |= sb->enable_USBP4_overcurrent; + writel(readl(bar + UOCCAP) + | sb->enable_USBP4_overcurrent, bar + UOCCAP); } } @@ -464,19 +465,20 @@ dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_UDC, 0); if (dev) { - bar = (uint32_t *) pci_read_config32(dev, + bar = (uint8_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0); - *(bar + UDCDEVCTL) |= UDC_SD_SET; + writel(readl(bar + UDCDEVCTL) | UDC_SD_SET, + bar + UDCDEVCTL); } dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_OTG, 0); if (dev) { - bar = (uint32_t *) pci_read_config32(dev, + bar = (uint8_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0); - *(bar + UOCCTL) |= PADEN_SET; - *(bar + UOCCAP) |= APU_SET; + writel(readl(bar + UOCCTL) | PADEN_SET, bar + UOCCTL); + writel(readl(bar + UOCCAP) | APU_SET, bar + UOCCAP); } }

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[PATCH][v3] read actual memory size in qemu-i386
by Patrick Georgi 06 Jun '08

06 Jun '08

Hi, the attached patch makes the i440bx emulation read the cmos registers of the bochs/qemu emulation that carry RAM size information instead of assuming 128MB. Regards, Patrick Signed-Off-By: Patrick Georgi <patrick(a)georgi-clan.de> Index: northbridge/intel/i440bxemulation/domain =================================================================== --- northbridge/intel/i440bxemulation/domain (revision 689) +++ northbridge/intel/i440bxemulation/domain (working copy) @@ -19,6 +19,5 @@ */ { - ramsize = "128"; device_operations = "i440bx_domain"; }; Index: northbridge/intel/i440bxemulation/i440bx.c =================================================================== --- northbridge/intel/i440bxemulation/i440bx.c (revision 689) +++ northbridge/intel/i440bxemulation/i440bx.c (working copy) @@ -37,25 +37,40 @@ * such modified SOFTWARE should be clearly marked, so as not to confuse * it with the version available from LANL. */ + /* dynamic qemu ram size detection + Copyright 2008 Patrick Georgi <patrick(a)georgi-clan.de> + Licensed under the terms of the GNU General Public License v2 or later + */ #include <types.h> #include <console.h> #include <device/device.h> #include <device/pci.h> #include <string.h> +#include <io.h> #include "i440bx.h" #include "statictree.h" /* Here are the ops for 440BX as a PCI domain. */ +static int inb_cmos(int port) +{ + outb(port, 0x70); + return inb(0x71); +} + static void pci_domain_set_resources(struct device *dev) { struct device *mc_dev; u32 tolmk; /* Top of low mem, Kbytes. */ int idx; - struct northbridge_intel_i440bxemulation_domain_config *device_configuration = - dev->device_configuration; - tolmk = device_configuration->ramsize * 1024; + /* read large mem memory descriptor + for <16 MB read the more detailed small mem descriptor + all values in kbytes */ + tolmk = ((inb_cmos(0x35)<<8) |inb_cmos(0x34)) * 64; + if (tolmk <= 16 * 1024) { + tolmk = (inb_cmos(0x31)<<8) |inb_cmos(0x30); + } mc_dev = dev->link[0].children; if (mc_dev) { idx = 10;

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[PATCH][v3] Argument order in compiler options
by Patrick Georgi 06 Jun '08

06 Jun '08

Hi, For building coreboot v3 on cygwin, these changes (among others that I still clean up) are needed. Otherwise, it doesn't find the symbols in the libraries (ld arguments are parsed right-to-left). Regards, Patrick Georgi Signed-Off-By: Patrick Georgi <patrick(a)georgi-clan.de> Index: util/kconfig/lxdialog/Makefile =================================================================== --- util/kconfig/lxdialog/Makefile (revision 687) +++ util/kconfig/lxdialog/Makefile (working copy) @@ -24,8 +24,8 @@ $(obj)/util/kconfig/lxdialog/lxdialog: $(obj)/dochecklxdialog $(patsubst %,$(obj)/util/kconfig/lxdialog/%,$(lxdialog-objs)) $(Q)printf " HOSTCC $(subst $(shell pwd)/,,$(@))\n" - $(Q)$(HOSTCC) $(HOST_LOADLIBES) \ - $(patsubst %,$(obj)/util/kconfig/lxdialog/%,$(lxdialog-objs)) -o $@ + $(Q)$(HOSTCC) \ + $(patsubst %,$(obj)/util/kconfig/lxdialog/%,$(lxdialog-objs)) -o $@ $(HOST_LOADLIBES) $(obj)/util/kconfig/lxdialog/%.o: $(src)/util/kconfig/lxdialog/%.c $(Q)mkdir -p $(obj)/util/kconfig/lxdialog/ Index: util/kconfig/Makefile =================================================================== --- util/kconfig/Makefile (revision 687) +++ util/kconfig/Makefile (working copy) @@ -102,11 +102,11 @@ $(obj)/util/kconfig/mconf: $(patsubst %,$(obj)/util/kconfig/%,$(mconf-objects)) $(Q)printf " HOSTCC $(subst $(shell pwd)/,,$(@))\n" - $(Q)$(HOSTCC) $(CURSESLIBS) $(INTLLIBS) -o $@ $^ + $(Q)$(HOSTCC) -o $@ $^ $(CURSESLIBS) $(INTLLIBS) $(obj)/util/kconfig/conf: $(patsubst %,$(obj)/util/kconfig/%,$(conf-objects)) $(Q)printf " HOSTCC $(subst $(shell pwd)/,,$(@))\n" - $(Q)$(HOSTCC) $(CURSESLIBS) -o $@ $^ + $(Q)$(HOSTCC) -o $@ $^ $(CURSESLIBS) $(obj)/util/kconfig/qconf: $(patsubst %,$(obj)/util/kconfig/%,$(qconf-objects)) $(Q)printf " HOSTCXX $(subst $(shell pwd)/,,$(@))\n"

3 3

r690 - in coreboot-v3/util/kconfig: . lxdialog
by svn＠coreboot.org 06 Jun '08

06 Jun '08

Author: oxygene Date: 2008-06-06 22:47:42 +0200 (Fri, 06 Jun 2008) New Revision: 690 Modified: coreboot-v3/util/kconfig/Makefile coreboot-v3/util/kconfig/lxdialog/Makefile Log: Order libraries last on the command line when building kconfig and lxdialog, so that their content is used to resolve unknown symbols even when they are static libraries. Also fix HOST_LOADLIBS typo. Signed-Off-By: Patrick Georgi <patrick(a)georgi-clan.de> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: coreboot-v3/util/kconfig/Makefile =================================================================== --- coreboot-v3/util/kconfig/Makefile 2008-06-04 14:36:35 UTC (rev 689) +++ coreboot-v3/util/kconfig/Makefile 2008-06-06 20:47:42 UTC (rev 690) @@ -102,11 +102,11 @@ $(obj)/util/kconfig/mconf: $(patsubst %,$(obj)/util/kconfig/%,$(mconf-objects)) $(Q)printf " HOSTCC $(subst $(shell pwd)/,,$(@))\n" - $(Q)$(HOSTCC) $(CURSESLIBS) $(INTLLIBS) -o $@ $^ + $(Q)$(HOSTCC) -o $@ $^ $(CURSESLIBS) $(INTLLIBS) $(obj)/util/kconfig/conf: $(patsubst %,$(obj)/util/kconfig/%,$(conf-objects)) $(Q)printf " HOSTCC $(subst $(shell pwd)/,,$(@))\n" - $(Q)$(HOSTCC) $(CURSESLIBS) -o $@ $^ + $(Q)$(HOSTCC) -o $@ $^ $(CURSESLIBS) $(obj)/util/kconfig/qconf: $(patsubst %,$(obj)/util/kconfig/%,$(qconf-objects)) $(Q)printf " HOSTCXX $(subst $(shell pwd)/,,$(@))\n" Modified: coreboot-v3/util/kconfig/lxdialog/Makefile =================================================================== --- coreboot-v3/util/kconfig/lxdialog/Makefile 2008-06-04 14:36:35 UTC (rev 689) +++ coreboot-v3/util/kconfig/lxdialog/Makefile 2008-06-06 20:47:42 UTC (rev 690) @@ -8,14 +8,14 @@ # Use recursively expanded variables so we do not call gcc unless # we really need to do so. (Do not call gcc as part of make mrproper) HOST_EXTRACFLAGS = $(shell $(CONFIG_SHELL) $(check-lxdialog) -ccflags) -HOST_LOADLIBES = $(shell $(CONFIG_SHELL) $(check-lxdialog) -ldflags $(HOSTCC)) +HOST_LOADLIBS = $(shell $(CONFIG_SHELL) $(check-lxdialog) -ldflags $(HOSTCC)) HOST_EXTRACFLAGS += -DLOCALE .PHONY: dochecklxdialog $(obj)/dochecklxdialog: $(Q)printf " CHECK $(subst $(shell pwd)/,,$(@))\n" - $(Q)$(CONFIG_SHELL) $(check-lxdialog) -check $(HOSTCC) $(HOST_LOADLIBES) + $(Q)$(CONFIG_SHELL) $(check-lxdialog) -check $(HOSTCC) $(HOST_LOADLIBS) always := lxdialog dochecklxdialog @@ -24,8 +24,8 @@ $(obj)/util/kconfig/lxdialog/lxdialog: $(obj)/dochecklxdialog $(patsubst %,$(obj)/util/kconfig/lxdialog/%,$(lxdialog-objs)) $(Q)printf " HOSTCC $(subst $(shell pwd)/,,$(@))\n" - $(Q)$(HOSTCC) $(HOST_LOADLIBES) \ - $(patsubst %,$(obj)/util/kconfig/lxdialog/%,$(lxdialog-objs)) -o $@ + $(Q)$(HOSTCC) \ + $(patsubst %,$(obj)/util/kconfig/lxdialog/%,$(lxdialog-objs)) -o $@ $(HOST_LOADLIBS) $(obj)/util/kconfig/lxdialog/%.o: $(src)/util/kconfig/lxdialog/%.c $(Q)mkdir -p $(obj)/util/kconfig/lxdialog/

1 0

Problem with PLL
by Uwe Schwarz 06 Jun '08

06 Jun '08

Hi, I'm trying to boot coreboot v2 on a AMD db800 (Geode LX) Board. Around 30% of my boots it keeps freezing right after "Configuring PLL" during pll_reset. Is there anything I could try to figure out why it's doing that? // Uwe

3 3

VIA Northbridge K8T890 and SiS Northbridge: SiS 761GX
by bari 06 Jun '08

06 Jun '08

Anyone know why the VIA Northbridge K8T890 in the SVN in the southbridge directory? Why didn't the SiS 761GX make it into the SVN at all? -Bari

3 3

Re: [coreboot] coreboot & OpenSolaris
by Carl-Daniel Hailfinger 06 Jun '08

06 Jun '08

Hi, [please CC Jörg on replies, I don't know whether he is already subscribed to the list.] Jörg Schilling and I have been working to get flashrom to compile again under Solaris. The credit belongs to Jörg. The patch below is a first hack to get everything running and not completely ready for merging. Adding platform-specific #include statements to each file is suboptimal, I'd prefer to have them all in flash.h. Once we have a mergeable patch, I'd like to get a review from the person who created Solaris support in the first place. Besides that, we may want to disable compilation explicitly for any untested arch. Especially the problem that there is no agreed-upon order of out[bwl] arguments is a disaster waiting to happen if someone tests a new Linux-incompatible platform. Regards, Carl-Daniel On 04.06.2008 16:22, Joerg Schilling wrote: > Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> wrote: > > >> Hast Du evtl. einen unfertigen Patch, den ich durchs Review jagen kann? >> Es wäre klasse, wenn wir das vor dem Release 1.0 mergen können. >> > > hier ist erstmal mein aktueller Stand: > > --- Makefile.orig Di Jun 3 16:53:49 2008 > +++ Makefile Mi Jun 4 16:21:23 2008 > @@ -15,6 +15,8 @@ > OS_ARCH = $(shell uname) > ifeq ($(OS_ARCH), SunOS) > LDFLAGS = -lpci -lz > +CFLAGS += -I. > +LDFLAGS += -L/tmp/pciutils-2.2.10/lib/ > else > LDFLAGS = -lpci -lz > STRIP_ARGS = -s > @@ -52,7 +54,7 @@ > rm -f $(PROGRAM) .dependencies > > dep: > - @$(CC) -MM *.c > .dependencies > + $(CC) -M $(CFLAGS) $(OBJS:%.o=%.c) > .dependencies > > pciutils: > @echo; echo -n "Checking for pciutils and zlib... " > @@ -60,7 +62,7 @@ > echo "struct pci_access *pacc;"; \ > echo "int main(int argc, char **argv)"; \ > echo "{ pacc = pci_alloc(); return 0; }"; ) > .test.c ) > - @$(CC) $(CFLAGS) .test.c -o .test $(LDFLAGS) &>/dev/null && \ > + @$(CC) $(CFLAGS) .test.c -o .test $(LDFLAGS) >/dev/null 2>&1 && \ > echo "found." || ( echo "not found."; echo; \ > echo "Please install pciutils-devel and zlib-devel."; \ > echo "See README for more information."; echo; \ > Index: flash.h > =================================================================== > --- flash.h (revision 3360) > +++ flash.h (working copy) > @@ -41,6 +41,14 @@ > #define INW(x) __extension__ ({ u_int tmp = (x); inw(tmp); }) > #define INL(x) __extension__ ({ u_int tmp = (x); inl(tmp); }) > #else > +#ifdef __sun > + #define OUTB(x, y) outb(y, x) > + #define OUTW(x, y) outw(y, x) > + #define OUTL(x, y) outl(y, x) > + #define INB inb > + #define INW inw > + #define INL inl > +#else > #define OUTB outb > #define OUTW outw > #define OUTL outl > @@ -48,6 +56,7 @@ > #define INW inw > #define INL inl > #endif > +#endif > > #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) > > @@ -357,7 +366,7 @@ > > /* udelay.c */ > void myusec_delay(int time); > -void myusec_calibrate_delay(); > +void myusec_calibrate_delay(void); > > /* PCI handling for board/chipset_enable */ > struct pci_access *pacc; > @@ -406,12 +415,12 @@ > int probe_spi_rdid(struct flashchip *flash); > int probe_spi_res(struct flashchip *flash); > int spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); > -void spi_write_enable(); > -void spi_write_disable(); > +void spi_write_enable(void); > +void spi_write_disable(void); > int spi_chip_erase_c7(struct flashchip *flash); > int spi_chip_write(struct flashchip *flash, uint8_t *buf); > int spi_chip_read(struct flashchip *flash, uint8_t *buf); > -uint8_t spi_read_status_register(); > +uint8_t spi_read_status_register(void); > void spi_disable_blockprotect(void); > void spi_byte_program(int address, uint8_t byte); > void spi_page_program(int block, uint8_t *buf, uint8_t *bios); > @@ -450,6 +459,8 @@ > volatile uint8_t *dst); > int probe_jedec(struct flashchip *flash); > int erase_chip_jedec(struct flashchip *flash); > +int write_page_write_jedec(volatile uint8_t *bios, uint8_t *src, > + volatile uint8_t *dst, int page_size); > int write_jedec(struct flashchip *flash, uint8_t *buf); > int erase_sector_jedec(volatile uint8_t *bios, unsigned int page); > int erase_block_jedec(volatile uint8_t *bios, unsigned int page); > Index: it87spi.c > =================================================================== > --- it87spi.c (revision 3360) > +++ it87spi.c (working copy) > @@ -26,6 +26,10 @@ > #include <pci/pci.h> > #include <stdint.h> > #include <string.h> > +/* for outb(),... */ > +#if defined (__sun) && (defined(__i386) || defined(__amd64)) > +#include <asm/sunddi.h> /* XXX nonportable gcc/_KERNEL only, may disappear */ > +#endif > #include "flash.h" > #include "spi.h" > > Index: chipset_enable.c > =================================================================== > --- chipset_enable.c (revision 3360) > +++ chipset_enable.c (working copy) > @@ -33,6 +33,10 @@ > #include <sys/mman.h> > #include <fcntl.h> > #include <unistd.h> > +/* for outb(),... */ > +#if defined (__sun) && (defined(__i386) || defined(__amd64)) > +#include <asm/sunddi.h> /* XXX nonportable gcc/_KERNEL only, may disappear */ > +#endif > #include "flash.h" > > static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name) > Index: flashrom.c > =================================================================== > --- flashrom.c (revision 3360) > +++ flashrom.c (working copy) > @@ -33,10 +33,9 @@ > #include <pci/pci.h> > /* for iopl */ > #if defined (__sun) && (defined(__i386) || defined(__amd64)) > -#include <strings.h> > #include <sys/sysi86.h> > #include <sys/psw.h> > -#include <asm/sunddi.h> > +#include <asm/sunddi.h> /* XXX nonportable gcc/_KERNEL only, may disappear */ > #endif > #include "flash.h" > > Index: board_enable.c > =================================================================== > --- board_enable.c (revision 3360) > +++ board_enable.c (working copy) > @@ -29,6 +29,10 @@ > #include <stdint.h> > #include <string.h> > #include <fcntl.h> > +/* for outb(),... */ > +#if defined (__sun) && (defined(__i386) || defined(__amd64)) > +#include <asm/sunddi.h> /* XXX nonportable gcc/_KERNEL only, may disappear */ > +#endif > #include "flash.h" > > /* > Jörg > > -- http://www.hailfinger.org/

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Fwd: Re: Open Firmware
by Carl-Daniel Hailfinger 06 Jun '08

06 Jun '08

Hi all, I felt compelled to respond to the post by Werner Almesberger on openmoko-kernel, but forgot to CC it here, so you get it as forwarded mail. Regards, Carl-Daniel -------- Original Message -------- Subject: Re: Open Firmware Date: Thu, 05 Jun 2008 22:16:37 +0200 From: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> To: openmoko-kernel(a)lists.openmoko.org References: 7780e76c0805231833x58ac3655j34e2eb1ee9bdbe40(a)mail.gmail.com Hi all, sorry for appearing out of nowhere. I have been following Openmoko for quite some time and I'm very pleasantly surprised by what has been achieved in such short time. Werner Almesberger wrote: > I wonder what troubles OLPC ran into with LinuxBIOS. I can understand > the slow boot time issues, but it should be easy enough to add a > fastpath for this. As someone who participated in early porting of LinuxBIOS (now coreboot) to the OLPC platform, I feel I'm qualified to answer this. Basically, in the beginning there was a choice between a proprietary BIOS and LinuxBIOS+Linux in the ROM. Since LinuxBIOS-Linux worked so well, that solution was chosen. However, size constraints of the ROM eventually led to the conclusion that something smaller than a full Linux kernel in the ROM was desirable. At that point, OpenFirmware became open source and it was subsequently used in combination with LinuxBIOS in the ROM. After some time, Mitch Bradley (OpenFirmware creator and expert) was (iirc) hired by OLPC to work on the firmware full time. Since he's an OpenFirmware expert and was not too familiar with the LinuxBIOS code, he eventually decided to move early hardware init into OpenFirmware and remove LinuxBIOS. The slow boot time was only partially (~10%) caused by LinuxBIOS version 2 and that issue has been fixed in coreboot v3. I have seen rather slow AMD Geode machines run through coreboot v3 initialization in 500 ms (including RAM setup, PCI setup etc.), so 500 ms after poweron you get to pass execution to a Linux kernel. Depending on your hardware, faster startup is possible. At the beginning of this year, LinuxBIOS was renamed to coreboot because we're neither a BIOS nor do we have Linux dependencies. However, we optionally support a Linux kernel (and a traditional BIOS emulation if anyone wants that) as a so-called payload, the thing that's executed directly after the lowlevel hardware init has been performed. We (the coreboot team) are very interested in validating our brand new coreboot version 3 design on multiple architectures. It works well on x86 (AMD GeodeLX is tested right now) and you can bundle it with a Linux kernel in ROM easily. We call that scenario LAB (Linux As Bootloader) and some people use it heavily. Since coreboot supports LZMA compressed payloads natively, having a complete Linux kernel in ROM is not a big size challenge anymore. If anybody wants to port coreboot to the FreeRunner or any other platform, we'd be happy to help. A first look at the code is probably easiest if you pick the coreboot v3 qemu(x86) target and work from there. More info about coreboot is available at http://www.coreboot.org/ . The mailing list is http://www.coreboot.org/mailman/listinfo/coreboot IRC (may be a bit slow to respond) http://www.coreboot.org/IRC If you have any questions, want a short demo, pointers to "cool features" lists or a generic introduction, feel free to ask either me personally or all developers via our mailing list. Regards, Carl-Daniel -- http://www.hailfinger.org/

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coreboot June 2008