coreboot October 2008

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[PATCH][V3] C7 Finishing touches
by Corey Osgood 11 Oct '08

11 Oct '08

Patch attached.

2 3

r918 - in coreboot-v3/include: . arch/x86
by svn＠coreboot.org 11 Oct '08

11 Oct '08

Author: cozzie Date: 2008-10-12 02:51:10 +0200 (Sun, 12 Oct 2008) New Revision: 918 Added: coreboot-v3/include/arch/x86/via_c7.h Modified: coreboot-v3/include/globalvars.h Log: Add the last bits to support C7 in v3 Signed-off-by: Corey Osgood <corey.osgood(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Added: coreboot-v3/include/arch/x86/via_c7.h =================================================================== --- coreboot-v3/include/arch/x86/via_c7.h (rev 0) +++ coreboot-v3/include/arch/x86/via_c7.h 2008-10-12 00:51:10 UTC (rev 918) @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Corey Osgood <corey.osgood(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef CPU_VIA_C7_H +#define CPU_VIA_C7_H + + +#ifndef __ASSEMBLER__ + +/* This is new. + * We're not using it yet. + * K8 requires it and, for future ports, we are going to require it. + * it's a useful placeholder for platform info that usually ends up + * scattered everywhere. On K8, it is stored near the base of stack + * in the global variable struct. + */ +struct sys_info { + int empty; +}; + +#endif + +#endif Modified: coreboot-v3/include/globalvars.h =================================================================== --- coreboot-v3/include/globalvars.h 2008-10-11 17:42:23 UTC (rev 917) +++ coreboot-v3/include/globalvars.h 2008-10-12 00:51:10 UTC (rev 918) @@ -35,6 +35,10 @@ #include <qemu.h> #endif +#ifdef CONFIG_CPU_VIA_C7 +#include <via_c7.h> +#endif + /* * struct global_vars is managed entirely from C code. Keep in mind that there * is NO buffer at the end of the struct, so having zero-sized arrays at the

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corebootV2 Can support IEI lx-800 mainboard?
by wangdu2002 11 Oct '08

11 Oct '08

I am a Chinese,I brower your site,I am sorry,my english is poor. I have a mainboard ,IEI lx-800 ,cpu Amd Geode 500HZ,like support mainboard lists IEI pcisa-lx-800,corebootV2 Can support this mainboard? this board datasheet in appendix. http://www.iei.com.tw can fund it. thanks you for free software!

10 13

r917 - coreboot-v3/superio/fintek/f71805f
by svn＠coreboot.org 11 Oct '08

11 Oct '08

Author: cozzie Date: 2008-10-11 19:42:23 +0200 (Sat, 11 Oct 2008) New Revision: 917 Modified: coreboot-v3/superio/fintek/f71805f/dts coreboot-v3/superio/fintek/f71805f/f71805f.h coreboot-v3/superio/fintek/f71805f/stage1.c coreboot-v3/superio/fintek/f71805f/superio.c Log: Make some changes to the Fintek F71805f: * Read port for early serial console from Kconfig * Change naming from SP (serial port) to COM to be consistent with Kconfig Signed-off-by: Corey Osgood <corey.osgood(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: coreboot-v3/superio/fintek/f71805f/dts =================================================================== --- coreboot-v3/superio/fintek/f71805f/dts 2008-10-11 01:01:07 UTC (rev 916) +++ coreboot-v3/superio/fintek/f71805f/dts 2008-10-11 17:42:23 UTC (rev 917) @@ -33,19 +33,17 @@ ppio = "0x378"; ppirq = "7"; - /* Note: renaming from comx to spx may have broken the DTS - * We'll find out later */ /* Serial Port 1 */ - sp1dev = "2"; - sp1enable = "1"; - sp1io = "0x3f8"; - sp1irq = "4"; + com1dev = "2"; + com1enable = "1"; + com1io = "0x3f8"; + com1irq = "4"; /* Serial Port 2 */ - sp2dev = "3"; - sp2enable = "1"; - sp2io = "0x2f8"; - sp2irq = "3"; + com2dev = "3"; + com2enable = "1"; + com2io = "0x2f8"; + com2irq = "3"; /* Hardware Monitor */ hwmdev = "0xb"; Modified: coreboot-v3/superio/fintek/f71805f/f71805f.h =================================================================== --- coreboot-v3/superio/fintek/f71805f/f71805f.h 2008-10-11 01:01:07 UTC (rev 916) +++ coreboot-v3/superio/fintek/f71805f/f71805f.h 2008-10-11 17:42:23 UTC (rev 917) @@ -26,12 +26,12 @@ * - Revision: V0.25P */ -void f71805f_enable_serial(u8, u8, u16); +void f71805f_enable_serial(u8); /* Logical Device Numbers (LDN). */ #define F71805F_FDC 0x00 /* Floppy */ -#define F71805F_SP1 0x01 /* UART1 */ -#define F71805F_SP2 0x02 /* UART2 */ +#define F71805F_COM1 0x01 /* UART1 */ +#define F71805F_COM2 0x02 /* UART2 */ #define F71805F_PP 0x03 /* Parallel Port */ #define F71805F_HWM 0x04 /* Hardware Monitor */ #define F71805F_GPIO 0x06 /* General Purpose I/O (GPIO) */ Modified: coreboot-v3/superio/fintek/f71805f/stage1.c =================================================================== --- coreboot-v3/superio/fintek/f71805f/stage1.c 2008-10-11 01:01:07 UTC (rev 916) +++ coreboot-v3/superio/fintek/f71805f/stage1.c 2008-10-11 17:42:23 UTC (rev 917) @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright 2007 Corey Osgood <corey.osgood(a)gmail.com> + * Copyright 2008 Corey Osgood <corey.osgood(a)gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,24 +18,32 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <io.h> +#include <config.h> #include <device/pnp.h> #include "f71805f.h" -static inline void f71805f_rawpnp_enter_ext_func_mode(u8 dev) +void f71805f_enable_serial(u8 dev) { - /* Fintek F71805f needs this only once, but Winbond needs it twice. - * Perhaps modify rawpnp_enter_ext_func_mode() to only do it once, - * then modify the winbond to call it twice? */ - outb(0x87, dev); -} + u8 serial_ldn; + u16 serial_iobase; -void f71805f_enable_serial(u8 dev, u8 serial, u16 iobase) -{ - f71805f_rawpnp_enter_ext_func_mode(dev); - rawpnp_set_logical_device(dev, serial); + /* Serial port info from Kconfig (FTW!). Would be even more + * awesome if we could get 'dev' from Kconfig or dts */ + /* TODO: Get/set serial port speed divisor from Kconfig as well */ +#if defined (CONFIG_CONSOLE_SERIAL_COM1) && CONFIG_CONSOLE_SERIAL_COM1 + serial_ldn = F71805F_COM1; + serial_iobase = 0x3f8; +#elif defined (CONFIG_CONSOLE_SERIAL_COM2) && CONFIG_CONSOLE_SERIAL_COM2 + serial_ldn = F71805F_COM2; + serial_iobase = 0x2f8; +#else /* No serial console */ + return; +#endif + + rawpnp_enter_ext_func_mode(dev); + rawpnp_set_logical_device(dev, serial_ldn); rawpnp_set_enable(dev, 0); - rawpnp_set_iobase(dev, PNP_IDX_IO0, iobase); + rawpnp_set_iobase(dev, PNP_IDX_IO0, serial_iobase); rawpnp_set_enable(dev, 1); rawpnp_exit_ext_func_mode(dev); } Modified: coreboot-v3/superio/fintek/f71805f/superio.c =================================================================== --- coreboot-v3/superio/fintek/f71805f/superio.c 2008-10-11 01:01:07 UTC (rev 916) +++ coreboot-v3/superio/fintek/f71805f/superio.c 2008-10-11 17:42:23 UTC (rev 917) @@ -79,15 +79,15 @@ return; switch (dev->path.pnp.device) { - case F71805F_SP1: + case F71805F_COM1: res0 = find_resource(dev, PNP_IDX_IO0); - //TODO: needed? fix or remove? - //init_uart8250(res0->base, &conf->sp1); + /* TODO: Fix these */ + //uart8250_init(res0->base, &conf->sp1); break; - case F71805F_SP2: + case F71805F_COM2: res1 = find_resource(dev, PNP_IDX_IO0); - //init_uart8250(res0->base, &conf->sp2); + //uart8250_init(res0->base, &conf->sp2); break; /* No KBC on F71805f */ @@ -106,8 +106,8 @@ }; static struct pnp_info pnp_dev_info[] = { - { &f71805f_ops, F71805F_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &f71805f_ops, F71805F_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &f71805f_ops, F71805F_COM1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &f71805f_ops, F71805F_COM2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, /* TODO: Everything else */ };

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[PATCH][v3] Fintek F71805f improvements
by Corey Osgood 11 Oct '08

11 Oct '08

See attached patch. Tested to build and work.

3 4

[PATCH] v2: Drop duplicated/unused failover.c files
by Uwe Hermann 11 Oct '08

11 Oct '08

See patch. Some other failover.c files (which are different from the current global failover.c) remain for now. That's for another patch maybe. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

2 2

r3649 - in trunk/coreboot-v2/src/mainboard: amd/db800 amd/norwich amd/rumba artecgroup/dbe61 asi/mb_5blmp asus/mew-vm digitallogic/adl855pc digitallogic/msm586seg digitallogic/msm800sev eaglelion/5bcm iei/juki-511p lippert/frontrunner pcengines/alix1c technologic/ts5300 via/epia
by svn＠coreboot.org 11 Oct '08

11 Oct '08

Author: uwe Date: 2008-10-11 18:10:54 +0200 (Sat, 11 Oct 2008) New Revision: 3649 Removed: trunk/coreboot-v2/src/mainboard/amd/db800/failover.c trunk/coreboot-v2/src/mainboard/amd/norwich/failover.c trunk/coreboot-v2/src/mainboard/amd/rumba/failover.c trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/failover.c trunk/coreboot-v2/src/mainboard/asus/mew-vm/failover.c trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/failover.c trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/failover.c trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/failover.c trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/failover.c trunk/coreboot-v2/src/mainboard/iei/juki-511p/failover.c trunk/coreboot-v2/src/mainboard/lippert/frontrunner/failover.c trunk/coreboot-v2/src/mainboard/pcengines/alix1c/failover.c trunk/coreboot-v2/src/mainboard/technologic/ts5300/failover.c trunk/coreboot-v2/src/mainboard/via/epia/failover.c Modified: trunk/coreboot-v2/src/mainboard/amd/rumba/Config.lb trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Config.lb trunk/coreboot-v2/src/mainboard/asus/mew-vm/Config.lb trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Config.lb trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Config.lb trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Config.lb trunk/coreboot-v2/src/mainboard/iei/juki-511p/Config.lb trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Config.lb trunk/coreboot-v2/src/mainboard/technologic/ts5300/Config.lb trunk/coreboot-v2/src/mainboard/via/epia/Config.lb Log: Drop a number of duplicated failover.c files (they have the same content as the global src/arch/i386/lib/failover.c file). Also, drop a number of dummy failover.c files which are not even used at all. This is abuild-tested by me. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Deleted: trunk/coreboot-v2/src/mainboard/amd/db800/failover.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/db800/failover.c 2008-10-10 20:54:41 UTC (rev 3648) +++ trunk/coreboot-v2/src/mainboard/amd/db800/failover.c 2008-10-11 16:10:54 UTC (rev 3649) @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#define ASSEMBLY 1 - -#include <stdint.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include "pc80/mc146818rtc_early.c" - -static unsigned long main(unsigned long bist) -{ - return bist; -} Deleted: trunk/coreboot-v2/src/mainboard/amd/norwich/failover.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/norwich/failover.c 2008-10-10 20:54:41 UTC (rev 3648) +++ trunk/coreboot-v2/src/mainboard/amd/norwich/failover.c 2008-10-11 16:10:54 UTC (rev 3649) @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#define ASSEMBLY 1 - -#include <stdint.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include "pc80/mc146818rtc_early.c" - -static unsigned long main(unsigned long bist) -{ - return bist; -} Modified: trunk/coreboot-v2/src/mainboard/amd/rumba/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/rumba/Config.lb 2008-10-10 20:54:41 UTC (rev 3648) +++ trunk/coreboot-v2/src/mainboard/amd/rumba/Config.lb 2008-10-11 16:10:54 UTC (rev 3649) @@ -51,13 +51,13 @@ ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E Deleted: trunk/coreboot-v2/src/mainboard/amd/rumba/failover.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/rumba/failover.c 2008-10-10 20:54:41 UTC (rev 3648) +++ trunk/coreboot-v2/src/mainboard/amd/rumba/failover.c 2008-10-11 16:10:54 UTC (rev 3649) @@ -1,32 +0,0 @@ -#define ASSEMBLY 1 -#include <stdint.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include "arch/romcc_io.h" -#include "pc80/mc146818rtc_early.c" - -static unsigned long main(unsigned long bist) -{ - /* This is the primary cpu how should I boot? */ - if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); - cpu_reset: - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: - return bist; -} Deleted: trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/failover.c =================================================================== --- trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/failover.c 2008-10-10 20:54:41 UTC (rev 3648) +++ trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/failover.c 2008-10-11 16:10:54 UTC (rev 3649) @@ -1,32 +0,0 @@ -#define ASSEMBLY 1 -#include <stdint.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include "arch/romcc_io.h" -#include "pc80/mc146818rtc_early.c" - -static unsigned long main(unsigned long bist) -{ - /* This is the primary cpu how should I boot? */ - if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); - cpu_reset: - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: - return bist; -} Modified: trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Config.lb 2008-10-10 20:54:41 UTC (rev 3648) +++ trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/Config.lb 2008-10-11 16:10:54 UTC (rev 3649) @@ -52,13 +52,13 @@ ## Romcc output ## # makerule ./failover.E -# depends "$(MAINBOARD)/failover.c ../romcc" -# action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" +# depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" +# action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" # end # # makerule ./failover.inc -# depends "$(MAINBOARD)/failover.c ../romcc" -# action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" +# depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" +# action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" # end makerule ./auto.E Modified: trunk/coreboot-v2/src/mainboard/asus/mew-vm/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/mew-vm/Config.lb 2008-10-10 20:54:41 UTC (rev 3648) +++ trunk/coreboot-v2/src/mainboard/asus/mew-vm/Config.lb 2008-10-11 16:10:54 UTC (rev 3649) @@ -51,13 +51,13 @@ ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E Deleted: trunk/coreboot-v2/src/mainboard/asus/mew-vm/failover.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/mew-vm/failover.c 2008-10-10 20:54:41 UTC (rev 3648) +++ trunk/coreboot-v2/src/mainboard/asus/mew-vm/failover.c 2008-10-11 16:10:54 UTC (rev 3649) @@ -1,32 +0,0 @@ -#define ASSEMBLY 1 -#include <stdint.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include "arch/romcc_io.h" -#include "pc80/mc146818rtc_early.c" - -static unsigned long main(unsigned long bist) -{ - /* This is the primary cpu how should I boot? */ - if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); - cpu_reset: - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: - return bist; -} Modified: trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Config.lb 2008-10-10 20:54:41 UTC (rev 3648) +++ trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Config.lb 2008-10-11 16:10:54 UTC (rev 3649) @@ -50,13 +50,13 @@ ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E Deleted: trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/failover.c =================================================================== --- trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/failover.c 2008-10-10 20:54:41 UTC (rev 3648) +++ trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/failover.c 2008-10-11 16:10:54 UTC (rev 3649) @@ -1,32 +0,0 @@ -#define ASSEMBLY 1 -#include <stdint.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include "arch/romcc_io.h" -#include "pc80/mc146818rtc_early.c" - -static unsigned long main(unsigned long bist) -{ - /* This is the primary cpu how should I boot? */ - if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); - cpu_reset: - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: - return bist; -} Modified: trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Config.lb 2008-10-10 20:54:41 UTC (rev 3648) +++ trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/Config.lb 2008-10-11 16:10:54 UTC (rev 3649) @@ -52,13 +52,13 @@ ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E Deleted: trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/failover.c =================================================================== --- trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/failover.c 2008-10-10 20:54:41 UTC (rev 3648) +++ trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/failover.c 2008-10-11 16:10:54 UTC (rev 3649) @@ -1,32 +0,0 @@ -#define ASSEMBLY 1 -#include <stdint.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include "arch/romcc_io.h" -#include "pc80/mc146818rtc_early.c" - -static unsigned long main(unsigned long bist) -{ - /* This is the primary cpu how should I boot? */ - if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); - cpu_reset: - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: - return bist; -} Deleted: trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/failover.c =================================================================== --- trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/failover.c 2008-10-10 20:54:41 UTC (rev 3648) +++ trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/failover.c 2008-10-11 16:10:54 UTC (rev 3649) @@ -1,32 +0,0 @@ -#define ASSEMBLY 1 -#include <stdint.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include "arch/romcc_io.h" -#include "pc80/mc146818rtc_early.c" - -static unsigned long main(unsigned long bist) -{ - /* This is the primary cpu how should I boot? */ - if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); - cpu_reset: - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: - return bist; -} Modified: trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Config.lb 2008-10-10 20:54:41 UTC (rev 3648) +++ trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/Config.lb 2008-10-11 16:10:54 UTC (rev 3649) @@ -51,13 +51,13 @@ ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E Deleted: trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/failover.c =================================================================== --- trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/failover.c 2008-10-10 20:54:41 UTC (rev 3648) +++ trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/failover.c 2008-10-11 16:10:54 UTC (rev 3649) @@ -1,32 +0,0 @@ -#define ASSEMBLY 1 -#include <stdint.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include "arch/romcc_io.h" -#include "pc80/mc146818rtc_early.c" - -static unsigned long main(unsigned long bist) -{ - /* This is the primary cpu how should I boot? */ - if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); - cpu_reset: - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: - return bist; -} Modified: trunk/coreboot-v2/src/mainboard/iei/juki-511p/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/iei/juki-511p/Config.lb 2008-10-10 20:54:41 UTC (rev 3648) +++ trunk/coreboot-v2/src/mainboard/iei/juki-511p/Config.lb 2008-10-11 16:10:54 UTC (rev 3649) @@ -47,13 +47,13 @@ ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E Deleted: trunk/coreboot-v2/src/mainboard/iei/juki-511p/failover.c =================================================================== --- trunk/coreboot-v2/src/mainboard/iei/juki-511p/failover.c 2008-10-10 20:54:41 UTC (rev 3648) +++ trunk/coreboot-v2/src/mainboard/iei/juki-511p/failover.c 2008-10-11 16:10:54 UTC (rev 3649) @@ -1,53 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov(a)gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#define ASSEMBLY 1 - -#include <stdint.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include "arch/romcc_io.h" -#include "pc80/mc146818rtc_early.c" - -static unsigned long main(unsigned long bist) -{ - /* This is the primary cpu how should I boot? */ - if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } -normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); -cpu_reset: - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - : /* clobbers */ - ); -fallback_image: - return bist; -} Modified: trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Config.lb 2008-10-10 20:54:41 UTC (rev 3648) +++ trunk/coreboot-v2/src/mainboard/lippert/frontrunner/Config.lb 2008-10-11 16:10:54 UTC (rev 3649) @@ -51,13 +51,13 @@ ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E Deleted: trunk/coreboot-v2/src/mainboard/lippert/frontrunner/failover.c =================================================================== --- trunk/coreboot-v2/src/mainboard/lippert/frontrunner/failover.c 2008-10-10 20:54:41 UTC (rev 3648) +++ trunk/coreboot-v2/src/mainboard/lippert/frontrunner/failover.c 2008-10-11 16:10:54 UTC (rev 3649) @@ -1,32 +0,0 @@ -#define ASSEMBLY 1 -#include <stdint.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include "arch/romcc_io.h" -#include "pc80/mc146818rtc_early.c" - -static unsigned long main(unsigned long bist) -{ - /* This is the primary cpu how should I boot? */ - if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); - cpu_reset: - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: - return bist; -} Deleted: trunk/coreboot-v2/src/mainboard/pcengines/alix1c/failover.c =================================================================== --- trunk/coreboot-v2/src/mainboard/pcengines/alix1c/failover.c 2008-10-10 20:54:41 UTC (rev 3648) +++ trunk/coreboot-v2/src/mainboard/pcengines/alix1c/failover.c 2008-10-11 16:10:54 UTC (rev 3649) @@ -1,32 +0,0 @@ -#define ASSEMBLY 1 -#include <stdint.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include "arch/romcc_io.h" -#include "pc80/mc146818rtc_early.c" - -static unsigned long main(unsigned long bist) -{ - /* This is the primary cpu how should I boot? */ - if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); - cpu_reset: - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: - return bist; -} Modified: trunk/coreboot-v2/src/mainboard/technologic/ts5300/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/technologic/ts5300/Config.lb 2008-10-10 20:54:41 UTC (rev 3648) +++ trunk/coreboot-v2/src/mainboard/technologic/ts5300/Config.lb 2008-10-11 16:10:54 UTC (rev 3649) @@ -52,13 +52,13 @@ ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E Deleted: trunk/coreboot-v2/src/mainboard/technologic/ts5300/failover.c =================================================================== --- trunk/coreboot-v2/src/mainboard/technologic/ts5300/failover.c 2008-10-10 20:54:41 UTC (rev 3648) +++ trunk/coreboot-v2/src/mainboard/technologic/ts5300/failover.c 2008-10-11 16:10:54 UTC (rev 3649) @@ -1,32 +0,0 @@ -#define ASSEMBLY 1 -#include <stdint.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include "arch/romcc_io.h" -#include "pc80/mc146818rtc_early.c" - -static unsigned long main(unsigned long bist) -{ - /* This is the primary cpu how should I boot? */ - if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); - cpu_reset: - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: - return bist; -} Modified: trunk/coreboot-v2/src/mainboard/via/epia/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia/Config.lb 2008-10-10 20:54:41 UTC (rev 3648) +++ trunk/coreboot-v2/src/mainboard/via/epia/Config.lb 2008-10-11 16:10:54 UTC (rev 3649) @@ -50,13 +50,13 @@ ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" end makerule ./auto.E Deleted: trunk/coreboot-v2/src/mainboard/via/epia/failover.c =================================================================== --- trunk/coreboot-v2/src/mainboard/via/epia/failover.c 2008-10-10 20:54:41 UTC (rev 3648) +++ trunk/coreboot-v2/src/mainboard/via/epia/failover.c 2008-10-11 16:10:54 UTC (rev 3649) @@ -1,32 +0,0 @@ -#define ASSEMBLY 1 -#include <stdint.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include "arch/romcc_io.h" -#include "pc80/mc146818rtc_early.c" - -static unsigned long main(unsigned long bist) -{ - /* This is the primary cpu how should I boot? */ - if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); - cpu_reset: - asm volatile ("jmp __cpu_reset" - : /* outputs */ - : "a"(bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: - return bist; -}

1 0

r916 - in coreboot-v3/arch/x86: . i586 via
by svn＠coreboot.org 10 Oct '08

10 Oct '08

Author: hailfinger Date: 2008-10-11 03:01:07 +0200 (Sat, 11 Oct 2008) New Revision: 916 Modified: coreboot-v3/arch/x86/Kconfig coreboot-v3/arch/x86/i586/stage0.S coreboot-v3/arch/x86/via/stage0.S Log: Whitespace fixes, readability improvements. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: coreboot-v3/arch/x86/Kconfig =================================================================== --- coreboot-v3/arch/x86/Kconfig 2008-10-11 00:07:36 UTC (rev 915) +++ coreboot-v3/arch/x86/Kconfig 2008-10-11 01:01:07 UTC (rev 916) @@ -64,7 +64,6 @@ arch/x86/Makefile for more hints on possible values. It is usually set in mainboard/*/Kconfig. - config CONFIG_HPET boolean depends CPU_AMD_K8 Modified: coreboot-v3/arch/x86/i586/stage0.S =================================================================== --- coreboot-v3/arch/x86/i586/stage0.S 2008-10-11 00:07:36 UTC (rev 915) +++ coreboot-v3/arch/x86/i586/stage0.S 2008-10-11 01:01:07 UTC (rev 916) @@ -69,21 +69,15 @@ .align 4 - - -/* We will use 4Kbytes only for cache as ram. This is - * enough to fit in our stack. - * - * disable HyperThreading is done by eswar +/* disable HyperThreading is done by eswar * the other is very similar to the AMD CAR, except remove amd specific msr */ #define CacheSize CONFIG_CARSIZE - #define CacheBase CONFIG_CARBASE #define ASSEMBLY -#include "mtrr.h" +#include <mtrr.h> /* Save the BIST result */ movl %eax, %ebp @@ -175,6 +169,7 @@ /* Clear all MTRRs */ xorl %edx, %edx movl $fixed_mtrr_msr, %esi + clear_fixed_var_mtrr: lodsl (%esi), %eax testl %eax, %eax @@ -331,8 +326,7 @@ lout: /* Store zero for the pointer to the global variables. */ - movl $0, %eax - pushl %eax + pushl $0 /* Restore the BIST result. */ movl %ebp, %eax Modified: coreboot-v3/arch/x86/via/stage0.S =================================================================== --- coreboot-v3/arch/x86/via/stage0.S 2008-10-11 00:07:36 UTC (rev 915) +++ coreboot-v3/arch/x86/via/stage0.S 2008-10-11 01:01:07 UTC (rev 916) @@ -1,6 +1,6 @@ -/* +/* * This file is part of the coreboot project. - * + * * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com> * Copyright (C) 2005 Eswar Nallusamy, LANL * Copyright (C) 2005 Tyan @@ -10,16 +10,16 @@ * Copyright (C) 2007,2008 Carl-Daniel Hailfinger * Copyright (C) 2008 VIA Technologies, Inc. * (Written by Jason Zhao <jasonzhao(a)viatech.com.cn> for VIA) - * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. - * + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA

1 0

r915 - in coreboot-v3/arch/x86: . via
by svn＠coreboot.org 10 Oct '08

10 Oct '08

Author: hailfinger Date: 2008-10-11 02:07:36 +0200 (Sat, 11 Oct 2008) New Revision: 915 Added: coreboot-v3/arch/x86/via/ coreboot-v3/arch/x86/via/stage0.S Modified: coreboot-v3/arch/x86/Kconfig coreboot-v3/arch/x86/Makefile Log: Add support for Cache-as-RAM on VIA C7 processors in v3. This required lots of preparatory work to not make the existing stage0 situation worse. Thanks to Jason Zhao we got a skeleton CAR code for VIA C7 based on older v2 code. I cleaned it up, modified it to fit into the improved v3 stage0 code infrastructure and believe this is mostly merge-ready. Thanks to Bari Ari for getting the code to me for rewrite/review. Thanks to Corey Osgood who kept me going with helpful early tests and motivation. Thanks to everybody who reviewed my code. CONFIG_CARTEST shall not be enabled (breaks the build). CONFIG_XIP_ROM_{SIZE,BASE} shall not be set (breaks the build). Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Signed-off-by: Jason Zhao <jasonzhao(a)viatech.com.cn> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/arch/x86/Kconfig =================================================================== --- coreboot-v3/arch/x86/Kconfig 2008-10-10 20:37:02 UTC (rev 914) +++ coreboot-v3/arch/x86/Kconfig 2008-10-11 00:07:36 UTC (rev 915) @@ -56,6 +56,15 @@ arch/x86/Makefile for more hints on possible values. It is usually set in mainboard/*/Kconfig. +config CPU_VIA_C7 + boolean + help + CPU type. At the moment this option selects the reset vector and + Cache-as-RAM (CAR) implementation for a mainboard. See + arch/x86/Makefile for more hints on possible values. + It is usually set in mainboard/*/Kconfig. + + config CONFIG_HPET boolean depends CPU_AMD_K8 @@ -159,6 +168,7 @@ default 0x8f000 if CPU_I586 default 0x80000 if CPU_AMD_GEODELX default 0xc8000 if CPU_AMD_K8 + default 0xffef0000 if CPU_VIA_C7 help This option sets the base address of the area used for CAR. @@ -167,6 +177,7 @@ default 0x1000 if CPU_I586 default 0x8000 if CPU_AMD_GEODELX default 0x8000 if CPU_AMD_K8 + default 0x8000 if CPU_VIA_C7 help This option sets the size of the area used for CAR. @@ -175,6 +186,7 @@ default 0x1000 if CPU_I586 default 0x1000 if CPU_AMD_GEODELX default 0x2000 if CPU_AMD_K8 + default 0x1000 if CPU_VIA_C7 help This option sets the top of the memory area, in KiB, used for coreboot. Modified: coreboot-v3/arch/x86/Makefile =================================================================== --- coreboot-v3/arch/x86/Makefile 2008-10-10 20:37:02 UTC (rev 914) +++ coreboot-v3/arch/x86/Makefile 2008-10-11 00:07:36 UTC (rev 915) @@ -122,9 +122,13 @@ ifeq ($(CONFIG_CPU_AMD_K8),y) STAGE0_CAR_OBJ = amd/stage0.o STAGE0_ARCH_X86_SRC += amd/k8/stage1.c +else +ifeq ($(CONFIG_CPU_VIA_C7),y) + STAGE0_CAR_OBJ = via/stage0.o endif endif endif +endif ifeq ($(CONFIG_PAYLOAD_NO_PREPARSE_ELF), y) PARSEELF = Added: coreboot-v3/arch/x86/via/stage0.S =================================================================== --- coreboot-v3/arch/x86/via/stage0.S (rev 0) +++ coreboot-v3/arch/x86/via/stage0.S 2008-10-11 00:07:36 UTC (rev 915) @@ -0,0 +1,207 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com> + * Copyright (C) 2005 Eswar Nallusamy, LANL + * Copyright (C) 2005 Tyan + * (Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan) + * Copyright (C) 2007 coresystems GmbH + * (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH) + * Copyright (C) 2007,2008 Carl-Daniel Hailfinger + * Copyright (C) 2008 VIA Technologies, Inc. + * (Written by Jason Zhao <jasonzhao(a)viatech.com.cn> for VIA) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Init code - Switch CPU to protected mode and enable Cache-as-Ram (CAR). */ + +#include <macros.h> + +#define ROM_CODE_SEG 0x08 +#define ROM_DATA_SEG 0x10 + +#define CACHE_RAM_CODE_SEG 0x18 +#define CACHE_RAM_DATA_SEG 0x20 + + .align 4 + .globl protected_stage0 +protected_stage0: + /* This code was used by v2. TODO. */ + lgdt %cs:gdtptr + ljmp $ROM_CODE_SEG, $__protected_stage0 + +.globl __protected_stage0 +__protected_stage0: + /* Save the BIST result. */ + movl %eax, %ebp + + port80_post(0x01) + + movw $ROM_DATA_SEG, %ax + movw %ax, %ds + movw %ax, %es + movw %ax, %ss + movw %ax, %fs + movw %ax, %gs + + /* Restore the BIST value to %eax. */ + movl %ebp, %eax + +.align 4 + +#define CacheSize CONFIG_CARSIZE +#define CacheBase CONFIG_CARBASE + +#define ASSEMBLY +#include <mtrr.h> + + /* Save the BIST result */ + movl %eax, %ebp + +CacheAsRam: + + /* disable cache */ + movl %cr0, %eax + orl $(0x1<<30),%eax + movl %eax,%cr0 + invd + + /* Set the default memory type and enable fixed and variable MTRRs */ + movl $MTRRdefType_MSR, %ecx + xorl %edx, %edx + /* Enable Variable and Fixed MTRRs */ + movl $0x00000c00, %eax + wrmsr + + /* Clear all MTRRs */ + xorl %edx, %edx + movl $fixed_mtrr_msr, %esi + +clear_fixed_var_mtrr: + lodsl (%esi), %eax + testl %eax, %eax + jz clear_fixed_var_mtrr_out + + movl %eax, %ecx + xorl %eax, %eax + wrmsr + + jmp clear_fixed_var_mtrr +clear_fixed_var_mtrr_out: + /* MTRRPhysBase */ + movl $0x200, %ecx + xorl %edx, %edx + movl $(CacheBase|MTRR_TYPE_WRBACK),%eax + wrmsr + + /* MTRRPhysMask */ + movl $0x201, %ecx + /* This assumes we never access addresses above 2^36 in CAR. */ + movl $0x0000000f,%edx + movl $(~(CacheSize-1)|0x800),%eax + wrmsr + +#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) + /* enable write base caching so we can do execute in place + * on the flash rom. + */ + /* MTRRPhysBase */ + movl $0x202, %ecx + xorl %edx, %edx + movl $(XIP_ROM_BASE|MTRR_TYPE_WRBACK),%eax + wrmsr + + /* MTRRPhysMask */ + movl $0x203, %ecx + movl $0x0000000f,%edx + movl $(~(XIP_ROM_SIZE - 1) | 0x800), %eax + wrmsr +#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */ + + movl $MTRRdefType_MSR, %ecx + xorl %edx, %edx + /* Enable Variable and Fixed MTRRs */ + movl $0x00000800, %eax + wrmsr + + /* enable cache */ + movl %cr0, %eax + andl $0x9fffffff,%eax + movl %eax, %cr0 + + /* Read the range with lodsl */ + movl $CacheBase, %esi + cld + movl $(CacheSize >> 2), %ecx + rep lodsl + + /* Clear the range */ + movl $CacheBase, %edi + movl $(CacheSize >> 2), %ecx + xorl %eax, %eax + rep stosl + +#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) + /* Read the XIP area */ + movl XIP_ROM_BASE, %esi + movl $(XIP_ROM_SIZE>>2), %ecx + rep lodsl +#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */ + + /* The key point of this CAR code is C7 cache does not turn into + * "no fill" mode, which is not compatible with general CAR code. + */ + + /* set up the stack pointer */ + movl $(CacheBase + CacheSize - 4), %eax + movl %eax, %esp + + /* Load a different set of data segments */ + movw $CACHE_RAM_DATA_SEG, %ax + movw %ax, %ds + movw %ax, %es + movw %ax, %ss + +lout: + /* Store zero for the pointer to the global variables. */ + pushl $0 + + /* Restore the BIST result. */ + movl %ebp, %eax + + /* We need to set ebp? No need. */ + movl %esp, %ebp + + /* Second parameter: init_detected */ + /* Store zero for the unused init_detected parameter. */ + pushl $0 + /* First parameter: bist */ + pushl %eax + call stage1_main + /* We will not go back. */ + +fixed_mtrr_msr: + .long 0x250, 0x258, 0x259 + .long 0x268, 0x269, 0x26A + .long 0x26B, 0x26C, 0x26D + .long 0x26E, 0x26F +var_mtrr_msr: + .long 0x200, 0x201, 0x202, 0x203 + .long 0x204, 0x205, 0x206, 0x207 + .long 0x208, 0x209, 0x20A, 0x20B + .long 0x20C, 0x20D, 0x20E, 0x20F + .long 0x000 /* NULL, end of table */ + +#include "../stage0_common.S"

1 0

New license for the logo
by Peter Stuge 10 Oct '08

10 Oct '08

Hello, when the logo was announced this summer it came with a rather strict license that made it difficult-to-impossible for many to use. Everyone agreed that this was bad, and we've finally changed the license to something that will hopefully be easier to work with. The license is heavily inspired by the Debian Open Use Logo License but since we only have one logo, ours is named coreboot Logo License. We also include some clarifications with explicitly allowed (and encouraged) use of the logo. The Logo page is linked to on the wiki front page under the "About" heading, and here's the address: http://www.coreboot.org/Logo //Peter

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coreboot October 2008