coreboot October 2008

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r928 - in coreboot-v3/southbridge: . via via/vt8237
by svn＠coreboot.org 14 Oct '08

14 Oct '08

Author: cozzie Date: 2008-10-14 20:26:09 +0200 (Tue, 14 Oct 2008) New Revision: 928 Added: coreboot-v3/southbridge/via/ coreboot-v3/southbridge/via/vt8237/ coreboot-v3/southbridge/via/vt8237/Makefile coreboot-v3/southbridge/via/vt8237/stage1.c coreboot-v3/southbridge/via/vt8237/vt8237.h Log: Add stage1 support for vt8237[RS] to v3. Signed-off-by: Corey Osgood <corey.osgood(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Added: coreboot-v3/southbridge/via/vt8237/Makefile =================================================================== --- coreboot-v3/southbridge/via/vt8237/Makefile (rev 0) +++ coreboot-v3/southbridge/via/vt8237/Makefile 2008-10-14 18:26:09 UTC (rev 928) @@ -0,0 +1,25 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 Corey Osgood <corey.osgood(a)gmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +ifeq ($(CONFIG_SOUTHBRIDGE_VIA_VT8237),y) + +STAGE2_CHIPSET_SRC += + +endif Added: coreboot-v3/southbridge/via/vt8237/stage1.c =================================================================== --- coreboot-v3/southbridge/via/vt8237/stage1.c (rev 0) +++ coreboot-v3/southbridge/via/vt8237/stage1.c 2008-10-14 18:26:09 UTC (rev 928) @@ -0,0 +1,318 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 Corey Osgood <corey.osgood(a)gmail.com> + * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <lib.h> +#include <console.h> +#include <device/pci.h> +#include <io.h> +#include <device/pci_ids.h> +#include <spd.h> +#include "vt8237.h" + +/* TODO List: + * * Merge the rest of the functions from v2, except smbus_fixup which doesn't + * seem to be necessary any more (?) + * * Clean up vt8237_early_network_init. + * Comments in code indicate that it's broken? + * * Figure out if the smbus actually needs to be reset after every transaction. + */ + +/** + * Print an error, should it occur. If no error, just exit. + * + * @param host_status The data returned on the host status register after + * a transaction is processed. + * @param loops The number of times a transaction was attempted. + */ +static void smbus_print_error(u8 host_status, int loops) +{ + /* Check if there actually was an error. */ + if ((host_status == 0x00 || host_status == 0x40 || + host_status == 0x42) && (loops < SMBUS_TIMEOUT)) + { + printk(BIOS_SPEW, "SMBus Ready/Completed Successfully\n"); + return; + } + if (loops >= SMBUS_TIMEOUT) + printk(BIOS_ERR, "SMBus Timed out\n"); + if (host_status & (1 << 4)) + printk(BIOS_ERR, "Interrupt/SMI# was Failed Bus Transaction\n"); + if (host_status & (1 << 3)) + printk(BIOS_ERR, "Bus error\n"); + if (host_status & (1 << 2)) + printk(BIOS_ERR, "Device error\n"); + if (host_status & (1 << 1)) + printk(BIOS_SPEW, "Interrupt/SMI# completed successfully\n"); + if (host_status & (1 << 0)) + printk(BIOS_ERR, "Host busy\n"); +} + +/** + * Reset and take ownership of the SMBus. + */ +static void smbus_reset(u16 smbus_io_base) +{ + outb(HOST_RESET, smbus_io_base + SMBHSTSTAT); + + /* Datasheet says we have to read it to take ownership of SMBus. */ + smbus_print_error(inb(smbus_io_base + SMBHSTSTAT), 0); +} + +/** + * Wait for the SMBus to become ready to process the next transaction. + */ +static void smbus_wait_until_ready(u16 smbus_io_base) +{ + int loops; + + printk(BIOS_SPEW, "Waiting until SMBus ready\n"); + + loops = 0; + while ((inb(smbus_io_base + SMBHSTSTAT) & 1) == 1 && loops <= SMBUS_TIMEOUT) + ++loops; + + smbus_print_error(inb(smbus_io_base + SMBHSTSTAT), loops); +} + +/** + * Read a byte from the SMBus. + * + * @param dimm The address location of the DIMM on the SMBus. + * @param offset The offset the data is located at. + */ +u8 smbus_read_byte(u16 dimm, u8 offset, u16 smbus_io_base) +{ + u8 val; + + printk(BIOS_SPEW, "SMBus Read from DIMM %d at address 0x%x\n", + (int)dimm, offset); + + smbus_reset(smbus_io_base); + + /* Clear host data port. */ + outb(0x00, smbus_io_base + SMBHSTDAT0); + /* Doesn't seem to be necessary...*/ + /* udelay(1); */ + smbus_wait_until_ready(smbus_io_base); + + /* With this, addresses are 0x50, 0x51, etc. Without it, + * addresses would be 0xa1, 0xa3, etc */ + dimm = (dimm << 1) | 1; + + outb(dimm, smbus_io_base + SMBXMITADD); + outb(offset, smbus_io_base + SMBHSTCMD); + + /* Start transaction, byte data read. */ + outb(0x48, smbus_io_base + SMBHSTCTL); + /* udelay(1); */ + smbus_wait_until_ready(smbus_io_base); + + val = inb(smbus_io_base + SMBHSTDAT0); + printk(BIOS_SPEW, "Read: 0x%x\n", val); + + /* TODO: Is this necessary? */ + smbus_reset(smbus_io_base); + + return val; +} + +/** + * Enable the smbus on vt8237-based systems + * + * @param smbus_io_base: The SMBus I/O base, usually 0x400 + */ +void enable_smbus(u16 smbus_io_base) +{ + u32 dev; + + /* Power management controller */ + pci_conf1_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC, + &dev); + + if (!dev) { + /* Power management controller */ + pci_conf1_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237S_LPC, &dev); + if (!dev) + { + printk(BIOS_ERR, "Power management controller not " + "found! Using hardcoded default.\n"); + dev = PCI_BDF(0, 17, 0); + } else { + printk(BIOS_DEBUG, "VT8237S Power management " + "controller found at 0x%x\n", dev); + } + } else { + printk(BIOS_DEBUG, "VT8237R Power management controller found " + "at 0x%x\n", dev); + } + + /* 7 = SMBus Clock from RTC 32.768KHz + * 5 = Internal PLL reset from susp + */ + pci_conf1_write_config8(dev, VT8237R_POWER_WELL, 0xa0); + + /* Enable SMBus. */ + pci_conf1_write_config16(dev, VT8237R_SMBUS_IO_BASE_REG, + smbus_io_base | 0x1); + + /* SMBus Host Configuration, enable. */ + pci_conf1_write_config8(dev, VT8237R_SMBUS_HOST_CONF, 0x01); + + /* Make it work for I/O. */ + pci_conf1_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); + + /* reset smbus */ + smbus_reset(smbus_io_base); + + /* Reset the internal pointer. */ + inb(smbus_io_base + SMBHSTCTL); +} + +/* TODO: + * Magic numbers -> #defines + * fix? + * clean up + */ + +/* offset 0x58 + * 31:20 reserved + * 19:16 4 bit position in shadow EEPROM + * 15:0 data to write + * + * offset 0x5c + * 31:28 reserved + * 27 ERDBG - enable read from 0x5c + * 26 reserved + * 25 SEELD + * 24 SEEPR - write 1 when done updating, wait until SEELD is set to 1, sticky + * cleared by reset, if it is 1 writing is disabled + * 19:16 4 bit position in shadow EEPROM + * 15:0 data from shadow EEPROM + * + * after PCIRESET SEELD and SEEPR must be 1 and 1 +*/ + +/* 1 = needs PCI reset, 0 don't reset, network initialized */ + +/* fixme maybe close the debug register after use? */ + +#define LAN_TIMEOUT 0x7FFFFFFF + +int vt8237_early_network_init(struct vt8237_network_rom *rom) { + struct vt8237_network_rom n; + int loops = 0; + u32 dev; + u32 tmp; + u8 status; + u16 *rom_write; + unsigned int checksum; + int i; + + /* Network adapter */ + pci_conf1_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237_LAN, + &dev); + + if (!dev) { + printk(BIOS_ERR, "Network is disabled, please enable\n"); + return 0; + } + + tmp = pci_conf1_read_config32(dev, 0x5c); + /* enable ERDBG */ + tmp |= 0x08000000; + pci_conf1_write_config32(dev, 0x5c, tmp); + + status = ((pci_conf1_read_config32(dev, 0x5c) >> 24) & 0x3); + + if (status == 3) { + /* network controller OK, EEPROM loaded */ + return 0; + } + + if (rom == NULL) { + printk(BIOS_ERR, "No configuration data specified, using default MAC!\n"); + n.mac_address[0] = 0x0; + n.mac_address[1] = 0x0; + n.mac_address[2] = 0xde; + n.mac_address[3] = 0xad; + n.mac_address[4] = 0xbe; + n.mac_address[5] = 0xef; + n.phy_addr = 0x1; + n.res1 = 0x0; + n.sub_sid = 0x102; + n.sub_vid = 0x1106; + n.pid = 0x3065; + n.vid = 0x1106; + n.pmcc = 0x1f; + n.data_sel = 0x10; + n.pmu_data_reg = 0x0; + n.aux_curr = 0x0; + n.reserved = 0x0; + n.min_gnt = 0x3; + n.max_lat = 0x8; + n.bcr0 = 0x9; + n.bcr1 = 0xe; + n.cfg_a = 0x3; + n.cfg_b = 0x0; + n.cfg_c = 0x40; + n.cfg_d = 0x82; + n.checksum = 0x0; + rom = &n; + } + + rom_write = (u16 *) rom; + checksum = 0; + /* write all data except checksum and second to last byte */ + tmp &= 0xff000000; /* leave reserved bits in */ + for (i = 0; i < 15; i++) { + pci_conf1_write_config32(dev, 0x58, tmp | (i << 16) | rom_write[i]); + /* lame code fixme */ + checksum += rom_write[i] & 0xff; + //checksum %= 256; + checksum += (rom_write[i] >> 8) & 0xff; + //checksum %= 256; + } + + checksum += (rom_write[15] & 0xff); + checksum = ~(checksum & 0xff); + tmp |= (((checksum & 0xff) << 8) | rom_write[15]); + + /* write last byte and checksum */ + pci_conf1_write_config32(dev, 0x58, (15 << 16) | tmp); + + tmp = pci_conf1_read_config32(dev, 0x5c); + pci_conf1_write_config32(dev, 0x5c, tmp | 0x01000000); /* toggle SEEPR */ + + /* Yes, this is a mess, but it's the easiest way to do it. */ + while ( (((pci_conf1_read_config32(dev, 0x5c) >> 25) & 1) == 0) + && (loops < LAN_TIMEOUT)) + ++loops; + + if (loops >= LAN_TIMEOUT) { + printk(BIOS_ERR, "Timout - LAN controller did not accept configuration\n"); + return 0; + } + + /* we are done, config will be used after PCIRST# */ + return 1; +} Added: coreboot-v3/southbridge/via/vt8237/vt8237.h =================================================================== --- coreboot-v3/southbridge/via/vt8237/vt8237.h (rev 0) +++ coreboot-v3/southbridge/via/vt8237/vt8237.h 2008-10-14 18:26:09 UTC (rev 928) @@ -0,0 +1,90 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License v2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SOUTHBRIDGE_VIA_VT8237_VT8237_H +#define SOUTHBRIDGE_VIA_VT8237_VT8237_H + +#include <types.h> + +/* Static resources for the VT8237R southbridge */ + +#define VT8237R_APIC_ID 0x2 +#define VT8237R_ACPI_IO_BASE 0x500 +/* 0x0 disabled, 0x2 reserved, 0xf = IRQ15 */ +#define VT8237R_ACPI_IRQ 0x9 +#define VT8237S_SPI_MEM_BASE 0xfed02000ULL +#define VT8237R_HPET_ADDR 0xfed00000ULL +#define VT8237R_APIC_BASE 0xfec00000ULL + +/* IDE */ +#define IDE_CS 0x40 +#define IDE_CONF_I 0x41 +#define IDE_CONF_II 0x42 +#define IDE_CONF_FIFO 0x43 +#define IDE_MISC_I 0x44 +#define IDE_MISC_II 0x45 +#define IDE_UDMA 0x50 + +/* SMBus */ +#define VT8237R_POWER_WELL 0x94 +#define VT8237R_SMBUS_IO_BASE_REG 0xd0 +#define VT8237R_SMBUS_HOST_CONF 0xd2 + +#define SMBHSTSTAT 0x0 +#define SMBSLVSTAT 0x1 +#define SMBHSTCTL 0x2 +#define SMBHSTCMD 0x3 +#define SMBXMITADD 0x4 +#define SMBHSTDAT0 0x5 + +#define HOST_RESET 0xff +/* 1 in the 0 bit of SMBHSTADD states to READ. */ +#define READ_CMD 0x01 +#define SMBUS_TIMEOUT (100 * 1000 * 10) +#define I2C_TRANS_CMD 0x40 +#define CLOCK_SLAVE_ADDRESS 0x69 + +struct vt8237_network_rom { + u8 mac_address[6]; + u8 phy_addr; + u8 res1; + u16 sub_sid; + u16 sub_vid; + u16 pid; + u16 vid; + u8 pmcc; + u8 data_sel; + u8 pmu_data_reg; + u8 aux_curr; + u16 reserved; + u8 min_gnt; + u8 max_lat; + u8 bcr0; + u8 bcr1; + u8 cfg_a; + u8 cfg_b; + u8 cfg_c; + u8 cfg_d; + u8 checksum; +} __attribute__ ((packed)); + +void enable_smbus(u16); +u8 smbus_read_byte(u16, u8, u16); + +#endif

1 0

AMD K8 define fix
by Myles Watson 14 Oct '08

14 Oct '08

This patch fixes an ifdef that should have been an ifndef. It also changes white space so that it was obvious what the difference from v2 to v3 was. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

3 4

r3658 - trunk/util/superiotool
by svn＠coreboot.org 14 Oct '08

14 Oct '08

Author: uwe Date: 2008-10-14 18:34:38 +0200 (Tue, 14 Oct 2008) New Revision: 3658 Modified: trunk/util/superiotool/ali.c trunk/util/superiotool/fintek.c trunk/util/superiotool/ite.c trunk/util/superiotool/smsc.c trunk/util/superiotool/winbond.c Log: Drop global register 0x07 for all Super I/Os (trivial). This is useless, as it changes with each access; it doesn't convey any useful information at all. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/util/superiotool/ali.c =================================================================== --- trunk/util/superiotool/ali.c 2008-10-14 16:28:50 UTC (rev 3657) +++ trunk/util/superiotool/ali.c 2008-10-14 16:34:38 UTC (rev 3658) @@ -29,8 +29,8 @@ /* TODO: M5113 doesn't seem to have ID registers? */ {0x5315, "M1535/M1535D/M1535+/M1535D+", { {NOLDN, NULL, - {0x07,0x1f,0x20,0x21,0x22,0x23,0x2c,0x2d,0x2e,EOT}, - {NANA,NANA,0x53,0x15,0x00,0x00,RSVD,RSVD,RSVD,EOT}}, + {0x1f,0x20,0x21,0x22,0x23,0x2c,0x2d,0x2e,EOT}, + {NANA,0x53,0x15,0x00,0x00,RSVD,RSVD,RSVD,EOT}}, {0x0, "Floppy", {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf4,EOT}, {0x00,0x03,0xf0,0x06,0x02,0x08,0x00,0xff,0x00,EOT}}, Modified: trunk/util/superiotool/fintek.c =================================================================== --- trunk/util/superiotool/fintek.c 2008-10-14 16:28:50 UTC (rev 3657) +++ trunk/util/superiotool/fintek.c 2008-10-14 16:34:38 UTC (rev 3658) @@ -81,10 +81,8 @@ {0x0604, "F71805F/FG", { /* We assume reserved bits are read as 0. */ {NOLDN, NULL, - {0x07,0x20,0x21,0x23,0x24,0x25,0x26,0x27,0x28, - 0x29,EOT}, - {NANA,0x04,0x06,0x19,0x34,0x00,0x00,0x3f,0x08, - 0x00,EOT}}, + {0x20,0x21,0x23,0x24,0x25,0x26,0x27,0x28,0x29,EOT}, + {0x04,0x06,0x19,0x34,0x00,0x00,0x3f,0x08,0x00,EOT}}, {0x0, "Floppy", {0x30,0x60,0x61,0x70,0x74,0xf0,0xf2,0xf4,EOT}, {0x01,0x03,0xf0,0x06,0x02,0x0e,0x03,0x00,EOT}}, Modified: trunk/util/superiotool/ite.c =================================================================== --- trunk/util/superiotool/ite.c 2008-10-14 16:28:50 UTC (rev 3657) +++ trunk/util/superiotool/ite.c 2008-10-14 16:34:38 UTC (rev 3658) @@ -30,10 +30,10 @@ {0x8661, "IT8661F", { /* TODO: Needs different init sequence. */ {NOLDN, NULL, - {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x20,0x21, - 0x22,0x23,0x24,EOT}, - {NANA,NANA,NANA,NANA,NANA,NANA,0x00,NANA,0x86,0x61, - 0x00,0x00,0x00,EOT}}, + {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x20,0x21,0x22, + 0x23,0x24,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,0x00,0x86,0x61,0x00, + 0x00,0x00,EOT}}, {0x0, "Floppy", {0x30,0x31,0x60,0x61,0x70,0x71,0x74,0xf0,EOT}, {0x00,0x00,0x03,0xf0,0x06,0x02,0x02,0x00,EOT}}, @@ -65,8 +65,8 @@ {EOT}}}, {0x8705, "IT8705F/AF / IT8700F", { {NOLDN, NULL, - {0x07,0x20,0x21,0x22,0x23,0x24,EOT}, - {NANA,0x87,0x05,0x00,0x00,NANA,EOT}}, + {0x20,0x21,0x22,0x23,0x24,EOT}, + {0x87,0x05,0x00,0x00,NANA,EOT}}, {0x0, "Floppy", {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,EOT}, {0x00,0x03,0xf0,0x06,0x02,0x00,0x00,EOT}}, @@ -116,10 +116,10 @@ {EOT}}}, {0x8708, "IT8708F", { {NOLDN, NULL, - {0x07,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28, - 0x29,0x2a,0x2e,0x2f,EOT}, - {NANA,0x87,0x08,0x00,0x00,NANA,0x3f,0x00,0xff,0xff, - 0xff,0xff,0x00,0x00,EOT}}, + {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29, + 0x2a,0x2e,0x2f,EOT}, + {0x87,0x08,0x00,0x00,NANA,0x3f,0x00,0xff,0xff,0xff, + 0xff,0x00,0x00,EOT}}, {0x0, "Floppy", {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,EOT}, {0x00,0x03,0xf0,0x06,0x02,0x00,0x00,EOT}}, @@ -173,8 +173,8 @@ {EOT}}}, {0x8712, "IT8712F", { {NOLDN, NULL, - {0x07,0x20,0x21,0x22,0x23,0x24,0x2b,EOT}, - {NANA,0x87,0x12,0x08,0x00,0x00,0x00,EOT}}, + {0x20,0x21,0x22,0x23,0x24,0x2b,EOT}, + {0x87,0x12,0x08,0x00,0x00,0x00,EOT}}, {0x0, "Floppy", {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,EOT}, {0x00,0x03,0xf0,0x06,0x02,0x00,0x00,EOT}}, @@ -224,8 +224,8 @@ {EOT}}}, {0x8716, "IT8716F", { {NOLDN, NULL, - {0x07,0x20,0x21,0x22,0x23,0x24,0x2b,EOT}, - {NANA,0x87,0x16,0x01,0x00,0x00,0x00,EOT}}, + {0x20,0x21,0x22,0x23,0x24,0x2b,EOT}, + {0x87,0x16,0x01,0x00,0x00,0x00,EOT}}, {0x0, "Floppy", {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,EOT}, {0x00,0x03,0xf0,0x06,0x02,0x00,0x00,EOT}}, @@ -274,8 +274,8 @@ {EOT}}}, {0x8718, "IT8718F", { {NOLDN, NULL, - {0x07,0x20,0x21,0x22,0x23,0x24,0x2b,EOT}, - {NANA,0x87,0x18,0x01,0x00,0x00,0x00,EOT}}, + {0x20,0x21,0x22,0x23,0x24,0x2b,EOT}, + {0x87,0x18,0x01,0x00,0x00,0x00,EOT}}, {0x0, "Floppy", {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,EOT}, {0x00,0x03,0xf0,0x06,0x02,0x00,0x00,EOT}}, Modified: trunk/util/superiotool/smsc.c =================================================================== --- trunk/util/superiotool/smsc.c 2008-10-14 16:28:50 UTC (rev 3657) +++ trunk/util/superiotool/smsc.c 2008-10-14 16:34:38 UTC (rev 3658) @@ -34,10 +34,10 @@ {EOT}}}, {0x0a, "FDC37N971", { {NOLDN, NULL, - {0x02,0x07,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27, - 0x28,0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, - {0x00,0x00,0x0a,0x00,0x00,0x00,0x04,0x04,NANA,NANA, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x02,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28, + 0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, + {0x00,0x0a,0x00,0x00,0x00,0x04,0x04,NANA,NANA,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, {0x0, "Floppy", {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf3,0xf4, 0xf5,EOT}, @@ -72,10 +72,10 @@ {EOT}}}, {0x0b, "FDC37N972", { {NOLDN, NULL, - {0x02,0x07,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27, - 0x28,0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, - {0x00,0x00,0x0b,0x00,0x00,0x00,0x04,0x04,NANA,NANA, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x02,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28, + 0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, + {0x00,0x0b,0x00,0x00,0x00,0x04,0x04,NANA,NANA,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, {0x0, "Floppy", {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf3,0xf4, 0xf5,EOT}, @@ -151,10 +151,10 @@ {EOT}}}, {0x09, "FDC37N958FR", { /* Found in e.g. Dell Latitude CPi A366XT. */ {NOLDN, NULL, - {0x03,0x07,0x20,0x21,0x22,0x23,0x24,0x26,0x27,0x28, - 0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, - {0x03,NANA,0x44,0x00,0x00,0x00,0x04,MISC,MISC,0x00, - NANA,NANA,NANA,NANA,NANA,EOT}}, + {0x03,0x20,0x21,0x22,0x23,0x24,0x26,0x27,0x28,0x2b, + 0x2c,0x2d,0x2e,0x2f,EOT}, + {0x03,0x44,0x00,0x00,0x00,0x04,MISC,MISC,0x00,NANA, + NANA,NANA,NANA,NANA,EOT}}, {0x0, "Floppy", {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf4,0xf5, EOT}, @@ -196,10 +196,10 @@ {EOT}}}, {0x44, "FDC37B78x", { {NOLDN, NULL, - {0x03,0x07,0x20,0x21,0x22,0x23,0x24,0x26,0x27,0x28, - 0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, - {0x03,NANA,0x44,0x00,0x00,0x00,0x04,MISC,MISC,0x00, - NANA,NANA,NANA,NANA,NANA,EOT}}, + {0x03,0x20,0x21,0x22,0x23,0x24,0x26,0x27,0x28,0x2b, + 0x2c,0x2d,0x2e,0x2f,EOT}, + {0x03,0x44,0x00,0x00,0x00,0x04,MISC,MISC,0x00,NANA, + NANA,NANA,NANA,NANA,EOT}}, {0x0, "Floppy", {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf4,0xf5, EOT}, @@ -241,10 +241,10 @@ {EOT}}}, {0x4c, "FDC37B72x", { {NOLDN, NULL, - {0x03,0x07,0x20,0x21,0x22,0x23,0x24,0x26,0x27,0x28, - 0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, - {0x03,NANA,0x4c,0x00,0x00,0x00,0x04,MISC,MISC,0x00, - NANA,NANA,NANA,NANA,NANA,EOT}}, + {0x03,0x20,0x21,0x22,0x23,0x24,0x26,0x27,0x28,0x2b, + 0x2c,0x2d,0x2e,0x2f,EOT}, + {0x03,0x4c,0x00,0x00,0x00,0x04,MISC,MISC,0x00,NANA, + NANA,NANA,NANA,NANA,EOT}}, {0x0, "Floppy", {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf4,0xf5, EOT}, @@ -279,10 +279,10 @@ {EOT}}}, {0x4d, "FDC37M81x", { {NOLDN, NULL, - {0x03,0x07,0x20,0x21,0x22,0x23,0x24,0x26,0x27,0x2b, - 0x2c,0x2d,0x2e,0x2f,EOT}, - {0x03,0x00,0x4d,NANA,0x00,0x00,0x04,MISC,MISC,NANA, - NANA,NANA,NANA,NANA,EOT}}, + {0x03,0x20,0x21,0x22,0x23,0x24,0x26,0x27,0x2b,0x2c, + 0x2d,0x2e,0x2f,EOT}, + {0x03,0x4d,NANA,0x00,0x00,0x04,MISC,MISC,NANA,NANA, + NANA,NANA,NANA,EOT}}, {0x0, "Floppy", {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf4, 0xf5,EOT}, @@ -354,10 +354,10 @@ {EOT}}}, {0x59, "LPC47M10x/112/13x", { {NOLDN, NULL, - {0x03,0x07,0x20,0x21,0x22,0x23,0x24,0x26,0x27,0x28, - 0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, - {RSVD,0x00,0x59,NANA,0x00,0x00,0x44,MISC,MISC,RSVD, - NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {0x03,0x20,0x21,0x22,0x23,0x24,0x26,0x27,0x28,0x2a, + 0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, + {RSVD,0x59,NANA,0x00,0x00,0x44,MISC,MISC,RSVD,NANA, + NANA,NANA,NANA,NANA,NANA,EOT}}, {0x0, "Floppy", {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf4, 0xf5,EOT}, @@ -393,10 +393,10 @@ {EOT}}}, {0x60, "LPC47M15x/192/997", { {NOLDN, NULL, - {0x03,0x07,0x20,0x21,0x22,0x23,0x24,0x26,0x27,0x28, - 0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, - {RSVD,0x00,0x60,NANA,0x00,0x00,0x44,MISC,MISC,RSVD, - NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {0x03,0x20,0x21,0x22,0x23,0x24,0x26,0x27,0x28,0x2a, + 0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, + {RSVD,0x60,NANA,0x00,0x00,0x44,MISC,MISC,RSVD,NANA, + NANA,NANA,NANA,NANA,NANA,EOT}}, {0x0, "Floppy", {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf4,0xf5, EOT}, @@ -443,10 +443,10 @@ {EOT}}}, {0x77, "A8000", { /* ASUS A8000, a rebranded DME1737(?) */ {NOLDN, NULL, - {0x03,0x07,0x20,0x21,0x22,0x23,0x24,0x26,0x27,0x28, - 0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, - {RSVD,0x00,0x77,NANA,0x00,RSVD,0x44,MISC,MISC,RSVD, - NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {0x03,0x20,0x21,0x22,0x23,0x24,0x26,0x27,0x28,0x2a, + 0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, + {RSVD,0x77,NANA,0x00,RSVD,0x44,MISC,MISC,RSVD,NANA, + NANA,NANA,NANA,NANA,NANA,EOT}}, {0x0, "Floppy", {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf4, 0xf5,EOT}, @@ -470,10 +470,10 @@ {EOT}}}, {0x78, "DME1737", { {NOLDN, NULL, - {0x03,0x07,0x20,0x21,0x22,0x23,0x24,0x26,0x27,0x28, - 0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, - {RSVD,0x00,0x77,NANA,0x00,RSVD,0x44,MISC,MISC,RSVD, - NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {0x03,0x20,0x21,0x22,0x23,0x24,0x26,0x27,0x28,0x2a, + 0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, + {RSVD,0x77,NANA,0x00,RSVD,0x44,MISC,MISC,RSVD,NANA, + NANA,NANA,NANA,NANA,NANA,EOT}}, {0x0, "Floppy", {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf4, 0xf5,EOT}, Modified: trunk/util/superiotool/winbond.c =================================================================== --- trunk/util/superiotool/winbond.c 2008-10-14 16:28:50 UTC (rev 3657) +++ trunk/util/superiotool/winbond.c 2008-10-14 16:34:38 UTC (rev 3658) @@ -45,9 +45,9 @@ {EOT}}}, {0x601, "W83697HF/F/HG", { /* No G version? */ {NOLDN, NULL, - {0x07,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x28,0x29, + {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x28,0x29, 0x2a,EOT}, - {NANA,0x60,NANA,0xff,0x00,0x00,0x00,0x00,0x00,0x00, + {0x60,NANA,0xff,0x00,0x00,0x00,0x00,0x00,0x00, MISC,EOT}}, /* Some register defaults depend on the value of PNPCSV. */ {0x0, "Floppy", @@ -259,10 +259,10 @@ /* ID only */ {0x52, "W83627HF/F/HG/G", { {NOLDN, NULL, - {0x02,0x07,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x28, - 0x29,0x2a,0x2b,0x2c,0x2e,0x2f,EOT}, - {0x00,NANA,0x52,NANA,0xff,0x00,MISC,0x00,0x00,0x00, - 0x00,0x7c,0xc0,0x00,0x00,0x00,EOT}}, + {0x02,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x28,0x29, + 0x2a,0x2b,0x2c,0x2e,0x2f,EOT}, + {0x00,0x52,NANA,0xff,0x00,MISC,0x00,0x00,0x00,0x00, + 0x7c,0xc0,0x00,0x00,0x00,EOT}}, {0x0, "Floppy", {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf4, 0xf5,EOT},

1 0

r927 - coreboot-v3/northbridge/amd/k8
by svn＠coreboot.org 14 Oct '08

14 Oct '08

Author: myles Date: 2008-10-14 18:31:57 +0200 (Tue, 14 Oct 2008) New Revision: 927 Modified: coreboot-v3/northbridge/amd/k8/domain.c Log: Change an ifdef to an ifndef so it matches the logic of v2. Clean up some white space. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Peter Stuge <peter(a)stuge.net> Modified: coreboot-v3/northbridge/amd/k8/domain.c =================================================================== --- coreboot-v3/northbridge/amd/k8/domain.c 2008-10-14 12:27:23 UTC (rev 926) +++ coreboot-v3/northbridge/amd/k8/domain.c 2008-10-14 16:31:57 UTC (rev 927) @@ -1,5 +1,5 @@ /* - * K8 northbridge + * K8 northbridge * This file is part of the coreboot project. * Copyright (C) 2004-2005 Linux Networx * (Written by Eric Biederman <ebiederman(a)lnxi.com> and Jason Schildt for Linux Networx) @@ -57,7 +57,7 @@ void f1_write_config32(unsigned int reg, u32 value); unsigned int amdk8_nodeid(struct device * dev); -static void k8_ram_resource(struct device * dev, unsigned long index, +static void k8_ram_resource(struct device * dev, unsigned long index, unsigned long basek, unsigned long sizek) { struct resource *resource; @@ -87,7 +87,7 @@ { struct resource *min; u32 tolm; - min = 0; + min = NULL; search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min); tolm = 0xffffffffUL; if (min && tolm > min->base) { @@ -125,41 +125,41 @@ } } } -#ifdef CONFIG_PCI_64BIT_PREF_MEM +#ifndef CONFIG_PCI_64BIT_PREF_MEM /* Initialize the system wide io space constraints */ resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); resource->base = 0x400; resource->limit = 0xffffUL; resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + /* Initialize the system wide memory resources constraints */ + resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); + resource->limit = 0xfcffffffffULL; + resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; #else - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, 0); - resource->base = 0x400; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO; - compute_allocate_resource(&dev->link[0], resource, - IORESOURCE_IO, IORESOURCE_IO); + /* Initialize the system wide io space constraints */ + resource = new_resource(dev, 0); + resource->base = 0x400; + resource->limit = 0xffffUL; + resource->flags = IORESOURCE_IO; + compute_allocate_resource(&dev->link[0], resource, + IORESOURCE_IO, IORESOURCE_IO); - /* Initialize the system wide prefetchable memory resources constraints */ - resource = new_resource(dev, 1); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - compute_allocate_resource(&dev->link[0], resource, - IORESOURCE_MEM | IORESOURCE_PREFETCH, - IORESOURCE_MEM | IORESOURCE_PREFETCH); + /* Initialize the system wide prefetchable memory resources constraints */ + resource = new_resource(dev, 1); + resource->limit = 0xfcffffffffULL; + resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; + compute_allocate_resource(&dev->link[0], resource, + IORESOURCE_MEM | IORESOURCE_PREFETCH, + IORESOURCE_MEM | IORESOURCE_PREFETCH); - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, 2); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM; - compute_allocate_resource(&dev->link[0], resource, - IORESOURCE_MEM | IORESOURCE_PREFETCH, - IORESOURCE_MEM); + /* Initialize the system wide memory resources constraints */ + resource = new_resource(dev, 2); + resource->limit = 0xfcffffffffULL; + resource->flags = IORESOURCE_MEM; + compute_allocate_resource(&dev->link[0], resource, + IORESOURCE_MEM | IORESOURCE_PREFETCH, + IORESOURCE_MEM); #endif printk(BIOS_DEBUG, "k8_pci_domain_read_resources done\n"); } @@ -185,68 +185,68 @@ #endif #if 0 - /* Place the IO devices somewhere safe */ - io = find_resource(dev, 0); - io->base = DEVICE_IO_START; + /* Place the IO devices somewhere safe */ + io = find_resource(dev, 0); + io->base = DEVICE_IO_START; #endif #ifdef CONFIG_PCI_64BIT_PREF_MEM - /* Now reallocate the pci resources memory with the - * highest addresses I can manage. - */ - mem1 = find_resource(dev, 1); - mem2 = find_resource(dev, 2); + /* Now reallocate the pci resources memory with the + * highest addresses I can manage. + */ + mem1 = find_resource(dev, 1); + mem2 = find_resource(dev, 2); #if 1 - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); + printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", + mem1->base, mem1->limit, mem1->size, mem1->align); + printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", + mem2->base, mem2->limit, mem2->size, mem2->align); #endif - /* See if both resources have roughly the same limits */ - if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || - ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) - { - /* If so place the one with the most stringent alignment first - */ - if (mem2->align > mem1->align) { - struct resource *tmp; - tmp = mem1; - mem1 = mem2; - mem2 = tmp; - } - /* Now place the memory as high up as it will go */ - mem2->base = resource_max(mem2); - mem1->limit = mem2->base - 1; - mem1->base = resource_max(mem1); - } - else { - /* Place the resources as high up as they will go */ - mem2->base = resource_max(mem2); - mem1->base = resource_max(mem1); - } + /* See if both resources have roughly the same limits */ + if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || + ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) + { + /* If so place the one with the most stringent alignment first + */ + if (mem2->align > mem1->align) { + struct resource *tmp; + tmp = mem1; + mem1 = mem2; + mem2 = tmp; + } + /* Now place the memory as high up as it will go */ + mem2->base = resource_max(mem2); + mem1->limit = mem2->base - 1; + mem1->base = resource_max(mem1); + } + else { + /* Place the resources as high up as they will go */ + mem2->base = resource_max(mem2); + mem1->base = resource_max(mem1); + } #if 1 - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); + printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", + mem1->base, mem1->limit, mem1->size, mem1->align); + printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", + mem2->base, mem2->limit, mem2->size, mem2->align); #endif - last = &dev->resource[dev->resources]; - for(resource = &dev->resource[0]; resource < last; resource++) - { + last = &dev->resource[dev->resources]; + for(resource = &dev->resource[0]; resource < last; resource++) + { #if 1 - resource->flags |= IORESOURCE_ASSIGNED; - resource->flags &= ~IORESOURCE_STORED; + resource->flags |= IORESOURCE_ASSIGNED; + resource->flags &= ~IORESOURCE_STORED; #endif - compute_allocate_resource(&dev->link[0], resource, - BRIDGE_IO_MASK, resource->flags & BRIDGE_IO_MASK); + compute_allocate_resource(&dev->link[0], resource, + BRIDGE_IO_MASK, resource->flags & BRIDGE_IO_MASK); - resource->flags |= IORESOURCE_STORED; - report_resource_stored(dev, resource, ""); + resource->flags |= IORESOURCE_STORED; + report_resource_stored(dev, resource, ""); - } + } #endif @@ -264,47 +264,47 @@ #endif #if CONFIG_HW_MEM_HOLE_SIZEK != 0 - /* if the hw mem hole is already set in raminit stage, here we will compare mmio_basek and hole_basek - * if mmio_basek is bigger that hole_basek and will use hole_basek as mmio_basek and we don't need to reset hole. - * otherwise We reset the hole to the mmio_basek - */ + /* if the hw mem hole is already set in raminit stage, here we will compare mmio_basek and hole_basek + * if mmio_basek is bigger that hole_basek and will use hole_basek as mmio_basek and we don't need to reset hole. + * otherwise We reset the hole to the mmio_basek + */ mem_hole = get_hw_mem_hole_info(); - if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { //We will use hole_basek as mmio_basek, and we don't need to reset hole anymore - mmio_basek = mem_hole.hole_startk; + if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { //We will use hole_basek as mmio_basek, and we don't need to reset hole anymore + mmio_basek = mem_hole.hole_startk; reset_memhole = 0; - } - + } + //mmio_basek = 3*1024*1024; // for debug to meet boundary if(reset_memhole) { if(mem_hole.node_id!=-1) { // We need to select CONFIG_HW_MEM_HOLE_SIZEK for raminit, it can not make hole_startk to some basek too....! - // We need to reset our Mem Hole, because We want more big HOLE than we already set - //Before that We need to disable mem hole at first, becase memhole could already be set on i+1 instead - disable_hoist_memory(mem_hole.hole_startk, mem_hole.node_id); + // We need to reset our Mem Hole, because We want more big HOLE than we already set + //Before that We need to disable mem hole at first, becase memhole could already be set on i+1 instead + disable_hoist_memory(mem_hole.hole_startk, mem_hole.node_id); } #if HW_MEM_HOLE_SIZE_AUTO_INC == 1 //We need to double check if the mmio_basek is valid for hole setting, if it is equal to basek, we need to decrease it some - u32 basek_pri; - for (i = 0; i < 8; i++) { - u32 base; + u32 basek_pri; + for (i = 0; i < 8; i++) { + u32 base; u32 basek; - base = f1_read_config32(0x40 + (i << 3)); - if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { - continue; - } + base = f1_read_config32(0x40 + (i << 3)); + if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { + continue; + } basek = (base & 0xffff0000) >> 2; if(mmio_basek == basek) { - mmio_basek -= (basek - basek_pri)>>1; // increase mem hole size to make sure it is on middle of pri node - break; + mmio_basek -= (basek - basek_pri)>>1; // increase mem hole size to make sure it is on middle of pri node + break; } basek_pri = basek; - } - #endif - } + } + #endif + } #endif @@ -327,12 +327,12 @@ idx += 0x10; basek = (8*64)+(16*16); sizek = limitk - ((8*64)+(16*16)); - + } - - printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); //yhlu - + + printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); //yhlu + /* See if I need to split the region to accomodate pci memory space */ if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) { if (basek <= mmio_basek) { @@ -344,10 +344,10 @@ sizek -= pre_sizek; } #if CONFIG_HW_MEM_HOLE_SIZEK != 0 - if(reset_memhole) - sizek += hoist_memory(mmio_basek,i); + if(reset_memhole) + sizek += hoist_memory(mmio_basek,i); #endif - + basek = mmio_basek; } if ((basek + sizek) <= 4*1024*1024) { @@ -373,8 +373,8 @@ for(reg = 0xe0; reg <= 0xec; reg += 4) { f1_write_config32(reg, 0); } - max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0x18, 0), 0xff, max); - + max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0x18, 0), 0xff, max); + /* Tune the hypertransport transaction for best performance. * Including enabling relaxed ordering if it is safe. */ @@ -402,12 +402,12 @@ struct device_operations k8domain_ops = { .id = {.type = DEVICE_ID_APIC_CLUSTER, {.pci_domain = {.vendor = PCI_VENDOR_ID_AMD, - .device = 0x1100}}}, + .device = 0x1100}}}, .constructor = default_device_constructor, - .phase3_scan = k8_domain_scan_bus, + .phase3_scan = k8_domain_scan_bus, .phase4_read_resources = k8_pci_domain_read_resources, .phase4_set_resources = k8_pci_domain_set_resources, .phase5_enable_resources = enable_childrens_resources, .ops_pci = &pci_dev_ops_pci, - .ops_pci_bus = &pci_cf8_conf1, + .ops_pci_bus = &pci_cf8_conf1, };

1 0

[PATCH] superiotool: Add dump support for it8726f
by Josh 14 Oct '08

14 Oct '08

I used the it8718f dump code as a reference for how to do this. There was one value that I wasn't sure about. 0x72 Watch Dog Timer Configuration Register ldn idx def 0x7 0x72 0x20 it8718f superiotool code 0x7 0x72 001s0000h it8718f datasheet 0x7 0x72 001s0000h it8726f datasheet I wasn't really sure what the s in 001s0000h meant, and couldn't figure out why it would be 0x20, but i went with 0x20 because that's what's in the code. superiotool -d shows the value as 0x00 for me. Josh

2 1

r3657 - trunk/util/superiotool
by svn＠coreboot.org 14 Oct '08

14 Oct '08

Author: uwe Date: 2008-10-14 18:28:50 +0200 (Tue, 14 Oct 2008) New Revision: 3657 Modified: trunk/util/superiotool/README trunk/util/superiotool/ite.c Log: Add dump support to ITE IT8726F, and add comments and a missing GPIO register to ITE IT8718F. Signed-off-by: Josh Profitt <zorn169(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/util/superiotool/README =================================================================== --- trunk/util/superiotool/README 2008-10-13 23:18:56 UTC (rev 3656) +++ trunk/util/superiotool/README 2008-10-14 16:28:50 UTC (rev 3657) @@ -87,6 +87,7 @@ David Hendricks <david.hendricks(a)gmail.com> Frieder Ferlemann <Frieder.Ferlemann(a)web.de> Idwer Vollering <idwer_v(a)hotmail.com> +Josh Profitt <zorn169(a)gmail.com> Rasmus Wiman <rasmus(a)wiman.org> Robinson P. Tryon <bishop.robinson(a)gmail.com> Ronald Hoogenboom <hoogenboom30(a)zonnet.nl> Modified: trunk/util/superiotool/ite.c =================================================================== --- trunk/util/superiotool/ite.c 2008-10-13 23:18:56 UTC (rev 3656) +++ trunk/util/superiotool/ite.c 2008-10-14 16:28:50 UTC (rev 3657) @@ -294,26 +294,28 @@ {0x00,0x02,0x90,0x02,0x30,0x09,0x00,0x00,0x00,0x00, 0x00,NANA,NANA,EOT}}, {0x5, "Keyboard", + /* 0xf0: Datasheet page 33: 0x00; page 56: 0x08. */ {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0xf0,EOT}, {0x01,0x00,0x60,0x00,0x64,0x01,0x02,0x00,EOT}}, {0x6, "Mouse", {0x30,0x70,0x71,0xf0,EOT}, {0x00,0x0c,0x02,0x00,EOT}}, {0x7, "GPIO", + /* 0x2c: Datasheet page 30: 0x00; page 43: 0x1f. */ {0x25,0x26,0x27,0x28,0x29,0x2a,0x2c,0x60,0x61,0x62, 0x63,0x64,0x65,0x70,0x71,0x72,0x73,0x74,0xb0,0xb1, 0xb2,0xb3,0xb4,0xb5,0xb8,0xb9,0xba,0xbb,0xbc,0xbd, - 0xc0,0xc1,0xc2,0xc3,0xc4,0xc8,0xc9,0xca,0xcb,0xcc, - 0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xf0,0xf1, - 0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xfb, - 0xfc,0xfd,0xfe,0xff,EOT}, + 0xc0,0xc1,0xc2,0xc3,0xc4,0xc5,0xc8,0xc9,0xca,0xcb, + 0xcc,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xf0, + 0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa, + 0xfb,0xfc,0xfd,0xfe,0xff,EOT}, {0x01,0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x20,0x38,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x01,0x00,0x00,0x40,0x00,0x01,0x00,0x00,0x40,0x00, + 0x01,0x00,0x00,0x40,0x00,0x00,0x01,0x00,0x00,0x40, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - NANA,0x00,0x00,0x00,EOT}}, + 0x00,NANA,0x00,0x00,0x00,EOT}}, {0xa, "Consumer IR", {0x30,0x60,0x61,0x70,0xf0,EOT}, {0x00,0x03,0x10,0x0b,0x00,EOT}}, @@ -322,6 +324,56 @@ {EOT}}}, {0x8726, "IT8726F", { /* Datasheet wrongly says that the ID is 0x8716. */ + {NOLDN, NULL, + {0x20,0x21,0x22,0x23,0x24,0x2b,EOT}, + {0x87,0x26,0x01,0x00,MISC,0x00,EOT}}, + {0x0, "Floppy", + {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,EOT}, + {0x00,0x03,0xf0,0x06,0x02,0x00,0x00,EOT}}, + {0x1, "COM1", + {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,0xf3,EOT}, + {0x00,0x03,0xf8,0x04,0x00,0x50,0x00,0x7f,EOT}}, + {0x2, "COM2", + {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,0xf3,EOT}, + {0x00,0x02,0xf8,0x03,0x00,0x50,0x00,0x7f,EOT}}, + {0x3, "Parallel port", + {0x30,0x60,0x61,0x62,0x63,0x70,0x74,0xf0,EOT}, + {0x00,0x03,0x78,0x07,0x78,0x07,0x03,0x03,EOT}}, + {0x4, "Environment controller", + {0x30,0x60,0x61,0x62,0x63,0x70,0xf0,0xf1,0xf2,0xf3, + 0xf4,0xf5,0xf6,EOT}, + {0x00,0x02,0x90,0x02,0x30,0x09,0x00,0x00,0x00,0x00, + 0x00,MISC,MISC,EOT}}, + {0x5, "Keyboard", + /* 0xf0: Datasheet page 35: 0x00; page 59: 0x08. */ + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0xf0,EOT}, + {0x01,0x00,0x60,0x00,0x64,0x01,0x02,0x08,EOT}}, + {0x6, "Mouse", + {0x30,0x70,0x71,0xf0,EOT}, + {0x00,0x0c,0x02,0x00,EOT}}, + {0x7, "GPIO", + /* 0x2c: Datasheet page 33: 0x00; page 45: 0x1f. */ + {0x25,0x26,0x27,0x28,0x29,0x2a,0x2c,0x60,0x61,0x62, + 0x63,0x64,0x65,0x70,0x71,0x72,0x73,0x74,0xb0,0xb1, + 0xb2,0xb3,0xb4,0xb5,0xb8,0xb9,0xba,0xbb,0xbc,0xbd, + 0xc0,0xc1,0xc2,0xc3,0xc4,0xc8,0xc9,0xca,0xcb,0xcc, + 0xe0,0xe1,0xe2,0xe3,0xe4,0xf0,0xf1,0xf2,0xf3,0xf4, + 0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xfb,0xfc,0xfd,EOT}, + {0x01,0x00,0x00,0x40,0x00,0x00,0x1f,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,MISC,0x38,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x01,0x00,0x00,0x40,0x00,0x01,0x00,0x00,0x40,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,MISC,0x00,EOT}}, + {0x8, "MIDI port", + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {0x00,0x03,0x00,0x0a,0x00,EOT}}, + {0x9, "Game port", + {0x30,0x60,0x61,EOT}, + {0x00,0x02,0x01,EOT}}, + {0xa, "Consumer IR", + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {0x00,0x03,0x10,0x0b,0x00,EOT}}, {EOT}}}, {EOT} };

1 0

[PATCH]: v2: Move AMD RS690/SB600 PCI IDs to pci_ids.h
by Uwe Hermann 14 Oct '08

14 Oct '08

See patch. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

4 6

r926 - coreboot-v3/device
by svn＠coreboot.org 14 Oct '08

14 Oct '08

Author: myles Date: 2008-10-14 14:27:23 +0200 (Tue, 14 Oct 2008) New Revision: 926 Modified: coreboot-v3/device/pci_rom.c Log: Because the enable bit was masked off, checking for 0xffffffff didn't work. This patch changes the place where the bit is masked. The other way to fix it would be to check for 0xfffffffe. V2 doesn't seem to have the problem. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/device/pci_rom.c =================================================================== --- coreboot-v3/device/pci_rom.c 2008-10-14 10:14:06 UTC (rev 925) +++ coreboot-v3/device/pci_rom.c 2008-10-14 12:27:23 UTC (rev 926) @@ -65,7 +65,7 @@ /* Override in place? */ rom_address = dev->rom_address; } else { - rom_address = pci_read_config32(dev, PCI_ROM_ADDRESS) & 0xfffffffe; + rom_address = pci_read_config32(dev, PCI_ROM_ADDRESS); } } @@ -74,6 +74,8 @@ return NULL; } + rom_address = rom_address & ~PCI_ROM_ADDRESS_ENABLE; + printk(BIOS_DEBUG, "ROM address for %s = %lx\n", dev_path(dev), rom_address); @@ -94,7 +96,7 @@ le32_to_cpu(rom_header->signature)); return NULL; } - + /* checksum */ rom_bytes = (unsigned char *)rom_address; for (i = 0; i < rom_header->size * 512; i++) @@ -166,7 +168,7 @@ return NULL; // Only one VGA supported. #endif if (rom_header != (void *)PCI_VGA_RAM_IMAGE_START) { - printk(BIOS_DEBUG, "Copying VGA ROM image from %p to 0x%x, 0x%x bytes\n", + printk(BIOS_DEBUG, "Copying VGA ROM image from %p to 0x%x, 0x%x bytes\n", rom_header, PCI_VGA_RAM_IMAGE_START, rom_size); memcpy((void *)PCI_VGA_RAM_IMAGE_START, rom_header, rom_size); }

1 0

[PATCH] v3: Improve ITE IT8712F support
by Uwe Hermann 14 Oct '08

14 Oct '08

See patch. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

2 2

[PATCH] v3: Fixup Fintek F71805F dts
by Uwe Hermann 14 Oct '08

14 Oct '08

See patch. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

2 2

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coreboot October 2008