coreboot October 2008

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r934 - coreboot-v3/southbridge/amd/rs690
by svn＠coreboot.org 16 Oct '08

16 Oct '08

Author: rminnich Date: 2008-10-16 18:02:12 +0200 (Thu, 16 Oct 2008) New Revision: 934 Added: coreboot-v3/southbridge/amd/rs690/pcie2.dts coreboot-v3/southbridge/amd/rs690/pcie3.dts coreboot-v3/southbridge/amd/rs690/pcie4.dts coreboot-v3/southbridge/amd/rs690/pcie5.dts coreboot-v3/southbridge/amd/rs690/pcie6.dts coreboot-v3/southbridge/amd/rs690/pcie7.dts coreboot-v3/southbridge/amd/rs690/pcie8.dts Modified: coreboot-v3/southbridge/amd/rs690/pcie.c Log: Having received no comments on this pro or con, and knowing we have to have this code, I'm comitting it. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/southbridge/amd/rs690/pcie.c =================================================================== --- coreboot-v3/southbridge/amd/rs690/pcie.c 2008-10-16 03:03:33 UTC (rev 933) +++ coreboot-v3/southbridge/amd/rs690/pcie.c 2008-10-16 16:02:12 UTC (rev 934) @@ -393,6 +393,7 @@ .set_subsystem = 0, }; + struct device_operations rs690_pcie = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_ATI, @@ -407,16 +408,94 @@ .ops_pci = &lops_pci, }; -/* not yet until we figure out how to handle gpp_configuration and port_enable -- are they per port or per chip? Should they - * be per port or per chip? -static struct pci_driver pcie_driver_dev7 __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV7, +/* the rest of these have no phase4_enable_disable; it is all managed by the above device. */ +struct device_operations rs690_pcie2 = { + .id = {.type = DEVICE_ID_PCI, + {.pci = {.vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV2}}}, + .constructor = default_device_constructor, + .phase3_scan = pci_scan_bridge, + .phase4_read_resources = pci_bus_read_resources, + .phase4_set_resources = pci_dev_set_resources, + .phase5_enable_resources = pci_bus_enable_resources, + .phase6_init = pcie_init, + .ops_pci = &lops_pci, }; -static struct pci_driver pcie_driver_dev8 __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV8, + +struct device_operations rs690_pcie3 = { + .id = {.type = DEVICE_ID_PCI, + {.pci = {.vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV3}}}, + .constructor = default_device_constructor, + .phase3_scan = pci_scan_bridge, + .phase4_read_resources = pci_bus_read_resources, + .phase4_set_resources = pci_dev_set_resources, + .phase5_enable_resources = pci_bus_enable_resources, + .phase6_init = pcie_init, + .ops_pci = &lops_pci, }; -*/ + +struct device_operations rs690_pcie4 = { + .id = {.type = DEVICE_ID_PCI, + {.pci = {.vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV4}}}, + .constructor = default_device_constructor, + .phase3_scan = pci_scan_bridge, + .phase4_read_resources = pci_bus_read_resources, + .phase4_set_resources = pci_dev_set_resources, + .phase5_enable_resources = pci_bus_enable_resources, + .phase6_init = pcie_init, + .ops_pci = &lops_pci, +}; + +struct device_operations rs690_pcie5 = { + .id = {.type = DEVICE_ID_PCI, + {.pci = {.vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV5}}}, + .constructor = default_device_constructor, + .phase3_scan = pci_scan_bridge, + .phase4_read_resources = pci_bus_read_resources, + .phase4_set_resources = pci_dev_set_resources, + .phase5_enable_resources = pci_bus_enable_resources, + .phase6_init = pcie_init, + .ops_pci = &lops_pci, +}; + +struct device_operations rs690_pcie6 = { + .id = {.type = DEVICE_ID_PCI, + {.pci = {.vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV6}}}, + .constructor = default_device_constructor, + .phase3_scan = pci_scan_bridge, + .phase4_read_resources = pci_bus_read_resources, + .phase4_set_resources = pci_dev_set_resources, + .phase5_enable_resources = pci_bus_enable_resources, + .phase6_init = pcie_init, + .ops_pci = &lops_pci, +}; + +struct device_operations rs690_pcie7 = { + .id = {.type = DEVICE_ID_PCI, + {.pci = {.vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV7}}}, + .constructor = default_device_constructor, + .phase3_scan = pci_scan_bridge, + .phase4_read_resources = pci_bus_read_resources, + .phase4_set_resources = pci_dev_set_resources, + .phase5_enable_resources = pci_bus_enable_resources, + .phase6_init = pcie_init, + .ops_pci = &lops_pci, +}; + +struct device_operations rs690_pcie8 = { + .id = {.type = DEVICE_ID_PCI, + {.pci = {.vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_RS690_PCIE_DEV8}}}, + .constructor = default_device_constructor, + .phase3_scan = pci_scan_bridge, + .phase4_read_resources = pci_bus_read_resources, + .phase4_set_resources = pci_dev_set_resources, + .phase5_enable_resources = pci_bus_enable_resources, + .phase6_init = pcie_init, + .ops_pci = &lops_pci, +}; Added: coreboot-v3/southbridge/amd/rs690/pcie2.dts =================================================================== --- coreboot-v3/southbridge/amd/rs690/pcie2.dts (rev 0) +++ coreboot-v3/southbridge/amd/rs690/pcie2.dts 2008-10-16 16:02:12 UTC (rev 934) @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +/* +#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) +#Define vga_rom_address = 0xfff0000 +#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) + */ +{ + device_operations = "rs690_pcie2"; +}; Added: coreboot-v3/southbridge/amd/rs690/pcie3.dts =================================================================== --- coreboot-v3/southbridge/amd/rs690/pcie3.dts (rev 0) +++ coreboot-v3/southbridge/amd/rs690/pcie3.dts 2008-10-16 16:02:12 UTC (rev 934) @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +/* +#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) +#Define vga_rom_address = 0xfff0000 +#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) + */ +{ + device_operations = "rs690_pcie3"; +}; Added: coreboot-v3/southbridge/amd/rs690/pcie4.dts =================================================================== --- coreboot-v3/southbridge/amd/rs690/pcie4.dts (rev 0) +++ coreboot-v3/southbridge/amd/rs690/pcie4.dts 2008-10-16 16:02:12 UTC (rev 934) @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +/* +#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) +#Define vga_rom_address = 0xfff0000 +#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) + */ +{ + device_operations = "rs690_pcie4"; +}; Added: coreboot-v3/southbridge/amd/rs690/pcie5.dts =================================================================== --- coreboot-v3/southbridge/amd/rs690/pcie5.dts (rev 0) +++ coreboot-v3/southbridge/amd/rs690/pcie5.dts 2008-10-16 16:02:12 UTC (rev 934) @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +/* +#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) +#Define vga_rom_address = 0xfff0000 +#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) + */ +{ + device_operations = "rs690_pcie5"; +}; Added: coreboot-v3/southbridge/amd/rs690/pcie6.dts =================================================================== --- coreboot-v3/southbridge/amd/rs690/pcie6.dts (rev 0) +++ coreboot-v3/southbridge/amd/rs690/pcie6.dts 2008-10-16 16:02:12 UTC (rev 934) @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +/* +#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) +#Define vga_rom_address = 0xfff0000 +#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) + */ +{ + device_operations = "rs690_pcie6"; +}; Added: coreboot-v3/southbridge/amd/rs690/pcie7.dts =================================================================== --- coreboot-v3/southbridge/amd/rs690/pcie7.dts (rev 0) +++ coreboot-v3/southbridge/amd/rs690/pcie7.dts 2008-10-16 16:02:12 UTC (rev 934) @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +/* +#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) +#Define vga_rom_address = 0xfff0000 +#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) + */ +{ + device_operations = "rs690_pcie7"; +}; Added: coreboot-v3/southbridge/amd/rs690/pcie8.dts =================================================================== --- coreboot-v3/southbridge/amd/rs690/pcie8.dts (rev 0) +++ coreboot-v3/southbridge/amd/rs690/pcie8.dts 2008-10-16 16:02:12 UTC (rev 934) @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +/* +#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) +#Define vga_rom_address = 0xfff0000 +#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) + */ +{ + device_operations = "rs690_pcie8"; +};

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r3660 - trunk/coreboot-v2/src/southbridge/via/vt8237r
by svn＠coreboot.org 16 Oct '08

16 Oct '08

Author: hailfinger Date: 2008-10-16 17:05:18 +0200 (Thu, 16 Oct 2008) New Revision: 3660 Modified: trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r.h Log: Revision 3567 introduced __attribute__((packed)) for a structured which is also visible to ROMCC and ROMCC doesn't understand that. The fix is to use __attribute__((packed)) only for gcc compiled code. This has been unfixed for too long. There are more problems remaining, but at least this one is solvable easily. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r.h =================================================================== --- trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r.h 2008-10-15 17:50:29 UTC (rev 3659) +++ trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r.h 2008-10-16 15:05:18 UTC (rev 3660) @@ -93,6 +93,10 @@ u8 cfg_c; u8 cfg_d; u8 checksum; -} __attribute__ ((packed)); +} +#if defined(__GNUC__) +__attribute__ ((packed)) +#endif +; #endif

1 0

r3657 build service
by coreboot information 16 Oct '08

16 Oct '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "uwe" checked in revision 3657 to the coreboot source repository and caused the following changes: Change Log: Add dump support to ITE IT8726F, and add comments and a missing GPIO register to ITE IT8718F. Signed-off-by: Josh Profitt <zorn169(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of azza:pt-6ibd has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3657&device=pt-6ibd&vendor… Compilation of iei:nova4899r has been fixed Compilation of jetway:j7f24 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3657&device=j7f24&vendor=j… Compilation of supermicro:x6dhr_ig has been fixed Compilation of televideo:tc7020 has been fixed Compilation of via:epia-cn is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3657&device=epia-cn&vendor… Compilation of via:pc2500e is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3657&device=pc2500e&vendor… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

r3656 build service
by coreboot information 16 Oct '08

16 Oct '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "eswierk" checked in revision 3656 to the coreboot source repository and caused the following changes: Change Log: Add support for the Intel EP80579 (Tolapai) Development Kit mainboard (Truxton). Signed-off-by: Ed Swierk <eswierk(a)arastra.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Build Log: Compilation of asus:p2b has been fixed Compilation of iei:juki-511p has been fixed Compilation of iei:nova4899r has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3656&device=nova4899r&vend… Compilation of jetway:j7f24 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3656&device=j7f24&vendor=j… Compilation of supermicro:x6dhe_g2 has been fixed Compilation of supermicro:x6dhr_ig has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3656&device=x6dhr_ig&vendo… Compilation of televideo:tc7020 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3656&device=tc7020&vendor=… Compilation of via:epia-cn is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3656&device=epia-cn&vendor… Compilation of via:pc2500e is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3656&device=pc2500e&vendor… If something broke during this checkin please be a pain in eswierk's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

r3655 build service
by coreboot information 16 Oct '08

16 Oct '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "uwe" checked in revision 3655 to the coreboot source repository and caused the following changes: Change Log: Move AMD RS690 and SB600 PCI IDs to pci_ids.h where they should be. Build-tested with the AMD dbm690t board. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Marc Jones <marc.jones(a)amd.com> Build Log: Compilation of asus:p2b has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3655&device=p2b&vendor=asus Compilation of iei:juki-511p has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3655&device=juki-511p&vend… Compilation of jetway:j7f24 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3655&device=j7f24&vendor=j… Compilation of supermicro:x6dhe_g2 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3655&device=x6dhe_g2&vendo… Compilation of via:epia-cn is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3655&device=epia-cn&vendor… Compilation of via:pc2500e is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3655&device=pc2500e&vendor… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

r3654 build service
by coreboot information 16 Oct '08

16 Oct '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "uwe" checked in revision 3654 to the coreboot source repository and caused the following changes: Change Log: Drop unused (or commented / #if 0) reset.c files. This is abuild-tested by me. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Peter Stuge <peter(a)stuge.se> Build Log: Compilation of asus:p3b-f has been fixed Compilation of ibm:e326 has been fixed Compilation of jetway:j7f24 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3654&device=j7f24&vendor=j… Compilation of via:epia has been fixed Compilation of via:epia-cn is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3654&device=epia-cn&vendor… Compilation of via:epia-m has been fixed Compilation of via:pc2500e is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3654&device=pc2500e&vendor… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

r3653 build service
by coreboot information 16 Oct '08

16 Oct '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "uwe" checked in revision 3653 to the coreboot source repository and caused the following changes: Change Log: Drop tons of duplicated debug.c files, move common file to lib/debug.c and use that one. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Peter Stuge <peter(a)stuge.se> Build Log: Compilation of amd:rumba has been fixed Compilation of asus:p3b-f has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3653&device=p3b-f&vendor=a… Compilation of gigabyte:ga-6bxc has been fixed Compilation of ibm:e326 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3653&device=e326&vendor=ibm Compilation of jetway:j7f24 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3653&device=j7f24&vendor=j… Compilation of lippert:frontrunner has been fixed Compilation of olpc:rev_a has been fixed Compilation of supermicro:x6dhe_g has been fixed Compilation of televideo:tc7020 has been fixed Compilation of via:epia has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3653&device=epia&vendor=via Compilation of via:epia-cn is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3653&device=epia-cn&vendor… Compilation of via:epia-m has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3653&device=epia-m&vendor=… Compilation of via:pc2500e is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3653&device=pc2500e&vendor… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

r3652 build service
by coreboot information 16 Oct '08

16 Oct '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "cozzie" checked in revision 3652 to the coreboot source repository and caused the following changes: Change Log: Remove an extra bracket left by the vt8237r cleanup patch (trivial) Signed-off-by: Corey Osgood <corey.osgood(a)gmail.com> Acked-by: Corey Osgood <corey.osgood(a)gmail.com> Build Log: Compilation of amd:rumba has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3652&device=rumba&vendor=a… Compilation of asus:a8v-e_se has been fixed Compilation of asus:m2v-mx_se has been fixed Compilation of gigabyte:ga-6bxc has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3652&device=ga-6bxc&vendor… Compilation of jetway:j7f24 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3652&device=j7f24&vendor=j… Compilation of lippert:frontrunner has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3652&device=frontrunner&ve… Compilation of olpc:rev_a has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3652&device=rev_a&vendor=o… Compilation of supermicro:x6dhe_g has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3652&device=x6dhe_g&vendor… Compilation of televideo:tc7020 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3652&device=tc7020&vendor=… Compilation of via:epia-cn is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3652&device=epia-cn&vendor… Compilation of via:pc2500e is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3652&device=pc2500e&vendor… If something broke during this checkin please be a pain in cozzie's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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is HP Pavilion dv1000 supported?
by 王晓林 16 Oct '08

16 Oct '08

Hi, list I have a HP Pavilion dv1000 laptop with Debian sid installed, and I'd like to try coreboot. Is it supported? Thanks! The detailed HW spec I know is from lspci and /proc/cpuinfo. lspci output: ------------ 00:00.0 Host bridge: Intel Corporation Mobile 915GM/PM/GMS/910GML Express Processor to DRAM Controller (rev 03) 00:02.0 VGA compatible controller: Intel Corporation Mobile 915GM/GMS/910GML Express Graphics Controller (rev 03) 00:02.1 Display controller: Intel Corporation Mobile 915GM/GMS/910GML Express Graphics Controller (rev 03) 00:1d.0 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #1 (rev 03) 00:1d.1 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #2 (rev 03) 00:1d.2 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #3 (rev 03) 00:1d.3 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #4 (rev 03) 00:1d.7 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB2 EHCI Controller (rev 03) 00:1e.0 PCI bridge: Intel Corporation 82801 Mobile PCI Bridge (rev d3) 00:1e.2 Multimedia audio controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) AC'97 Audio Controller (rev 03) 00:1e.3 Modem: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) AC'97 Modem Controller (rev 03) 00:1f.0 ISA bridge: Intel Corporation 82801FBM (ICH6M) LPC Interface Bridge (rev 03) 00:1f.1 IDE interface: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) IDE Controller (rev 03) 00:1f.3 SMBus: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) SMBus Controller (rev 03) 06:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ (rev 10) 06:06.0 Network controller: Intel Corporation PRO/Wireless 2200BG [Calexico2] Network Connection (rev 05) 06:09.0 CardBus bridge: Texas Instruments PCIxx21/x515 Cardbus Controller 06:09.2 FireWire (IEEE 1394): Texas Instruments OHCI Compliant IEEE 1394 Host Controller 06:09.3 Mass storage controller: Texas Instruments PCIxx21 Integrated FlashMedia Controller 06:09.4 SD Host controller: Texas Instruments PCI6411/6421/6611/6621/7411/7421/7611/7621 Secure Digital Controller /proc/cpuinfo: ------------- processor : 0 vendor_id : GenuineIntel cpu family : 6 model : 13 model name : Intel(R) Pentium(R) M processor 1.73GHz stepping : 8 cpu MHz : 1729.228 cache size : 2048 KB fdiv_bug : no hlt_bug : no f00f_bug : no coma_bug : no fpu : yes fpu_exception : yes cpuid level : 2 wp : yes flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat clflush dts acpi mmx fxsr sse sse2 ss tm pbe nx bts est tm2 bogomips : 3462.00 clflush size : 64 power management: -- Xiaolin Wang email: wx672ster(a)gmail.com mobile: 13577067397

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Fintek SPI driver for Flashrom (unfinished)
by Sean Nelson 16 Oct '08

16 Oct '08

Fintek SPI Driver file for Flashrom Index: fintek_spi.c =================================================================== --- fintek_spi.c (revision 0) +++ fintek_spi.c (revision 0) @@ -0,0 +1,384 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2008 Sean Nelson <snelson(a)nmt.edu> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Contains the Fintek F7188x SPI specific routines + * + * The Fintek SPI is different from the it87xxx SIO in that there's no + * base address to help program through SPI, but in the F7188x SIOs the + * SPI Interface is accessed through LDN 0x8 and configuration registers + * 0xf0 - 0xf8 and 0xfa - 0xff. + */ + +#include <stdio.h> +#include <pci/pci.h> +#include <stdint.h> +#include <string.h> +#include "flash.h" +#include "spi.h" + +#define FINTEK_SUPERIO_PORT1 0x4e +#define FINTEK_SUPERIO_PORT2 0x2e + +/* Logical Device Number for the SPI Device in Fintek SIO */ +#define SPI_LDN 0x08 + +/* the Configuration Register for ROM address masking + * Bit 7 is the ROM Write Enable. + * Bit 0 which enables address range 0xfff00000 - 0xfff7ffff + * The rest of the bits are 'power on trapped' + * via pull-up/down sio pin connections. + */ +#define FINTEK_SIO_ROM_ADDR_SELECT 0x27 + +/* Configuration Registers of the SPI Device */ +#define SPI_CTRL 0xf0 +#define SPI_TIMEOUT 0xf1 +#define SPI_BAUD 0xf2 +#define SPI_STATUS 0xf3 +#define SPI_H_DATA 0xf4 +#define SPI_CMD_DATA 0xf5 +#define SPI_CS 0xf6 +#define SPI_MMAP 0xf7 +#define SPI_OP 0xf8 +#define SPI_L_DATA 0xfa +#define SPI_H_ADDR 0xfb +#define SPI_M_ADDR 0xfc +#define SPI_L_ADDR 0xfd +#define SPI_PROG 0xfe +#define SPI_WR_DATA 0xff + +uint16_t fintek_flashport = 0; + +/* + * use fast 33MHz SPI (<>0) or slow 16MHz (0) + */ +int fast_spi = 1; + +/* + * for now assume SST Flash style continuous program mode + * set to 0 to use AMD style continuous + */ +int sst_continuous = 1; + +/* Generic Super I/O helper functions */ +uint8_t regval(uint16_t port, uint8_t reg) +{ + OUTB(reg, port); + return INB(port + 1); +} + +void regwrite(uint16_t port, uint8_t reg, uint8_t val) +{ + OUTB(reg, port); + OUTB(val, port + 1); +} + +/* Helper functions for most recent ITE IT87xx Super I/O chips */ +#define CHIP_ID_BYTE1_REG 0x20 +#define CHIP_ID_BYTE2_REG 0x21 +static void enter_conf_mode_fintek(uint16_t port) +{ + OUTB(0x87, port); + OUTB(0x87, port); +} + +static void exit_conf_mode_fintek(uint16_t port) +{ + OUTB(0xaa, port); +} + +static uint16_t find_fintek_spi_flash_port(uint16_t port) +{ + uint8_t tmp = 0; + uint16_t id, flashport = 0; + + enter_conf_mode_fintek(port); + + id = regval(port, CHIP_ID_BYTE1_REG) << 8; + id |= regval(port, CHIP_ID_BYTE2_REG); + + /* id 0x0541 is good for F71883 and F71882 according to datasheets */ + if (id == 0x0541) { + /* + * ROM Address Select Register (readonly): NOLDN, reg 0x27 + * bit 7 - ROM Write Enable + * bit 6 - SPI Enable + * bit 5 - use SPI as Backup BIOS; 0b = use SPI as Primary BIOS + * bit 4 - port 0x4e as config reg port; 0b = port is 2e + * bit 3 - enable addr 0x000e0000 to 0x000effff decoding + * + * bit 2 - enable addr 0xfff80000 to 0xffffffff decoding + * and addr 0x000f0000 to 0x000fffff decoding + * + * bit 1 - enable addr 0xffee000 to 0xffeeffff decoding + * + * bit 0 - enable addr 0xfff0000 to 0xfff7ffff decoding + * default: disable + */ + tmp = regval(port, 0x27); + printf("Serial flash segment 0x%08x-0x%08x %sabled\n", + 0xFFF00000, 0xFFF7FFFF, (tmp & 1 << 0) ? "en" : "dis"); + printf("Serial flash segment 0x%08x-0x%08x %sabled\n", + 0xFFEE0000, 0xFFEEFFFF, (tmp & 1 << 1) ? "en" : "dis"); + printf("Serial flash segment 0x%08x-0x%08x %sabled\n", + 0xFFF80000, 0xFFFFFFFF, (tmp & 1 << 2) ? "en" : "dis"); + printf("Serial flash segment 0x%08x-0x%08x %sabled\n", + 0x000F0000, 0x000FFFFF, (tmp & 1 << 2) ? "en" : "dis"); + printf("Serial flash segment 0x%08x-0x%08x %sabled\n", + 0x000E0000, 0x000EFFFF, (tmp & 1 << 3) ? "en" : "dis"); + printf("LPC write to serial flash %sabled\n", + (tmp & 1 << 7) ? "en" : "dis"); + + /* If any serial flash segment is enabled, enable writing. */ + if ((tmp & 0xf) && (!(tmp & 1 << 7))) { + printf("Enabling LPC write to serial flash\n"); + tmp |= 1 << 7; + regwrite(port, 0x27, tmp); + } + + /* + * Since we have to use configuration registers of the SIO, we use + * LDN 0x8, reg 0x27 to figure out the SIO port we use for SPI + * programming and use LDN 0x8's config registers in programming + * the flash via SPI. If bit 4 is 1 then the port is 0x4e, + * otherwise we use SIO port 0x2e. + */ + if (tmp & 1 << 4) + { + flashport = FINTEK_SUPERIO_PORT1; + } else + { + flashport = FINTEK_SUPERIO_PORT2; + } + } + exit_conf_mode_fintek(port); + return flashport; +} + +int fintek_probe_spi_flash(const char *name) +{ + fintek_flashport = find_ite_spi_flash_port(FINTEK_SUPERIO_PORT1); + + if (!fintek_flashport) + fintek_flashport = find_ite_spi_flash_port(FINTEK_SUPERIO_PORT2); + + if (fintek_flashport) + flashbus = BUS_TYPE_FINTEK_SPI; + + return (!fintek_flashport); +} + +/* + * spi commands use various SPI configuration registers: + * Baud Rate Divistor Register (0xf2) -- bits 2-0 chooses between + * 33MHz or 16.7MHz SCK frequency. + * Status Register (0xf3) -- Interrupt status and operation status. + * High Byte Data Register (0xf4) -- received upper 8 bits in a operation. + * Command Data Register (0xf5) -- command value for flash command. + * Operate Register (0xf8) -- setting a bit will start the IO of SPI + * Low Byte Data Register (0xfa) -- received lower 8 bits in a operation. + * Address High Byte Register (0xfb) -- high byte address for sector erase, + * program, read. + * Address Middle Byte Register (0xfc) -- similar to previous. + * Address Low Byte Register (0xfd) -- similar to previous. + * Program Byte Register (0xfe) -- byte for programming in continuous mode. + * Write Data Register (0xff) -- data to write flash for program, write status + */ + +/* NOTE: + * this has return paths that do not clean up; can be fixed by a little + * reordering of code and possibly a new variable + */ +int fintek_spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) +{ + uint8_t busy, op_busy, operate; + int i; + + /* can't read back more than 2 bytes, fail otherwise */ + if (readcnt > 2) { + printf("%s called with unsupported readcnt %i.\n", + __FUNCTION__, readcnt); + return 1; + } + + enter_conf_mode_fintek(fintek_flashport); + regwrite(fintek_flashport, 0x07, 0x8); + + /* 33 or 16 MHz, SST continuous mode. + */ + regwrite(fintek_flashport, 0xf2, (fast_spi ? 0 : 1)); + operate = regval(fintek_flashport, 0xf8) & 0x80; + regwrite(fintek_flashport, 0xf8, operate|((sst_continuous ? 1 : 0) << 7)); + + /* + * wait to make sure the SPI isn't doing anything, + * before we do our thing + */ + do { + busy = regval(fintek_flashport, 0xf3) & 0x04; + } while (busy); + + /* + * depending on the write mode and count fill registers with cmd and data + * + * the datasheet says the F7188x SIOs have a 3 byte addressing, + * 1 byte for command, 2 bytes for return data, and 1 byte writing + */ + switch (writecnt) { + case 1: /* when we only need to send a command byte */ + regwrite(fintek_flashport, 0xf5, writearr[0]); + break; + case 2: /* when we need to send a cmd byte and a write_data byte */ + regwrite(fintek_flashport, 0xf5, writearr[0]); + regwrite(fintek_flashport, 0xff, writearr[1]); + break; + case 4: /* when we need to send a cmd byte and an address */ + regwrite(fintek_flashport, 0xf5, writearr[0]); + regwrite(fintek_flashport, 0xfb, writearr[1]); + regwrite(fintek_flashport, 0xfc, writearr[2]); + regwrite(fintek_flashport, 0xfd, writearr[3]); + break; + case 5: + /* when we need to send a cmd byte, write_data byte, and address */ + regwrite(fintek_flashport, 0xf5, writearr[0]); + regwrite(fintek_flashport, 0xfb, writearr[1]); + regwrite(fintek_flashport, 0xfc, writearr[2]); + regwrite(fintek_flashport, 0xfd, writearr[3]); + regwrite(fintek_flashport, 0xff, writearr[4]); + break; + /* + * Just in case, we somehow get a unknown byte count for a command + */ + default: + printf("%s called with unsupported writecnt %i.\n", + __FUNCTION__, writecnt); + return 1; + } + + /* + * The Fintek F7188x SuperIOs use a SPI operate Register at Index 0xf8 to + * set off the execution of various SPI functions + */ + operate = regval(fintek_flashport, 0xf8); + switch(writearr[0]) + { + case JEDEC_RDSR: + regwrite(fintek_flashport, 0xf8, operate|(1 << 5)); + break; + case JEDEC_WRSR: + regwrite(fintek_flashport, 0xf8, operate|(1 << 4)); + break; + case JEDEC_SE: + regwrite(fintek_flashport, 0xf8, operate|(1 << 3)); + break; + case JEDEC_RDID: + regwrite(fintek_flashport, 0xf8, operate|(1 << 2)); + break; + case JEDEC_BYTE_PROGRAM: + regwrite(fintek_flashport, 0xf8, operate|(1 << 1)); + break; + case JEDEC_READ: + regwrite(fintek_flashport, 0xf8, operate|(1 << 0)); + break; + default: /* IO_SPI */ + regwrite(fintek_flashport, 0xf8, operate|(1 << 6)); + } + + do { + op_busy = regval(fintek_flashport, 0xf8) & 0x7f + } while (op_busy);/* wait for op to finish */ + + if (readcnt > 0) { + /* + * wait to make sure that the SPI isn't working, and to + * insure that we can actually save the return data + * from SPI slave device + */ + do { + busy = regval(fintek_flashport, 0xf3) & 0x08; + } while (busy); + + /* save the low byte from SPI first */ + readarr[0] = regval(fintek_flashport, 0xfa); + /* next save the high byte from SPI */ + readarr[1] = regval(fintek_flashport, 0xf4); + } + exit_conf_mode_fintek(fintek_flashport); + + return 0; +} + +/* NOTE: use flash->page_size or somesuch that should be used + * am i sure that the scheme will work? + */ +static void fintek_spi_page_program(struct flashchip *flash, int block, uint8_t *buf, uint8_t *bios) { + int i; + uint8_t oper, op_busy; + + spi_write_enable(); /* tell the SPI slave device to enable write */ + + enter_conf_mode_fintek(fintek_flashport); + regwrite(fintek_flashport, 0x07, 0x8); /* SPI device select */ + + regwrite(fintek_flashport, 0xf5, 0x06); /* CMD_DATA */ + regwrite(fintek_flashport, 0xf2, (fast_spi ? 0 : 1 )); /* set SPI data */ + + + for (i = 0; i < flash->page_size; i++) { + bios[flash->page_size * block + i] = buf[flash->page_size * block + i]; + + /* we have to start off the SPI during a memory cycle */ + oper = regval(fintek_flashport, 0xf8); + regwrite(fintek_flashport, 0xf8, oper|(1 << 1)); + do { + op_busy = regval(fintek_flashport, 0xf8) & 0x7f + } while (op_busy);/* wait for op to finish */ + } + + regwrite(fintek_flashport, 0xf0, 0); + exit_conf_mode_fintek(fintek_flashport); + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 1-10 ms, so wait in 1 ms steps. + */ + while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + usleep(1000); +} + +int fintek_spi_chip_read(struct flashchip *flash, uint8_t *buf) +{ + int total_size = 1024 * flash->total_size; + int i; + fast_spi = 0; + /* NOTE: it is said that the fintek can be set up for a large + * decode window; so we can just use a memcpy + */ + memcpy(buf, (const char *)flash->virtual_memory, total_size); + return 0; +} + +int fintek_spi_chip_write(struct flashchip *flash, uint8_t *buf) { + int total_size = 1024 * flash->total_size; + int i; + for (i = 0; i < total_size / flash->page_size; i++) { + fintek_spi_page_program(flash, i, buf, (uint8_t *)flash->virtual_memory); + } + return 0; +} +

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coreboot October 2008