coreboot October 2008

coreboot@coreboot.org

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608 discussions

Re: [coreboot] Resource Allocation problems
by Myles Watson 18 Oct '08

18 Oct '08

On Fri, Oct 17, 2008 at 4:27 PM, ron minnich <rminnich(a)gmail.com> wrote: > On Fri, Oct 17, 2008 at 3:26 PM, Myles Watson <mylesgw(a)gmail.com> wrote: > > > It's interesting to me that there is no corresponding resource for the > > FC0003 00FFFF00 pair. They get set in the resource map and are never > > touched again. > > Do you know when they get set? > Stage1: enable rom ... setting up resource map ex offset.... snip (0+0,18+0,1+0,bc) & 00000048 | 00ffff00+00000000 ... (0+0,18+0,1+0,b8) & 000000f0 | 00fc0003+00000000 snip At the very beginning. Thanks, Myles

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[PATCH] v2: BCOM WinNETP680 improvements
by Uwe Hermann 17 Oct '08

17 Oct '08

See patch. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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Resource Allocation problems
by Myles Watson 17 Oct '08

17 Oct '08

This is the resource tree for SimNOW: Root Device resource base 1000 size 2000 align c gran 0 limit ffff flags 40000100 Root Device resource base fd000000 size 1200000 align 18 gran 0 limit febfffff flags 40000200 PCI_DOMAIN: 0000 resource base 400 size 0 align 0 gran 0 limit ffff flags 40040100 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit fcffffffff flags 40040200 PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 PCI_DOMAIN: 0000 resource base c0000 size ff40000 align 0 gran 0 limit 0 flags e0004200 PCI: 00:18.0 resource base fe200000 size 0 align 14 gran 14 limit ffffffffff flags 60001200 PCI: 00:18.0 resource base 1000 size 2000 align c gran c limit ffff flags 60000100 PCI: 00:18.0 resource base fd000000 size 1200000 align 18 gran 14 limit febfffff flags 60000200 PCI: 00:18.0 resource base 3000 size 0 align c gran c limit ffff flags 60000100 PCI: 00:18.0 resource base fe200000 size 0 align 14 gran 14 limit ffffffffff flags 60001200 PCI: 00:18.0 resource base fe200000 size 0 align 14 gran 14 limit ffffffffff flags 60000200 PCI: 00:18.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags 0 PCI: 00:06.0 resource base 1000 size 1000 align c gran c limit ffff flags 60000102 PCI: 00:06.0 resource base fd000000 size 1100000 align 18 gran 14 limit febfffff flags 60000202 PCI: 01:00.0 resource base fe050000 size 1000 align c gran c limit ffffffff flags 60000200 PCI: 01:00.1 resource base fe051000 size 1000 align c gran c limit ffffffff flags 60000200 PCI: 01:00.2 resource base fe054000 size 100 align 8 gran 8 limit ffffffff flags 60000200 PCI: 01:01.0 resource base fe052000 size 1000 align c gran c limit ffffffff flags 60000200 PCI: 01:04.0 resource base fd000000 size 1000000 align 18 gran 18 limit ffffffff flags 60000200 PCI: 01:04.0 resource base fe055000 size 100 align 8 gran 8 limit ffffffff flags 60000200 PCI: 01:04.0 resource base 1000 size 100 align 8 gran 8 limit ffff flags 60000100 PCI: 01:04.0 resource base fe040000 size 10000 align 10 gran 10 limit ffffffff flags 60002200 PCI: 01:05.0 resource base fe000000 size 20000 align 11 gran 11 limit ffffffff flags 60000200 PCI: 01:05.0 resource base fe020000 size 20000 align 11 gran 11 limit ffffffff flags 60000200 PCI: 01:05.0 resource base 1400 size 40 align 6 gran 6 limit ffff flags 60000100 PCI: 01:05.0 resource base fe053000 size 800 align b gran b limit ffffffff flags 60002200 PCI: 00:07.0 resource base 0 size 0 align 0 gran 0 limit 0 flags 40040100 PCI: 00:07.0 resource base 0 size 0 align 0 gran 0 limit 0 flags 40040200 PCI: 00:07.1 resource base 2c60 size 10 align 4 gran 4 limit ffff flags 60000100 PCI: 00:07.2 resource base 2c40 size 20 align 5 gran 5 limit ffff flags 60000100 PCI: 00:07.5 resource base 2000 size 100 align 8 gran 8 limit ffff flags 60000100 PCI: 00:07.5 resource base 2c00 size 40 align 6 gran 6 limit ffff flags 60000100 PCI: 00:07.6 resource base 2400 size 100 align 8 gran 8 limit ffff flags 60000100 PCI: 00:07.6 resource base 2800 size 80 align 7 gran 7 limit ffff flags 60000100 PCI: 00:07.7 resource base fe100000 size 1000 align c gran c limit ffffffff flags 60000200 PCI: 00:07.7 resource base 2880 size 80 align 7 gran 7 limit ffff flags 60000100 PCI: 00:0a.1 resource base fe101000 size 1000 align c gran c limit ffffffffffffffff flags 60000201 PCI: 00:0b.1 resource base fe102000 size 1000 align c gran c limit ffffffffffffffff flags 60000201 There are several resources of size zero. Can we get rid of them? There is a nearly duplicated resource for 0:18.0, both of which are size 0. Thanks, Myles

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temporary fix
by Myles Watson 17 Oct '08

17 Oct '08

This allows me to keep going while the details of where code lives gets worked out. I removed printk references and copied the definitions of the PCI functions. No need to commit ever. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

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r3667 - trunk/coreboot-v2/src/mainboard/jetway/j7f24
by svn＠coreboot.org 17 Oct '08

17 Oct '08

Author: cozzie Date: 2008-10-17 16:17:05 +0200 (Fri, 17 Oct 2008) New Revision: 3667 Modified: trunk/coreboot-v2/src/mainboard/jetway/j7f24/Options.lb Log: One more little fix for the Jetway J7F[24], option tables can only be built in the normal image, not fallback. Signed-off-by: Corey Osgood <corey.osgood(a)gmail.com> Acked-by: Corey Osgood <corey.osgood(a)gmail.com> Modified: trunk/coreboot-v2/src/mainboard/jetway/j7f24/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/jetway/j7f24/Options.lb 2008-10-17 02:47:20 UTC (rev 3666) +++ trunk/coreboot-v2/src/mainboard/jetway/j7f24/Options.lb 2008-10-17 14:17:05 UTC (rev 3667) @@ -83,14 +83,14 @@ default HAVE_PIRQ_TABLE = 1 default IRQ_SLOT_COUNT = 10 default HAVE_ACPI_TABLES = 0 -default HAVE_OPTION_TABLE = 1 +default HAVE_OPTION_TABLE = 0 default ROM_IMAGE_SIZE = 64 * 1024 default FALLBACK_SIZE = ROM_SIZE default USE_FALLBACK_IMAGE = 1 default STACK_SIZE = 8 * 1024 default HEAP_SIZE = 16 * 1024 -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 +default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +#default USE_OPTION_TABLE = 0 default _RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 default CROSS_COMPILE = ""

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r3666 build service
by coreboot information 17 Oct '08

17 Oct '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "cozzie" checked in revision 3666 to the coreboot source repository and caused the following changes: Change Log: Config-abuild.lb's for jetway/j7f24 and bcom/winnetp680, to (finally) get abuild to stop complaining about these boards. They build fine with the default configs on a regular build. Signed-off-by: Corey Osgood <corey.osgood(a)gmail.com> Acked-by: Corey Osgood <corey.osgood(a)gmail.com> Build Log: Compilation of bcom:winnetp680 has been fixed Compilation of jetway:j7f24 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3666&device=j7f24&vendor=j… Compilation of msi:ms7135 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3666&device=ms7135&vendor=… If something broke during this checkin please be a pain in cozzie's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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r3665 build service
by coreboot information 17 Oct '08

17 Oct '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "cozzie" checked in revision 3665 to the coreboot source repository and caused the following changes: Change Log: Final fix for C7 boards, which are still using ROMCC, to be able to build. As far as I know, no C7 boards currently in the tree use SPI flash. Signed-off-by: Corey Osgood <corey.osgood(a)gmail.com> Acked-by: Peter Stuge <peter(a)stuge.se> Build Log: Compilation of bcom:winnetp680 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3665&device=winnetp680&ven… Compilation of jetway:j7f24 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3665&device=j7f24&vendor=j… Compilation of supermicro:h8dmr has been fixed Compilation of via:epia-cn has been fixed Compilation of via:pc2500e has been fixed If something broke during this checkin please be a pain in cozzie's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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r3664 build service
by coreboot information 17 Oct '08

17 Oct '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "hailfinger" checked in revision 3664 to the coreboot source repository and caused the following changes: Change Log: ROMCC chokes on vt8237_early_network_init(). Since that function is only called from one target and that target is compiled with GCC, make the function dependent on GCC. ROMCC also chokes on the ULL suffix for integer constants. Change the affected ones to UL for ROMCC compiled code. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Build Log: Compilation of bcom:winnetp680 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3664&device=winnetp680&ven… Compilation of jetway:j7f24 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3664&device=j7f24&vendor=j… Compilation of supermicro:h8dmr has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3664&device=h8dmr&vendor=s… Compilation of technologic:ts5300 has been fixed Compilation of tyan:s4882 has been fixed Compilation of via:epia-cn is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3664&device=epia-cn&vendor… Compilation of via:pc2500e is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3664&device=pc2500e&vendor… If something broke during this checkin please be a pain in hailfinger's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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r3663 build service
by coreboot information 17 Oct '08

17 Oct '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "hailfinger" checked in revision 3663 to the coreboot source repository and caused the following changes: Change Log: Revision 3564 improved compilation time, but it also introduced a dependency bug which hit people running parallel make instances. With our current makefile architecture, the "right" fix is impossible. However, we can still kill the race conditions leading to arbitrary compilation failures. That trick depends on the atomicity of the mv command. Extensive comments explain what the workaround does. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Build Log: Compilation of a-trend:atc-6240 has been fixed Compilation of amd:rumba has been fixed Compilation of asi:mb_5blmp has been fixed Compilation of asus:mew-am has been fixed Compilation of bcom:winnetp680 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3663&device=winnetp680&ven… Compilation of jetway:j7f24 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3663&device=j7f24&vendor=j… Compilation of olpc:btest has been fixed Compilation of technologic:ts5300 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3663&device=ts5300&vendor=… Compilation of tyan:s1846 has been fixed Compilation of tyan:s4882 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3663&device=s4882&vendor=t… Compilation of via:epia-cn is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3663&device=epia-cn&vendor… Compilation of via:pc2500e is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3663&device=pc2500e&vendor… If something broke during this checkin please be a pain in hailfinger's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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r3666 - in trunk/coreboot-v2/targets: bcom/winnetp680 jetway/j7f24
by svn＠coreboot.org 17 Oct '08

17 Oct '08

Author: cozzie Date: 2008-10-17 04:47:20 +0200 (Fri, 17 Oct 2008) New Revision: 3666 Added: trunk/coreboot-v2/targets/bcom/winnetp680/Config-abuild.lb trunk/coreboot-v2/targets/jetway/j7f24/Config-abuild.lb Log: Config-abuild.lb's for jetway/j7f24 and bcom/winnetp680, to (finally) get abuild to stop complaining about these boards. They build fine with the default configs on a regular build. Signed-off-by: Corey Osgood <corey.osgood(a)gmail.com> Acked-by: Corey Osgood <corey.osgood(a)gmail.com> Added: trunk/coreboot-v2/targets/bcom/winnetp680/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/bcom/winnetp680/Config-abuild.lb (rev 0) +++ trunk/coreboot-v2/targets/bcom/winnetp680/Config-abuild.lb 2008-10-17 02:47:20 UTC (rev 3666) @@ -0,0 +1,20 @@ +# This will make a target directory of ./VENDOR_MAINBOARD + +target VENDOR_MAINBOARD +mainboard VENDOR/MAINBOARD + +option CC="CROSSCC" +option CROSS_COMPILE="CROSS_PREFIX" +option HOSTCC="CROSS_HOSTCC" + +__COMPRESSION__ + +option ROM_SIZE=512*1024 + +romimage "fallback" + option USE_FALLBACK_IMAGE=1 + option ROM_IMAGE_SIZE=0x20000 + option COREBOOT_EXTRA_VERSION=".0-fallback" + payload __PAYLOAD__ +end +buildrom ./coreboot.rom ROM_SIZE "fallback" Added: trunk/coreboot-v2/targets/jetway/j7f24/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/jetway/j7f24/Config-abuild.lb (rev 0) +++ trunk/coreboot-v2/targets/jetway/j7f24/Config-abuild.lb 2008-10-17 02:47:20 UTC (rev 3666) @@ -0,0 +1,20 @@ +# This will make a target directory of ./VENDOR_MAINBOARD + +target VENDOR_MAINBOARD +mainboard VENDOR/MAINBOARD + +option CC="CROSSCC" +option CROSS_COMPILE="CROSS_PREFIX" +option HOSTCC="CROSS_HOSTCC" + +__COMPRESSION__ + +option ROM_SIZE=512*1024 + +romimage "fallback" + option USE_FALLBACK_IMAGE=1 + option ROM_IMAGE_SIZE=0x20000 + option COREBOOT_EXTRA_VERSION=".0-fallback" + payload __PAYLOAD__ +end +buildrom ./coreboot.rom ROM_SIZE "fallback"

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coreboot October 2008