coreboot October 2008

coreboot@coreboot.org

84 participants
608 discussions

new project.
by James Ortega 18 Oct '08

18 Oct '08

Hello All, Great project guys! I'm new to Coreboot. What I'd like to do is load CoreBoot on to a mainboard that has dual NIC support. Once that is done I'd like to load Linux Firewall off a solid state drive. Requirements. AMD mainboard 2gb ram dual nic (must have) micro atx 2x 2.5 sold state drive. or the new 1.8 inch drive. (raid) This hardware needs to fit into the new Antec Skeleton Mini case. Thanks for your time & attention,

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Invitation for Coreboot to Southern California Linux Expo 7x
by Gareth J. Greenaway 18 Oct '08

18 Oct '08

Greetings, I would like to formerly invite the Coreboot project to attend the 7th Annual Southern California Linux Expo. The show will be held February 20th-22nd, 2009 once again at the Westin LAX in Los Angeles, CA. SCALE 7x will be an excellent venue to showcase all the hard work going into Coreboot. Because Coreboot is an open source project, SCALE will provide a complementary booth on our show floor including all the usual amenities such a 6' table chairs, 500W power drop, one Ethernet drop and 3-5 complementary passes to the show. I am also including our application for dotORG exhibitors as well as our Call For Papers in case anyone is interested in submitting a talk for consideration. Any questions, please do not hesitate to ask. Thanks for your time! Gareth http://scale7x.socallinuxexpo.org/s7x_cfp http://scale7x.socallinuxexpo.org/s7x_call_for_dotOrg_exhibitors -- Gareth J. Greenaway | g(a)socallinuxexpo.org Voice - 877-831-2569 x130 Southern California Linux Expo http://www.socallinuxexpo.org

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[PATCH] flashrom: SiS620 read working
by Urja Rannikko 18 Oct '08

18 Oct '08

Hello, This patch allows the SiS 620 chipset to detect flash roms, and read them fully (256k atleast). The information on what to do was read from alldatasheet.com sis 5595 datasheet and uniflash 1.40 source, note that i looked for only SiS620. Also is a read success (with this patch of course, for this mb) for an ASD AE29F2008, which detects as an Winbond W29C020C, but should work with it's routines. (UNIFLASH.TXT: Supported Flash Chips: "*AE29F2008 = Winbond W29C020(C) | 256KB") log here: [root@localhost flashrom]# ./flashrom -r flashrom_read.bin Calibrating delay loop... OK. No coreboot table found. Found chipset "SiS5595", enabling flash write... OK. Found chip "Winbond W29C020C" (256 KB) at physical address 0xfffc0000. Reading Flash...done [root@localhost flashrom]# diff flashrom_read.bin ../uniflash_bios.bin [root@localhost flashrom]# --- uniflash_bios.bin is a backup read with uniflash + freedos boot disk. -- urjaman

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r3668 - trunk/util/flashrom
by svn＠coreboot.org 18 Oct '08

18 Oct '08

Author: stuge Date: 2008-10-18 15:54:30 +0200 (Sat, 18 Oct 2008) New Revision: 3668 Modified: trunk/util/flashrom/chipset_enable.c Log: flashrom: Allow the SiS 620 chipset to detect and read at least 256kb chips. Based on the 5595 datasheet and uniflash 1.40 sources, only looking for info about SiS620. Signed-off-by: Urja Rannikko <urjaman(a)gmail.com> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/util/flashrom/chipset_enable.c =================================================================== --- trunk/util/flashrom/chipset_enable.c 2008-10-17 14:17:05 UTC (rev 3667) +++ trunk/util/flashrom/chipset_enable.c 2008-10-18 13:54:30 UTC (rev 3668) @@ -540,6 +540,17 @@ return -1; } + /* Extended BIOS enable = 1, Lower BIOS Enable = 1 */ + new = pci_read_byte(dev,0x40); + new &= 0xFB; + new |= 0x3; + pci_write_byte(dev,0x40,new); + newer = pci_read_byte(dev,0x40); + if (newer != new) { + printf("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name); + printf("Stuck at 0x%x\n", newer); + return -1; + } return 0; }

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Funny boot log in Coreinfo
by Myles Watson 18 Oct '08

18 Oct '08

I haven't looked into the cause yet, but the boot log looks a little "funny" in coreinfo. At least it's smiling. Thanks, Myles

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r3667 build service
by coreboot information 18 Oct '08

18 Oct '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "cozzie" checked in revision 3667 to the coreboot source repository and caused the following changes: Change Log: One more little fix for the Jetway J7F[24], option tables can only be built in the normal image, not fallback. Signed-off-by: Corey Osgood <corey.osgood(a)gmail.com> Acked-by: Corey Osgood <corey.osgood(a)gmail.com> Build Log: Compilation of asus:a8n_e has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3667&device=a8n_e&vendor=a… Compilation of jetway:j7f24 has been fixed Compilation of msi:ms7135 has been fixed If something broke during this checkin please be a pain in cozzie's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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VIA C7 CAR
by Carl-Daniel Hailfinger 18 Oct '08

18 Oct '08

Dear Jason, we now have merged the C7 CAR code in coreboot v2 and coreboot v3. Thanks a lot for your contribution! One small piece is missing before everything works: How do we disable CAR again? Do you use the normal x86 CAR disabling routine? Regards, Carl-Daniel

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[PATCH] Multiboot bugfix #2 (coreboot-v3)
by Robert Millan 18 Oct '08

18 Oct '08

Hi, I noticed that free regions provided by search_global_resources() don't have the reserved regions substracted from them. This patch introduces a check to weed them out, splitting when necessary. -- Robert Millan The DRM opt-in fallacy: "Your data belongs to us. We will decide when (and how) you may access your data; but nobody's threatening your freedom: we still allow you to remove your data and not access it at all."

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r937 - coreboot-v3/arch/x86
by svn＠coreboot.org 18 Oct '08

18 Oct '08

Author: jcrouse Date: 2008-10-18 00:49:50 +0200 (Sat, 18 Oct 2008) New Revision: 937 Modified: coreboot-v3/arch/x86/multiboot.c Log: I noticed that free regions provided by search_global_resources() don't have the reserved regions substracted from them. This patch introduces a check to weed them out, splitting when necessary Signed-off-by: Robert Millan <rmh(a)aybabtu.com> Acked-by: Jordan Crouse <jordan.crouse(a)amd.com> Modified: coreboot-v3/arch/x86/multiboot.c =================================================================== --- coreboot-v3/arch/x86/multiboot.c 2008-10-17 22:49:43 UTC (rev 936) +++ coreboot-v3/arch/x86/multiboot.c 2008-10-17 22:49:50 UTC (rev 937) @@ -25,42 +25,83 @@ static struct multiboot_mmap_entry *mb_mem; -static void build_mb_mem_range(void *gp, struct device *dev, struct resource *res) +static struct { + u64 addr; + u64 len; +} reserved_mem[2]; + +static void build_mb_mem_range_nooverlap(u64 addr, u64 len) { - mb_mem->addr = res->base; - mb_mem->len = res->size; + int i; + for (i = 0; i < sizeof(reserved_mem) / sizeof(reserved_mem[0]); i++) { + /* free region fully contained in reserved region, abort */ + if (addr >= reserved_mem[i].addr && addr + len <= reserved_mem[i].addr + reserved_mem[i].len) + return; + /* reserved region splits free region */ + if (addr < reserved_mem[i].addr && addr + len > reserved_mem[i].addr + reserved_mem[i].len) { + build_mb_mem_range_nooverlap(addr, reserved_mem[i].addr - addr); + build_mb_mem_range_nooverlap(reserved_mem[i].addr + reserved_mem[i].len, (addr + len) - (reserved_mem[i].addr + reserved_mem[i].len)); + return; + } + /* left overlap */ + if (addr < reserved_mem[i].addr + reserved_mem[i].len && addr + len > reserved_mem[i].addr + reserved_mem[i].len) { + len += addr; + addr = reserved_mem[i].addr + reserved_mem[i].len; + len -= addr; + /* len += addr - old_addr */ + continue; + } + /* right overlap */ + if (addr < reserved_mem[i].addr && addr + len > reserved_mem[i].addr) { + len = reserved_mem[i].addr - addr; + continue; + } + /* none of the above, just add it */ + } + + mb_mem->addr = addr; + mb_mem->len = len; mb_mem->type = 1; mb_mem->size = sizeof(*mb_mem) - sizeof(mb_mem->size); mb_mem++; } +static void build_mb_mem_range(void *gp, struct device *dev, struct resource *res) +{ + build_mb_mem_range_nooverlap(res->base, res->size); +} + unsigned long write_multiboot_info( unsigned long low_table_start, unsigned long low_table_end, unsigned long rom_table_start, unsigned long rom_table_end) { - struct multiboot_info *mbi = rom_table_end; + struct multiboot_info *mbi; + int i; + + mbi = rom_table_end; memset(mbi, 0, sizeof(*mbi)); rom_table_end += sizeof(*mbi); mbi->mmap_addr = (u32) rom_table_end; mb_mem = rom_table_end; + /* reserved regions */ + reserved_mem[0].addr = low_table_start; + reserved_mem[0].len = low_table_end - low_table_start; + reserved_mem[1].addr = rom_table_start; + reserved_mem[1].len = rom_table_end - rom_table_start; + for (i = 0; i < sizeof(reserved_mem) / sizeof(reserved_mem[0]); i++) { + mb_mem->addr = reserved_mem[i].addr; + mb_mem->len = reserved_mem[i].len; + mb_mem->type = 2; + mb_mem->size = sizeof(*mb_mem) - sizeof(mb_mem->size); + mb_mem++; + } + /* free regions */ search_global_resources( IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, build_mb_mem_range, NULL); - /* reserved regions */ - mb_mem->addr = low_table_start; - mb_mem->len = low_table_end - low_table_start; - mb_mem->type = 2; - mb_mem->size = sizeof(*mb_mem) - sizeof(mb_mem->size); - mb_mem++; - mb_mem->addr = rom_table_start; - mb_mem->len = rom_table_end - rom_table_start; - mb_mem->type = 2; - mb_mem->size = sizeof(*mb_mem) - sizeof(mb_mem->size); - mb_mem++; - mbi->mmap_length = ((u32) mb_mem) - mbi->mmap_addr; mbi->flags |= MB_INFO_MEM_MAP;

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r936 - in coreboot-v3: arch/x86 include lib
by svn＠coreboot.org 18 Oct '08

18 Oct '08

Author: jcrouse Date: 2008-10-18 00:49:43 +0200 (Sat, 18 Oct 2008) New Revision: 936 Modified: coreboot-v3/arch/x86/archtables.c coreboot-v3/arch/x86/stage1.c coreboot-v3/include/tables.h coreboot-v3/lib/stage2.c coreboot-v3/lib/tables.c Log: the multiboot map is generated too early in arch_write_tables(), before a number of routines that write/reserve stuff are executed (in my test this only affects the 0x0-0x500 region but I notice there's other stuff too). Attached patch moves it down, solving the problem. Because stage1 can no longer assume the MBI is at 0xf0000, I had to add a return path for stage2 to give it a pointer, using its exit status value. Signed-off-by: Robert Millan <rmh(a)aybabtu.com> Acked-by: Jordan Crouse <jordan.crouse(a)amd.com> Modified: coreboot-v3/arch/x86/archtables.c =================================================================== --- coreboot-v3/arch/x86/archtables.c 2008-10-16 17:50:08 UTC (rev 935) +++ coreboot-v3/arch/x86/archtables.c 2008-10-17 22:49:43 UTC (rev 936) @@ -59,7 +59,7 @@ printk(BIOS_DEBUG,"OK\n"); } #endif -struct lb_memory *arch_write_tables(void) +void *arch_write_tables(void) { #if 0 #if HAVE_MP_TABLE==1 @@ -69,6 +69,8 @@ unsigned long low_table_start, low_table_end; unsigned long rom_table_start, rom_table_end; + void *mbi; + rom_table_start = 0xf0000; rom_table_end = 0xf0000; /* Start low addr at 16 bytes instead of 0 because of a buglet @@ -79,14 +81,6 @@ post_code(POST_STAGE2_ARCH_WRITE_TABLES_ENTER); - /* The Multiboot information structure must be in 0xf0000 */ - rom_table_end = write_multiboot_info( - low_table_start, low_table_end, - rom_table_start, rom_table_end); - - /* FIXME: is this alignment needed for PIRQ table? */ - rom_table_end = (rom_table_end + 1023) & ~1023; - /* This table must be betweeen 0xf0000 & 0x100000 */ /* we need to make a decision: create empty functions * in .h files if the cpp variable is undefined, or #ifdef? @@ -149,10 +143,17 @@ move_gdt(low_table_end); low_table_end += &gdt_end - &gdt; #endif + + /* The Multiboot information structure */ + mbi = rom_table_end; + rom_table_end = write_multiboot_info( + low_table_start, low_table_end, + rom_table_start, rom_table_end); + /* The coreboot table must be in 0-4K or 960K-1M */ write_coreboot_table( low_table_start, low_table_end, rom_table_start, rom_table_end); - return get_lb_mem(); + return mbi; } Modified: coreboot-v3/arch/x86/stage1.c =================================================================== --- coreboot-v3/arch/x86/stage1.c 2008-10-16 17:50:08 UTC (rev 935) +++ coreboot-v3/arch/x86/stage1.c 2008-10-17 22:49:43 UTC (rev 936) @@ -147,10 +147,10 @@ #endif /* CONFIG_PAYLOAD_ELF_LOADER */ -static int run_address_multiboot(void *f) +static int run_address_multiboot(void *f, struct multiboot_info *mbi) { int ret, dummy; - __asm__ __volatile__ ("call *%4" : "=a" (ret), "=c" (dummy) : "a" (MB_MAGIC2), "b" (0xf0000), "c" (f) : "edx", "memory"); + __asm__ __volatile__ ("call *%4" : "=a" (ret), "=c" (dummy) : "a" (MB_MAGIC2), "b" (mbi), "c" (f) : "edx", "memory"); return ret; } @@ -281,6 +281,8 @@ void *entry; int ret; struct mem_file archive; + struct multiboot_info *mbi; + #ifdef CONFIG_PAYLOAD_ELF_LOADER struct mem_file result; int elfboot_mem(struct lb_memory *mem, void *where, int size); @@ -303,8 +305,8 @@ entry = load_file_segments(&archive, "normal/stage2"); if (entry == (void *)-1) die("FATAL: Failed loading stage2."); - ret = run_address(entry); - if (ret) + mbi = run_address(entry); + if (! mbi) die("FATAL: Failed in stage2 code."); printk(BIOS_DEBUG, "Stage2 code done.\n"); @@ -319,7 +321,7 @@ if (entry != (void*)-1) { /* Final coreboot call before handing off to the payload. */ mainboard_pre_payload(); - run_address_multiboot(entry); + run_address_multiboot(entry, mbi); } else { die("FATAL: No usable payload found.\n"); } Modified: coreboot-v3/include/tables.h =================================================================== --- coreboot-v3/include/tables.h 2008-10-16 17:50:08 UTC (rev 935) +++ coreboot-v3/include/tables.h 2008-10-17 22:49:43 UTC (rev 936) @@ -30,7 +30,7 @@ * defined here. */ -struct lb_memory *write_tables(void); +void *write_tables(void); /* The coreboot table information is for conveying information * from the firmware to the loaded OS image. Primarily this @@ -270,7 +270,7 @@ #define CHECKSUM_PCBIOS 1 }; -struct lb_memory *arch_write_tables(void); +void *arch_write_tables(void); unsigned long write_coreboot_table( unsigned long low_table_start, unsigned long low_table_end, unsigned long rom_table_start, unsigned long rom_table_end); Modified: coreboot-v3/lib/stage2.c =================================================================== --- coreboot-v3/lib/stage2.c 2008-10-16 17:50:08 UTC (rev 935) +++ coreboot-v3/lib/stage2.c 2008-10-17 22:49:43 UTC (rev 936) @@ -41,8 +41,10 @@ * TODO: * - Check whether this documentation is still correct. Improve it. */ -int stage2(void) +void *stage2(void) { + void *mbi; + /* TODO: Add comment. */ void show_all_devs(void); @@ -88,9 +90,9 @@ /* TODO: Add comment. */ post_code(POST_STAGE2_WRITE_TABLES); - write_tables(); + mbi = write_tables(); show_all_devs(); - return 0; + return mbi; } EXPORT_SYMBOL(stage2); Modified: coreboot-v3/lib/tables.c =================================================================== --- coreboot-v3/lib/tables.c 2008-10-16 17:50:08 UTC (rev 935) +++ coreboot-v3/lib/tables.c 2008-10-17 22:49:43 UTC (rev 936) @@ -29,7 +29,7 @@ // #include <cpu.h> #include <tables.h> -struct lb_memory *write_tables(void) +void *write_tables(void) { return arch_write_tables(); }

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coreboot October 2008