coreboot October 2008

coreboot@coreboot.org

84 participants
608 discussions

phase4_enable_disable
by ron minnich 15 Oct '08

15 Oct '08

Here are all the usages we have at present: agp3dev_enable, amd8111_enable, amd8111_usb2_enable, f71805f_pnp_enable_resources, ioapic_enable, it8712f_pnp_enable_resources, it8716f_pnp_enable_disable, rs690_enable, sb600_enable, setup_onboard, w83627hf_pnp_enable_resources, For each one we need this answer: 1. Is this function needed to enable proper scanning of the device, i.e. can we discover the device and its functions (if any) without calling this function. That determines if we need to call this function in phase3_enable_scan 2. Is this function needed to enable reading resources on this device, or any child devices? If we don't call this function, can we still get (e.g.) BAR values? That determines if we need to call this function in phase4_enable_disable 3. Is this function needed to enable the device? That determines if we call this function in phase5 So, let's try to work this out. I also want to rename these to some extent. E.g. w83627hf_pnp_enable_resources: is it enabling *resources* -- where a resource is an io or memory address range -- or *devices* -- where a device is a serial or keyboard or whatever. This confusion is in v2, I'd like not to have it in v3. ron

1 0

[PATCH] v3: determine global variable location
by Carl-Daniel Hailfinger 15 Oct '08

15 Oct '08

We need a way to find out where our stack and our global variables are at any given moment. This is a first generic try, but doing this in a processor-specific way would be more appropriate. Please note that this needs a new #define or Kconfig variable somewhere: CONFIG_RAM_STACK_LOCATION. As an alternative, we could declare the top of memory as optimal stack location. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: corebootv3-globalvariablelocation/arch/x86/stage1.c =================================================================== --- corebootv3-globalvariablelocation/arch/x86/stage1.c (Revision 925) +++ corebootv3-globalvariablelocation/arch/x86/stage1.c (Arbeitskopie) @@ -70,11 +70,22 @@ /* * The name is slightly misleading because this is the initial stack pointer, * not the address of the first element on the stack. + * NOTE: This function is very processor specific. */ void *bottom_of_stack(void) { - /* -4 because CONFIG_CARBASE + CONFIG_CARSIZE - 4 is initial %esp */ - return (void *)(CONFIG_CARBASE + CONFIG_CARSIZE - 4); + u32 onstack = (u32)&onstack; + + /* Check whether the variable onstack is inside the CAR area. + * If it is, assume we're still in CAR or the stack has not moved. + * Otherwise return initial %esp for the RAM-based stack location. + */ + if ((onstack >= CONFIG_CARBASE) && + (onstack < CONFIG_CARBASE + CONFIG_CARSIZE - 4)) + /* CONFIG_CARBASE + CONFIG_CARSIZE - 4 is initial %esp */ + return (void *)(CONFIG_CARBASE + CONFIG_CARSIZE - 4); + /* OK, so current %esp is not inside the CAR area. */ + return (void *) CONFIG_RAM_STACK_LOCATION; } struct global_vars *global_vars(void) -- http://www.hailfinger.org/

2 8

r933 - in coreboot-v3: arch/x86 include/arch/x86
by svn＠coreboot.org 15 Oct '08

15 Oct '08

Author: hailfinger Date: 2008-10-16 05:03:33 +0200 (Thu, 16 Oct 2008) New Revision: 933 Modified: coreboot-v3/arch/x86/stage1.c coreboot-v3/include/arch/x86/cpu.h Log: We need a way to find out where our stack and our global variables are at any given moment. The code is generic enough to handle this in a processor-specific way behind the scenes if needed. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/arch/x86/stage1.c =================================================================== --- coreboot-v3/arch/x86/stage1.c 2008-10-16 03:00:28 UTC (rev 932) +++ coreboot-v3/arch/x86/stage1.c 2008-10-16 03:03:33 UTC (rev 933) @@ -71,11 +71,21 @@ /* * The name is slightly misleading because this is the initial stack pointer, * not the address of the first element on the stack. + * NOTE: This function is very processor specific. */ void *bottom_of_stack(void) { - /* -4 because CONFIG_CARBASE + CONFIG_CARSIZE - 4 is initial %esp */ - return (void *)(CONFIG_CARBASE + CONFIG_CARSIZE - 4); + u32 onstack = (u32)&onstack; + + /* Check whether the variable onstack is inside the CAR stack area. + * If it is, assume we're still in CAR or the stack has not moved. + * Otherwise return initial %esp for the RAM-based stack location. + */ + if ((onstack >= CAR_STACK_BASE - CAR_STACK_SIZE) && + (onstack < CAR_STACK_BASE)) + return (void *)CAR_STACK_BASE; + /* OK, so current %esp is not inside the CAR stack area. */ + return (void *)RAM_STACK_BASE; } struct global_vars *global_vars(void) Modified: coreboot-v3/include/arch/x86/cpu.h =================================================================== --- coreboot-v3/include/arch/x86/cpu.h 2008-10-16 03:00:28 UTC (rev 932) +++ coreboot-v3/include/arch/x86/cpu.h 2008-10-16 03:03:33 UTC (rev 933) @@ -266,11 +266,17 @@ struct global_vars * global_vars(void); EXPORT_SYMBOL(global_vars); +#define CAR_STACK_BASE (CONFIG_CARBASE + CONFIG_CARSIZE - 4) +#define RAM_STACK_BASE 0x88ffc + #ifdef CONFIG_CONSOLE_BUFFER #define PRINTK_BUF_SIZE_CAR (CONFIG_CARSIZE / 2) #define PRINTK_BUF_ADDR_CAR CONFIG_CARBASE #define PRINTK_BUF_SIZE_RAM 65536 #define PRINTK_BUF_ADDR_RAM 0x90000 +#define CAR_STACK_SIZE ((CONFIG_CARSIZE / 2) - 4) +#else +#define CAR_STACK_SIZE (CONFIG_CARSIZE - 4) #endif /* resource maps. These started out as special for the K8 but now have more general usage */

1 0

[RFC] v3: Stack switching abstraction for C7 and later Intel processors
by Carl-Daniel Hailfinger 15 Oct '08

15 Oct '08

Right now we face the problem that we can't support processors which have a CAR area outside the usual RAM area. For those processors, we have to implement a stack copying and switching mechanism. Since gcc can't be told that the stack just moved, split stage1_main() into stage1_main() and stage1_late(). stage1_main() is still the entry point and will handle everything up to the point where we want to disable CAR. Switching the stack, disabling CAR and handling other tasks related to the stack switch (printk buffer move) is all wrapped in the switch_stack() function. switch_stack() will then call stage1_late() which is the second part of the old stage1_main(). Test booted on qemu only. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: corebootv3-stackrebuild/arch/x86/stage1.c =================================================================== --- corebootv3-stackrebuild/arch/x86/stage1.c (Revision 925) +++ corebootv3-stackrebuild/arch/x86/stage1.c (Arbeitskopie) @@ -143,6 +143,9 @@ return ret; } +void switch_stack(void); +void __attribute__((stdcall)) stage1_late(void); + /** * This function is called from assembler code with its argument on the * stack. Force the compiler to generate always correct code for this case. @@ -159,24 +162,8 @@ struct global_vars globvars; int ret; struct mem_file archive; - void *entry; struct node_core_id me; -#ifdef CONFIG_PAYLOAD_ELF_LOADER - struct mem_file result; - int elfboot_mem(struct lb_memory *mem, void *where, int size); - /* Why can't we statically init this hack? */ - unsigned char faker[64]; - struct lb_memory *mem = (struct lb_memory*) faker; - - mem->tag = LB_TAG_MEMORY; - mem->size = 28; - mem->map[0].start.lo = mem->map[0].start.hi = 0; - mem->map[0].size.lo = (32*1024*1024); - mem->map[0].size.hi = 0; - mem->map[0].type = LB_MEM_RAM; -#endif /* CONFIG_PAYLOAD_ELF_LOADER */ - post_code(POST_STAGE1_MAIN); /* before we do anything, we want to stop if we do not run @@ -234,6 +221,25 @@ printk(BIOS_DEBUG, "Done RAM init code\n"); + /* Switch the stack location from CAR to RAM, rebuild the stack, + * disable CAR and continue at stage1_late(). This is all wrapped in + * switch_stack to make the code easier to follow. + */ + switch_stack(); +} + +/** + * This function is called to take care of switching and rebuilding the stack + * so that we can cope with processors which don't support a CAR area at low + * addresses where CAR could be copied to RAM without problems. + * After the stack has been rebuilt, we switch the stack pointer to the new + * location, move the printk buffer and cotinue at stage1_late(). + * + * NOTE: switch_stack may need to be reimplemented in processor-specific asm. + * TODO: Reevaluate whether printk_buffer_move should come before disable_car() + */ +void switch_stack() +{ /* Turn off Cache-As-Ram */ disable_car(); @@ -241,7 +247,37 @@ /* Move the printk buffer to PRINTK_BUF_ADDR_RAM */ printk_buffer_move((void *)PRINTK_BUF_ADDR_RAM, PRINTK_BUF_SIZE_RAM); #endif + stage1_late(); +} +/** + * This function is the second part of stage1_main() after switching the stack + * and disabling CAR. + */ +void __attribute__((stdcall)) stage1_late() +{ + void *entry; + int ret; + struct mem_file archive; +#ifdef CONFIG_PAYLOAD_ELF_LOADER + struct mem_file result; + int elfboot_mem(struct lb_memory *mem, void *where, int size); + + /* Why can't we statically init this hack? */ + unsigned char faker[64]; + struct lb_memory *mem = (struct lb_memory*) faker; + + mem->tag = LB_TAG_MEMORY; + mem->size = 28; + mem->map[0].start.lo = mem->map[0].start.hi = 0; + mem->map[0].size.lo = (32*1024*1024); + mem->map[0].size.hi = 0; + mem->map[0].type = LB_MEM_RAM; +#endif /* CONFIG_PAYLOAD_ELF_LOADER */ + + // location and size of image. + init_archive(&archive); + entry = load_file_segments(&archive, "normal/stage2"); if (entry == (void *)-1) die("FATAL: Failed loading stage2."); -- http://www.hailfinger.org/

5 28

r932 - in coreboot-v3: arch/x86 arch/x86/amd arch/x86/amd/k8 arch/x86/geodelx arch/x86/i586 arch/x86/via doc/design include/arch/x86 mainboard/emulation/qemu-x86
by svn＠coreboot.org 15 Oct '08

15 Oct '08

Author: hailfinger Date: 2008-10-16 05:00:28 +0200 (Thu, 16 Oct 2008) New Revision: 932 Added: coreboot-v3/include/arch/x86/stage1.h Modified: coreboot-v3/arch/x86/amd/k8/stage1.c coreboot-v3/arch/x86/amd/stage0.S coreboot-v3/arch/x86/geodelx/stage0.S coreboot-v3/arch/x86/geodelx/stage1.c coreboot-v3/arch/x86/i586/stage0.S coreboot-v3/arch/x86/stage1.c coreboot-v3/arch/x86/via/stage0.S coreboot-v3/doc/design/newboot.lyx coreboot-v3/mainboard/emulation/qemu-x86/stage1.c Log: Right now we face the problem that we can't support processors which have a CAR area outside the usual RAM area. For those processors, we have to implement a stack copying and switching mechanism. Since gcc can't be told that the stack just moved, split stage1_main() into stage1_phase1() and stage1_phase2() and stage1_phase3(). stage1_phase1() is the new entry point in stage1 and will handle everything up to the point where we want to disable CAR. Switching the stack, disabling CAR and handling other tasks related to the stack switch (printk buffer move) is all wrapped in the stage1_phase2() function. stage1_phase2() calls disable_car() which then calls stage1_phase3(). stage1_phase3() is the former second half of stage1_main(). Notes about this patch: - Code flow is almost unchanged for Qemu, K8 and Geode. No extensive new testing required. - We can support stack-keeping and stack-relocating architectures at the same time, so C7 is definitely supportable - The comment in stage1_phase2 says "some of this is not yet done". That refers to the nonexisting code for stack switching on C7. - "Minimal changes, maximum benefit". Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/arch/x86/amd/k8/stage1.c =================================================================== --- coreboot-v3/arch/x86/amd/k8/stage1.c 2008-10-15 17:46:52 UTC (rev 931) +++ coreboot-v3/arch/x86/amd/k8/stage1.c 2008-10-16 03:00:28 UTC (rev 932) @@ -26,6 +26,7 @@ #include <macros.h> #include <cpu.h> #include <amd/k8/k8.h> +#include <stage1.h> /** * Set the MTRR for initial ram access. @@ -73,4 +74,5 @@ /* we're now running in ram. Although this will be called again, it does no harm to call it here. */ set_init_ram_access(); banner(BIOS_DEBUG, "disable_car: done"); + stage1_phase3(); } Modified: coreboot-v3/arch/x86/amd/stage0.S =================================================================== --- coreboot-v3/arch/x86/amd/stage0.S 2008-10-15 17:46:52 UTC (rev 931) +++ coreboot-v3/arch/x86/amd/stage0.S 2008-10-16 03:00:28 UTC (rev 932) @@ -341,7 +341,7 @@ pushl %ebx /* First parameter: bist */ pushl %eax - call stage1_main + call stage1_phase1 /* We will not go back. */ movb $0xAF, %al /* Should never see this postcode */ Modified: coreboot-v3/arch/x86/geodelx/stage0.S =================================================================== --- coreboot-v3/arch/x86/geodelx/stage0.S 2008-10-15 17:46:52 UTC (rev 931) +++ coreboot-v3/arch/x86/geodelx/stage0.S 2008-10-16 03:00:28 UTC (rev 932) @@ -271,7 +271,7 @@ pushl $0 /* First parameter: bist */ pushl %eax - call stage1_main + call stage1_phase1 /* We will not go back. */ #include "../stage0_common.S" Modified: coreboot-v3/arch/x86/geodelx/stage1.c =================================================================== --- coreboot-v3/arch/x86/geodelx/stage1.c 2008-10-15 17:46:52 UTC (rev 931) +++ coreboot-v3/arch/x86/geodelx/stage1.c 2008-10-16 03:00:28 UTC (rev 932) @@ -24,6 +24,7 @@ #include <amd_geodelx.h> #include <console.h> #include <msr.h> +#include <stage1.h> static const struct msrinit msr_table[] = { /* Setup access to cache under 1MB. */ @@ -93,4 +94,5 @@ banner(BIOS_DEBUG, "Disable_car: done wbinvd"); northbridge_init_early(); banner(BIOS_DEBUG, "disable_car: done"); + stage1_phase3(); } Modified: coreboot-v3/arch/x86/i586/stage0.S =================================================================== --- coreboot-v3/arch/x86/i586/stage0.S 2008-10-15 17:46:52 UTC (rev 931) +++ coreboot-v3/arch/x86/i586/stage0.S 2008-10-16 03:00:28 UTC (rev 932) @@ -339,7 +339,7 @@ pushl $0 /* First parameter: bist */ pushl %eax - call stage1_main + call stage1_phase1 /* We will not go back. */ fixed_mtrr_msr: Modified: coreboot-v3/arch/x86/stage1.c =================================================================== --- coreboot-v3/arch/x86/stage1.c 2008-10-15 17:46:52 UTC (rev 931) +++ coreboot-v3/arch/x86/stage1.c 2008-10-16 03:00:28 UTC (rev 932) @@ -30,6 +30,7 @@ #include <mc146818rtc.h> #include <cpu.h> #include <multiboot.h> +#include <stage1.h> #ifdef CONFIG_PAYLOAD_ELF_LOADER /* ah, well, what a mess! This is a hard code. FIX ME but how? @@ -154,29 +155,13 @@ * that we are restarting after some sort of reconfiguration. Note that we could use it on geode but * do not at present. */ -void __attribute__((stdcall)) stage1_main(u32 bist, u32 init_detected) +void __attribute__((stdcall)) stage1_phase1(u32 bist, u32 init_detected) { struct global_vars globvars; int ret; struct mem_file archive; - void *entry; struct node_core_id me; -#ifdef CONFIG_PAYLOAD_ELF_LOADER - struct mem_file result; - int elfboot_mem(struct lb_memory *mem, void *where, int size); - /* Why can't we statically init this hack? */ - unsigned char faker[64]; - struct lb_memory *mem = (struct lb_memory*) faker; - - mem->tag = LB_TAG_MEMORY; - mem->size = 28; - mem->map[0].start.lo = mem->map[0].start.hi = 0; - mem->map[0].size.lo = (32*1024*1024); - mem->map[0].size.hi = 0; - mem->map[0].type = LB_MEM_RAM; -#endif /* CONFIG_PAYLOAD_ELF_LOADER */ - post_code(POST_STAGE1_MAIN); /* before we do anything, we want to stop if we do not run @@ -234,14 +219,77 @@ printk(BIOS_DEBUG, "Done RAM init code\n"); - /* Turn off Cache-As-Ram */ - disable_car(); + /* Switch the stack location from CAR to RAM, rebuild the stack, + * disable CAR and continue at stage1_phase3(). This is all wrapped in + * stage1_phase2() to make the code easier to follow. + * We will NEVER return. + */ + stage1_phase2(); + /* If we reach this point, something went terribly wrong. */ + die("The world is broken.\n"); +} + +/** + * This function is called to take care of switching and rebuilding the stack + * so that we can cope with processors which don't support a CAR area at low + * addresses where CAR could be copied to RAM without problems. + * This function handles everything related to switching off CAR and moving + * important data from CAR to RAM. + * 1. Perform all work which can be done while CAR and RAM are both active. + * That's mainly moving the printk buffer around. + * 2a. Optionally back up the new stack location (desirable for S3). + * 2b. Optionally rebuild the stack at another location. + * 2c. Switch stack pointer to the new stack if the stack was rebuilt. + * 3. Disable CAR. + * 4. Call or jump to stage1_phase3. + * Steps 2a-4 have to be done in asm. That's what the oddly named disable_car() + * function does. + * + * TODO: Some parts of the list above are not yet done, so the code will not + * yet work on C7. + */ +void stage1_phase2() +{ #ifdef CONFIG_CONSOLE_BUFFER /* Move the printk buffer to PRINTK_BUF_ADDR_RAM */ printk_buffer_move((void *)PRINTK_BUF_ADDR_RAM, PRINTK_BUF_SIZE_RAM); #endif + /* Turn off Cache-As-Ram */ + disable_car(); + /* If we reach this point, something went terribly wrong. */ + die("The world is broken.\n"); +} + +/** + * This function is the second part of the former stage1_main() after + * switching the stack and disabling CAR. + */ +void __attribute__((stdcall)) stage1_phase3() +{ + void *entry; + int ret; + struct mem_file archive; +#ifdef CONFIG_PAYLOAD_ELF_LOADER + struct mem_file result; + int elfboot_mem(struct lb_memory *mem, void *where, int size); + + /* Why can't we statically init this hack? */ + unsigned char faker[64]; + struct lb_memory *mem = (struct lb_memory*) faker; + + mem->tag = LB_TAG_MEMORY; + mem->size = 28; + mem->map[0].start.lo = mem->map[0].start.hi = 0; + mem->map[0].size.lo = (32*1024*1024); + mem->map[0].size.hi = 0; + mem->map[0].type = LB_MEM_RAM; +#endif /* CONFIG_PAYLOAD_ELF_LOADER */ + + // location and size of image. + init_archive(&archive); + entry = load_file_segments(&archive, "normal/stage2"); if (entry == (void *)-1) die("FATAL: Failed loading stage2."); Modified: coreboot-v3/arch/x86/via/stage0.S =================================================================== --- coreboot-v3/arch/x86/via/stage0.S 2008-10-15 17:46:52 UTC (rev 931) +++ coreboot-v3/arch/x86/via/stage0.S 2008-10-16 03:00:28 UTC (rev 932) @@ -189,7 +189,7 @@ pushl $0 /* First parameter: bist */ pushl %eax - call stage1_main + call stage1_phase1 /* We will not go back. */ fixed_mtrr_msr: Modified: coreboot-v3/doc/design/newboot.lyx =================================================================== --- coreboot-v3/doc/design/newboot.lyx 2008-10-15 17:46:52 UTC (rev 931) +++ coreboot-v3/doc/design/newboot.lyx 2008-10-16 03:00:28 UTC (rev 932) @@ -759,7 +759,7 @@ \end_layout \begin_layout Standard -Initial entry point for stage 1 is arch/{architecture}/stage1.c:stage1_main(). +Initial entry point for stage 1 is arch/{architecture}/stage1.c:stage1_phase1(). \end_layout \begin_layout Standard Added: coreboot-v3/include/arch/x86/stage1.h =================================================================== --- coreboot-v3/include/arch/x86/stage1.h (rev 0) +++ coreboot-v3/include/arch/x86/stage1.h 2008-10-16 03:00:28 UTC (rev 932) @@ -0,0 +1,2 @@ +void stage1_phase2(void); +void __attribute__((stdcall)) stage1_phase3(void); Modified: coreboot-v3/mainboard/emulation/qemu-x86/stage1.c =================================================================== --- coreboot-v3/mainboard/emulation/qemu-x86/stage1.c 2008-10-15 17:46:52 UTC (rev 931) +++ coreboot-v3/mainboard/emulation/qemu-x86/stage1.c 2008-10-16 03:00:28 UTC (rev 932) @@ -17,6 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <stage1.h> + /* printk() will not yet output anything. */ /** @@ -34,6 +36,7 @@ void disable_car(void) { + stage1_phase3(); }

1 0

Serengeti vga hang
by Myles Watson 15 Oct '08

15 Oct '08

Here's the latest log. It hangs in the emulator. I've tried both emulators, but to no avail. Thanks, Myles

3 15

[PATCH] v3: CN700 initram support
by Corey Osgood 15 Oct '08

15 Oct '08

See attached. Thanks Carl-Daniel for the explanation on floats in CAR, hope you don't mind that I've quoted you ;) -Corey

2 7

Re: [coreboot] alix.2c3 stops at mainboard_pre_payload: done
by Roman Yeryomin 15 Oct '08

15 Oct '08

On Sun, Oct 12, 2008 at 3:16 AM, Roman Yeryomin <leroi.lists(a)gmail.com> wrote: > On Sat, Oct 11, 2008 at 8:33 PM, ron minnich <rminnich(a)gmail.com> wrote: >>> >>> while trying to resolve this problem I've noticed following: >>> >>> on system with native bios (tinybios): >>> cat /proc/tty/driver/serial >>> serinfo:1.0 driver revision: >>> 0: uart:16550A port:000003F8 irq:4 tx:945 rx:15 RTS|CTS|DTR|DSR|CD >>> 1: uart:16550A port:000002F8 irq:3 tx:0 rx:0 CTS|DSR|CD >>> >>> but on system with coreboot: >>> cat /proc/tty/driver/serial >>> serinfo:1.0 driver revision: >>> 0: uart:NS16550A port:000003F8 irq:4 tx:0 rx:0 RTS|DTR >>> 1: uart:unknown port:000002F8 irq:3 >>> >> >> OK, this is kind of the problem I remember. If you have time go into >> the kernel, IIRC, there is a test for some modem signal and the device >> is not available otherwise. I am sorry to be so fuzzy but this was >> seven years ago. It was a weird problem. > > you think this is kernel problem? > >> It seems whatever you have on that port is not asserting DTR, which is >> also odd. Is there a loopback control in this part that routes DSR >> back to DTR? > > Well, according to datasheet there is loopback control in cs5536 uart, > but I don't think the problem is there. > I've asked Pascal Dornier (pcengines) how he sets up uart in his bios > but didn't receive an answer yet. > I still think the problem is in coreboot (or libpayload)... Pascal answered me: After init -> changes to Linux driver, or does it still use Int 10 + Int 16 ? My BIOS does a redirect of these BIOS interrupts to the serial console. Roman

3 3

Patch: New board: Bcom WinNET P680
by Alex Mauer 15 Oct '08

15 Oct '08

Attached please find a patch which adds support for the Bcom P680 mainboard. This board is a thin client system, used in (at least) the Neoware e140 thin client. It's essentially the same as the epia-cn, but with a Winbond W83697HG Super-IO. Signed-off-by: Alex Mauer <hawke(a)hawkesnest.net> This patch is based on an svn cp of the jetway j7f24 target/mainboard, so it doesn't show the entire add for those files.

4 5

Simple logic fix patch
by Myles Watson 15 Oct '08

15 Oct '08

Because the enable bit was masked off, checking for 0xffffffff didn't work. This patch changes the place where the bit is masked. The other way to fix it would be to check for 0xfffffffe. V2 doesn't seem to have the problem. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

3 2

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coreboot October 2008