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[LinuxBIOS] r2720 - in trunk/LinuxBIOSv2/src/northbridge/intel: . i82810
by svn＠openbios.org 14 Jun '07

14 Jun '07

Author: uwe Date: 2007-06-14 14:02:38 +0200 (Thu, 14 Jun 2007) New Revision: 2720 Added: trunk/LinuxBIOSv2/src/northbridge/intel/i82810/ trunk/LinuxBIOSv2/src/northbridge/intel/i82810/Config.lb trunk/LinuxBIOSv2/src/northbridge/intel/i82810/chip.h trunk/LinuxBIOSv2/src/northbridge/intel/i82810/debug.c trunk/LinuxBIOSv2/src/northbridge/intel/i82810/i82810.h trunk/LinuxBIOSv2/src/northbridge/intel/i82810/northbridge.c trunk/LinuxBIOSv2/src/northbridge/intel/i82810/northbridge.h trunk/LinuxBIOSv2/src/northbridge/intel/i82810/raminit.c trunk/LinuxBIOSv2/src/northbridge/intel/i82810/raminit.h Log: Add initial support for the Intel 82810 northbridge. Signed-off-by: Corey Osgood <corey.osgood(a)gmail.com> Acked-by: Joseph Smith <joe(a)smittys.pointclark.net> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Added: trunk/LinuxBIOSv2/src/northbridge/intel/i82810/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/intel/i82810/Config.lb (rev 0) +++ trunk/LinuxBIOSv2/src/northbridge/intel/i82810/Config.lb 2007-06-14 12:02:38 UTC (rev 2720) @@ -0,0 +1,22 @@ +## +## This file is part of the LinuxBIOS project. +## +## Copyright (C) 2007 Corey Osgood <corey(a)slightlyhackish.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config chip.h +object northbridge.o Added: trunk/LinuxBIOSv2/src/northbridge/intel/i82810/chip.h =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/intel/i82810/chip.h (rev 0) +++ trunk/LinuxBIOSv2/src/northbridge/intel/i82810/chip.h 2007-06-14 12:02:38 UTC (rev 2720) @@ -0,0 +1,25 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Corey Osgood <corey(a)slightlyhackish.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +struct northbridge_intel_i82810_config +{ +}; + +extern struct chip_operations northbridge_intel_i82810_ops; Added: trunk/LinuxBIOSv2/src/northbridge/intel/i82810/debug.c =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/intel/i82810/debug.c (rev 0) +++ trunk/LinuxBIOSv2/src/northbridge/intel/i82810/debug.c 2007-06-14 12:02:38 UTC (rev 2720) @@ -0,0 +1,35 @@ + +static void dump_spd_registers(const struct mem_controller *ctrl) +{ + int i; + print_debug("\r\n"); + for(i = 0; i < 4; i++) { + unsigned device; + device = ctrl->channel0[i]; + if (device) { + int j; + print_debug("dimm: "); + print_debug_hex8(i); + print_debug(".0: "); + print_debug_hex8(device); + for(j = 0; j < 256; j++) { + int status; + unsigned char byte; + if ((j & 0xf) == 0) { + print_debug("\r\n"); + print_debug_hex8(j); + print_debug(": "); + } + status = smbus_read_byte(device, j); + if (status < 0) { + print_debug("bad device\r\n"); + break; + } + byte = status & 0xff; + print_debug_hex8(byte); + print_debug_char(' '); + } + print_debug("\r\n"); + } + } +} Added: trunk/LinuxBIOSv2/src/northbridge/intel/i82810/i82810.h =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/intel/i82810/i82810.h (rev 0) +++ trunk/LinuxBIOSv2/src/northbridge/intel/i82810/i82810.h 2007-06-14 12:02:38 UTC (rev 2720) @@ -0,0 +1,59 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Corey Osgood <corey(a)slightlyhackish.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Datasheet: + * - Name: Intel 810 Chipset: + * 82810/82810-DC100 Graphics and Memory Controller Hub (GMCH) + * - URL: http://www.intel.com/design/chipsets/datashts/290656.htm + * - PDF: ftp://download.intel.com/design/chipsets/datashts/29065602.pdf + * - Order Number: 290656-002 + */ + +/* + * PCI Configuration Registers. + * + * Any addresses between 0x00 and 0xff not listed below are reserved and + * should not be touched. + */ + +#define VID 0x00 /* Vendor Identification */ +#define DID 0x02 /* Device Identification */ +#define PCICMD 0x04 /* PCI Command Register */ +#define PCISTS 0x06 /* PCI Status Register */ +#define RID 0x08 /* Revision Identification */ +#define SUBC 0x0a /* Sub-Class Code */ +#define BCC 0x0b /* Base Class Code */ +#define MLT 0x0d /* Master Latency Timer */ +#define HDR 0x0e /* Header Type */ +#define SVID 0x2c /* Subsystem Vendor Identification */ +#define SID 0x2e /* Subsystem Identification */ +#define CAPPTR 0x34 /* Capabilities Pointer */ + +/* TODO: Descriptions */ +#define GMCHCFG 0x50 +#define PAM 0x51 +#define DRP 0x52 +#define DRAMT 0x53 +#define FDHC 0x58 +#define SMRAM 0x70 /* System Management RAM Control */ +#define MISSC 0x72 +#define MISSC2 0x80 +#define BUFF_SC 0x92 Added: trunk/LinuxBIOSv2/src/northbridge/intel/i82810/northbridge.c =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/intel/i82810/northbridge.c (rev 0) +++ trunk/LinuxBIOSv2/src/northbridge/intel/i82810/northbridge.c 2007-06-14 12:02:38 UTC (rev 2720) @@ -0,0 +1,217 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Corey Osgood <corey(a)slightlyhackish.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/io.h> +#include <stdint.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <stdlib.h> +#include <string.h> +#include <bitops.h> +#include "chip.h" +#include "northbridge.h" +#include "i82810.h" + +static void northbridge_init(device_t dev) +{ + printk_spew("Northbridge init\n"); +} + +static struct device_operations northbridge_operations = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = northbridge_init, + .enable = 0, + .ops_pci = 0, +}; + +static struct pci_driver northbridge_driver __pci_driver = { + .ops = &northbridge_operations, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x7120, +}; + +#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM) + +static void pci_domain_read_resources(device_t dev) +{ + struct resource *resource; + unsigned reg; + + /* Initialize the system wide io space constraints */ + resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); + resource->base = 0x400; + resource->limit = 0xffffUL; + resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + + /* Initialize the system wide memory resources constraints */ + resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); + resource->limit = 0xffffffffULL; + resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; +} + +static void ram_resource(device_t dev, unsigned long index, + unsigned long basek, unsigned long sizek) +{ + struct resource *resource; + + if (!sizek) { + return; + } + resource = new_resource(dev, index); + resource->base = ((resource_t)basek) << 10; + resource->size = ((resource_t)sizek) << 10; + resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \ + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; +} + +static void tolm_test(void *gp, struct device *dev, struct resource *new) +{ + struct resource **best_p = gp; + struct resource *best; + best = *best_p; + if (!best || (best->base > new->base)) { + best = new; + } + *best_p = best; +} + +static uint32_t find_pci_tolm(struct bus *bus) +{ + struct resource *min; + uint32_t tolm; + min = 0; + search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min); + tolm = 0xffffffffUL; + if (min && tolm > min->base) { + tolm = min->base; + } + return tolm; +} + +/* Table which returns the RAM size in MB when fed the DRP[7:4] or [3:0] value. + * Note that 2 is a value which the DRP should never be programmed to. + * Some size values appear twice, due to single-sided vs dual-sided banks. + */ +static int translate_i82810_to_mb[] = { +/* DRP 0 1 (2) 3 4 5 6 7 8 9 A B C D E F */ +/* MB */0, 8, 0, 16, 16, 24, 32, 32, 48, 64, 64, 96, 128, 128, 192, 256, +}; + +static void pci_domain_set_resources(device_t dev) +{ + device_t mc_dev; + uint32_t pci_tolm; + + pci_tolm = find_pci_tolm(&dev->link[0]); + mc_dev = dev->link[0].children; + + if (mc_dev) { + /* Figure out which areas are/should be occupied by RAM. + * This is all computed in kilobytes and converted to/from + * the memory controller right at the edges. + * Having different variables in different units is + * too confusing to get right. Kilobytes are good up to + * 4 Terabytes of RAM... + */ + unsigned long tomk, tolmk; + int idx; + int drp_value; + + /* First get the value for DIMM 0. */ + drp_value = pci_read_config8(mc_dev, DRP); + /* Translate it to MB and add to tomk. */ + tomk = (unsigned long)(translate_i82810_to_mb[drp_value & 0xf]); + /* Now do the same for DIMM 1. */ + drp_value = drp_value >> 4; // >>= 4; //? mess with later + tomk += (unsigned long)(translate_i82810_to_mb[drp_value]); + + printk_debug("Setting RAM size to %d MB\n", tomk); + + /* Convert tomk from MB to KB. */ + tomk = tomk << 10; + + /* Compute the top of Low memory. */ + tolmk = pci_tolm >> 10; + if (tolmk >= tomk) { + /* The PCI hole does does not overlap the memory. */ + tolmk = tomk; + } + + /* Report the memory regions. */ + idx = 10; + ram_resource(dev, idx++, 0, 640); + ram_resource(dev, idx++, 1024, tolmk - 1024); + } + assign_resources(&dev->link[0]); +} + +static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) +{ + max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); + return max; +} + +static struct device_operations pci_domain_ops = { + .read_resources = pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .enable_resources = enable_childrens_resources, + .init = 0, + .scan_bus = pci_domain_scan_bus, +}; + +static void cpu_bus_init(device_t dev) +{ + initialize_cpus(&dev->link[0]); +} + +static void cpu_bus_noop(device_t dev) +{ +} + +static struct device_operations cpu_bus_ops = { + .read_resources = cpu_bus_noop, + .set_resources = cpu_bus_noop, + .enable_resources = cpu_bus_noop, + .init = cpu_bus_init, + .scan_bus = 0, +}; + +static void enable_dev(struct device *dev) +{ + struct device_path path; + + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { + dev->ops = &pci_domain_ops; + pci_set_method(dev); + } + else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) { + dev->ops = &cpu_bus_ops; + } +} + +struct chip_operations northbridge_intel_i82810_ops = { + CHIP_NAME("Intel 82810 Northbridge") + .enable_dev = enable_dev, +}; Added: trunk/LinuxBIOSv2/src/northbridge/intel/i82810/northbridge.h =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/intel/i82810/northbridge.h (rev 0) +++ trunk/LinuxBIOSv2/src/northbridge/intel/i82810/northbridge.h 2007-06-14 12:02:38 UTC (rev 2720) @@ -0,0 +1,26 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Corey Osgood <corey(a)slightlyhackish.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef NORTHBRIDGE_INTEL_I82810_NORTHBRIDGE_H +#define NORTHBRIDGE_INTEL_I82810_NORTHBRIDGE_H + +extern unsigned int i82810_scan_root_bus(device_t root, unsigned int max); + +#endif /* NORTHBRIDGE_INTEL_I82810_NORTHBRIDGE_H */ Added: trunk/LinuxBIOSv2/src/northbridge/intel/i82810/raminit.c =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/intel/i82810/raminit.c (rev 0) +++ trunk/LinuxBIOSv2/src/northbridge/intel/i82810/raminit.c 2007-06-14 12:02:38 UTC (rev 2720) @@ -0,0 +1,327 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * Copyright (C) 2007 Corey Osgood <corey(a)slightlyhackish.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <spd.h> +#include <sdram_mode.h> +#include <delay.h> +#include "i82810.h" + +/*----------------------------------------------------------------------------- +Macros and definitions. +-----------------------------------------------------------------------------*/ + +/* Uncomment this to enable debugging output. */ +// #define DEBUG_RAM_SETUP 1 + +/* Debugging macros. */ +#if defined(DEBUG_RAM_SETUP) +#define PRINT_DEBUG(x) print_debug(x) +#define PRINT_DEBUG_HEX8(x) print_debug_hex8(x) +#define PRINT_DEBUG_HEX16(x) print_debug_hex16(x) +#define PRINT_DEBUG_HEX32(x) print_debug_hex32(x) +#define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0)) +#else +#define PRINT_DEBUG(x) +#define PRINT_DEBUG_HEX8(x) +#define PRINT_DEBUG_HEX16(x) +#define PRINT_DEBUG_HEX32(x) +#define DUMPNORTH() +#endif + +/* DRAMT[7:5] - SDRAM Mode Select (SMS). */ +#define RAM_COMMAND_SELF_REFRESH 0x0 /* IE disable refresh */ +#define RAM_COMMAND_NORMAL 0x1 /* Normal refresh, 15.6us/11.7us for 100/133MHz */ +#define RAM_COMMAND_NORMAL_FR 0x2 /* Fast refresh, 7.8us/5.85us for 100/133MHz */ +#define RAM_COMMAND_NOP 0x4 +#define RAM_COMMAND_PRECHARGE 0x5 +#define RAM_COMMAND_MRS 0x6 +#define RAM_COMMAND_CBR 0x7 + +/*----------------------------------------------------------------------------- +SDRAM configuration functions. +-----------------------------------------------------------------------------*/ + +/** + * Send the specified RAM command to all DIMMs. + * + * @param Memory controller + * @param TODO + * @param TODO + */ +static void do_ram_command(const struct mem_controller *ctrl, uint32_t command, + uint32_t addr_offset, uint32_t row_offset) +{ + int i; + uint8_t reg; + + /* TODO: Support for multiple DIMMs. */ + + /* Configure the RAM command. */ + reg = pci_read_config8(ctrl->d0, DRAMT); + reg &= 0x1f; /* Clear bits 7-5. */ + reg |= command << 5; + pci_write_config8(ctrl->d0, DRAMT, reg); + + /* RAM_COMMAND_NORMAL affects only the memory controller and + doesn't need to be "sent" to the DIMMs. */ + /* if (command == RAM_COMMAND_NORMAL) return; */ + + PRINT_DEBUG(" Sending RAM command 0x"); + PRINT_DEBUG_HEX8(reg); + PRINT_DEBUG(" to 0x"); + PRINT_DEBUG_HEX32(0 + addr_offset); // FIXME + PRINT_DEBUG("\r\n"); + + /* Read from (DIMM start address + addr_offset). */ + read32(0 + addr_offset); //first offset is always 0 + read32(row_offset + addr_offset); +} + +/*----------------------------------------------------------------------------- +DIMM-independant configuration functions. +-----------------------------------------------------------------------------*/ + +static void spd_set_dram_size(const struct mem_controller *ctrl, uint32_t row_offset) +{ + /* The variables drp and dimm_size have to be ints since all the + * SMBus-related functions return ints, and its just easier this way. + */ + int i, drp, dimm_size; + + drp = 0x00; + + for (i = 0; i < DIMM_SOCKETS; i++) + { + /* First check if a DIMM is actually present. */ + if (smbus_read_byte(ctrl->channel0[i], 2) == 4) { + print_debug("Found DIMM in slot "); + print_debug_hex8(i); + print_debug("\r\n"); + + dimm_size = smbus_read_byte(ctrl->channel0[i], 31); + + /* WISHLIST: would be nice to display it as decimal? */ + print_debug("DIMM is 0x"); + print_debug_hex8(dimm_size * 4); + print_debug("MB\r\n"); + + /* The i810 can't handle DIMMs larger than 128MB per + * side. This will fail if the DIMM uses a + * non-supported DRAM tech, and can't be used until + * buffers are done dynamically. + * Note: the factory BIOS just dies if it spots + * this :D + */ + if(dimm_size > 32) { + print_err("DIMM row sizes larger than 128MB not" + "supported on i810\r\n"); + print_err("Attempting to treat as 128MB DIMM\r\n"); + dimm_size = 32; + } + + /* Set the row offset, in KBytes (should this be Kbits?) */ + /* Note that this offset is the start of the next row. */ + row_offset = (dimm_size * 4 * 1024); + + /* This is the way I was doing this, it's provided mainly + * as an alternative to the "new" way. + */ + + #if 0 + /* 8MB */ + if(dimm_size == 0x2) dimm_size = 0x1; + /* 16MB */ + else if(dimm_size == 0x4) dimm_size = 0x4; + /* 32MB */ + else if(dimm_size == 0x8) dimm_size = 0x7; + /* 64 MB */ + else if(dimm_size == 0x10) dimm_size = 0xa; + /* 128 MB */ + else if(dimm_size == 0x20) dimm_size = 0xd; + else print_debug("Ram Size not supported\r\n"); + #endif + + /* This array is provided in raminit.h, because it got + * extremely messy. The above way is cleaner, but + * doesn't support any asymetrical/odd configurations. + */ + dimm_size = translate_spd_to_i82810[dimm_size]; + + print_debug("After translation, dimm_size is 0x"); + print_debug_hex8(dimm_size); + print_debug("\r\n"); + + /* If the DIMM is dual-sided, the DRP value is +2 */ + /* TODO: Figure out asymetrical configurations */ + if ((smbus_read_byte(ctrl->channel0[i], 127) | 0xf) == 0xff) { + print_debug("DIMM is dual-sided\r\n"); + dimm_size += 2; + } + } else { + print_debug("No DIMM found in slot "); + print_debug_hex8(i); + print_debug("\r\n"); + + /* If there's no DIMM in the slot, set the value to 0. */ + dimm_size = 0x00; + } + + /* Put in dimm_size to reflect the current DIMM. */ + drp |= dimm_size << (i * 4); + } + + print_debug("DRP calculated to 0x"); + print_debug_hex8(drp); + print_debug("\r\n"); + + pci_write_config8(ctrl->d0, DRP, drp); +} + +static void set_dram_timing(const struct mem_controller *ctrl) +{ + /* TODO, for now using default, hopefully safe values. */ + // pci_write_config8(ctrl->d0, DRAMT, 0x00); +} + +static void set_dram_buffer_strength(const struct mem_controller *ctrl) +{ + /* TODO: This needs to be set according to the DRAM tech + * (x8, x16, or x32). Argh, Intel provides no docs on this! + * Currently, it needs to be pulled from the output of + * lspci -xxx Rx92 + */ + pci_write_config16(ctrl->d0, BUFF_SC, 0x77da); +} + +/*----------------------------------------------------------------------------- +Public interface. +-----------------------------------------------------------------------------*/ + +/** + * TODO. + * + * @param Memory controller + */ +static void sdram_set_registers(const struct mem_controller *ctrl) +{ + unsigned long val; + + /* TODO */ + pci_write_config8(ctrl->d0, GMCHCFG, 0x60); + + /* PAMR: Programmable Attributes Register + * Every pair of bits controls an address range: + * 00 = Disabled, all accesses are forwarded to the ICH + * 01 = Read Only + * 10 = Write Only + * 11 = Read/Write + + * Bit Range + * 7:6 000F0000 - 000FFFFF + * 5:4 000E0000 - 000EFFFF + * 3:2 000D0000 - 000DFFFF + * 1:0 000C0000 - 000CFFFF + */ + + /* Ideally, this should be R/W for as many ranges as possible. */ + pci_write_config8(ctrl->d0, PAM, 0x00); + + /* Enable 1MB framebuffer. */ + pci_write_config8(ctrl->d0, SMRAM, 0xC0); + + val = pci_read_config16(ctrl->d0, MISSC); + /* Preserve reserved bits. */ + val &= 0xff06; + /* Set graphics cache window to 32MB, no power throttling. */ + val |= 0x0001; + pci_write_config16(ctrl->d0, MISSC, val); + + val = pci_read_config8(ctrl->d0, MISSC2); + /* Enable graphics palettes and clock gating (not optional!) */ + val |= 0x06; + pci_write_config8(ctrl->d0, MISSC2, val); +} + +/** + * TODO. + * + * @param Memory controller + */ +static void sdram_set_spd_registers(const struct mem_controller *ctrl) +{ + /* spd_set_dram_size() moved into sdram_enable() to prevent having + * to pass a variable between here and there. + */ + set_dram_buffer_strength(ctrl); + + set_dram_timing(ctrl); +} + +/** + * Enable SDRAM. + * + * @param Number of controllers + * @param Memory controller + */ +static void sdram_enable(int controllers, const struct mem_controller *ctrl) +{ + int i; + + /* Todo: this will currently work with either one dual sided or two + * single sided DIMMs. Needs to work with 2 dual sided DIMMs in the + * long run. + */ + uint32_t row_offset; + + spd_set_dram_size(ctrl, row_offset); + + /* 1. Apply NOP. */ + PRINT_DEBUG("RAM Enable 1: Apply NOP\r\n"); + do_ram_command(ctrl, RAM_COMMAND_NOP, 0, row_offset); + udelay(200); + + /* 2. Precharge all. Wait tRP. */ + PRINT_DEBUG("RAM Enable 2: Precharge all\r\n"); + do_ram_command(ctrl, RAM_COMMAND_PRECHARGE, 0, row_offset); + udelay(1); + + /* 3. Perform 8 refresh cycles. Wait tRC each time. */ + PRINT_DEBUG("RAM Enable 3: CBR\r\n"); + do_ram_command(ctrl, RAM_COMMAND_CBR, 0, row_offset); + for (i = 0; i < 8; i++) { + read32(0); + read32(row_offset); + udelay(1); + } + + /* 4. Mode register set. Wait two memory cycles. */ + PRINT_DEBUG("RAM Enable 4: Mode register set\r\n"); + do_ram_command(ctrl, RAM_COMMAND_MRS, 0x1d0, row_offset); + udelay(2); + + /* 5. Normal operation (enables refresh) */ + PRINT_DEBUG("RAM Enable 5: Normal operation\r\n"); + do_ram_command(ctrl, RAM_COMMAND_NORMAL, 0, row_offset); + udelay(1); + + PRINT_DEBUG("Northbridge following SDRAM init:\r\n"); + DUMPNORTH(); +} Added: trunk/LinuxBIOSv2/src/northbridge/intel/i82810/raminit.h =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/intel/i82810/raminit.h (rev 0) +++ trunk/LinuxBIOSv2/src/northbridge/intel/i82810/raminit.h 2007-06-14 12:02:38 UTC (rev 2720) @@ -0,0 +1,90 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Corey Osgood <corey(a)slightlyhackish.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef NORTHBRIDGE_INTEL_I82810_RAMINIT_H +#define NORTHBRIDGE_INTEL_I82810_RAMINIT_H + +/* The i810 supports max 2 dual-sided DIMMs. */ +#define DIMM_SOCKETS 2 + +struct mem_controller { + device_t d0; + uint16_t channel0[DIMM_SOCKETS]; +}; + + +#endif /* NORTHBRIDGE_INTEL_I82810_RAMINIT_H */ + +/* The following table has been bumped over to this header to avoid clutter in + * raminit.c. It's used to translate the value read from SPD Byte 31 to a value + * the northbridge can understand in DRP, aka Rx52[7:4], [3:0]. Where most + * northbridges have some sort of simple calculation that can be done for this, + * I haven't yet figured out one for this northbridge. Until someone does, + * this table is necessary. + */ + +/* TODO: Find a better way of doing this */ + +static const uint8_t translate_spd_to_i82810[] = { + /* Note: 4MB sizes are not supported, so dual-sided DIMMs with a 4MB + * side can't be either, at least for now. + */ + /* TODO: For above case, only use the other side if > 4MB, and get some + * of these DIMMs to test it with. Same for unsupported 128/x sizes. + */ + + /* SPD Byte 31 Memory Size [Side 1/2] */ + 0xff, /* 0x01 No memory */ + 0xff, /* 0x01 4/0 */ + 0x01, /* 0x02 8/0 */ + 0xff, /* 0x03 8/4 */ + 0x04, /* 0x04 16/0 or 16 */ + 0xff, /* 0x05 16/4 */ + 0x05, /* 0x06 16/8 */ + 0xff, /* 0x07 Invalid */ + 0x07, /* 0x08 32/0 or 32 */ + 0xff, /* 0x09 32/4 */ + 0xff, /* 0x0A 32/8 */ + 0xff, /* 0x0B Invalid */ + 0x08, /* 0x0C 32/16 */ + 0xff, 0xff, 0xff, /* 0x0D-0F Invalid */ + 0x0a, /* 0x10 64/0 or 64 */ + 0xff, /* 0x11 64/4 */ + 0xff, /* 0x12 64/8 */ + 0xff, /* 0x13 Invalid */ + 0xff, /* 0x14 64/16 */ + 0xff, 0xff, 0xff, /* 0x15-17 Invalid */ + 0x0b, /* 0x18 64/32 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x19-1f Invalid */ + 0x0d, /* 0x20 128/0 or 128 */ + /* These configurations are not supported by the i810 */ + 0xff, /* 0x21 128/4 */ + 0xff, /* 0x22 128/8 */ + 0xff, /* 0x23 Invalid */ + 0xff, /* 0x24 128/16 */ + 0xff, 0xff, 0xff, /* 0x25-27 Invalid */ + 0xff, /* 0x28 128/32 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x29-2f Invalid */ + 0x0e, /* 0x30 128/64 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, /* 0x31-3f Invalid */ + 0x0f, /* 0x40 256/0 or 256 */ + /* Anything larger is not supported by the i810 */ +};

1 0

[LinuxBIOS] r2719 build service
by LinuxBIOS information 14 Jun '07

14 Jun '07

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "stepan" checked in revision 2719 to the LinuxBIOS source repository and caused the following changes: Change Log: This patch adds support for the Intel i82810 northbridge and various i82801xx southbridges, along with the Asus MEW-VM. With this, my machine attempts to boot linux, but does so very slowly and fails during the boot process, probably because of the irq tables. Signed-off-by: Corey Osgood <corey.osgood(a)gmail.com> Acked-by: Joseph Smith <joe(a)smittys.pointclark.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of arima:hdama is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2719&device=hdama&vendor=… Configuration of artecgroup:dbe61 is still broken Configuration of asus:mew-vm is still broken Compilation of ibm:e325 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2719&device=e325&vendor=i… Compilation of ibm:e326 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2719&device=e326&vendor=i… Compilation of iei:juki-511p is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2719&device=juki-511p&ven… Compilation of iwill:dk8s2 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2719&device=dk8s2&vendor=… Compilation of iwill:dk8x is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2719&device=dk8x&vendor=i… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, LinuxBIOS automatic build system

1 0

[LinuxBIOS] r2719 - in trunk/LinuxBIOSv2: src/cpu/intel/model_6xx src/mainboard/asus src/mainboard/asus/mew-vm src/southbridge/intel src/southbridge/intel/i82801xx targets/asus targets/asus/mew-vm
by svn＠openbios.org 14 Jun '07

14 Jun '07

Author: stepan Date: 2007-06-14 08:10:57 +0200 (Thu, 14 Jun 2007) New Revision: 2719 Added: trunk/LinuxBIOSv2/src/mainboard/asus/mew-vm/ trunk/LinuxBIOSv2/src/mainboard/asus/mew-vm/Config.lb trunk/LinuxBIOSv2/src/mainboard/asus/mew-vm/Options.lb trunk/LinuxBIOSv2/src/mainboard/asus/mew-vm/auto.c trunk/LinuxBIOSv2/src/mainboard/asus/mew-vm/chip.h trunk/LinuxBIOSv2/src/mainboard/asus/mew-vm/cmos.layout trunk/LinuxBIOSv2/src/mainboard/asus/mew-vm/debug.c trunk/LinuxBIOSv2/src/mainboard/asus/mew-vm/failover.c trunk/LinuxBIOSv2/src/mainboard/asus/mew-vm/irq_tables.c trunk/LinuxBIOSv2/src/mainboard/asus/mew-vm/mainboard.c trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/ trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/Config.lb trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/chip.h trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/cmos_failover.c trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx.c trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx.h trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_ac97.c trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_early_smbus.c trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_ide.c trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_lpc.c trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_nic.c trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_pci.c trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_reset.c trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_sata.c trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_smbus.c trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_smbus.h trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_usb.c trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_usb_ehci.c trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_watchdog.c trunk/LinuxBIOSv2/targets/asus/mew-vm/ trunk/LinuxBIOSv2/targets/asus/mew-vm/Config.lb Modified: trunk/LinuxBIOSv2/src/cpu/intel/model_6xx/model_6xx_init.c Log: This patch adds support for the Intel i82810 northbridge and various i82801xx southbridges, along with the Asus MEW-VM. With this, my machine attempts to boot linux, but does so very slowly and fails during the boot process, probably because of the irq tables. Signed-off-by: Corey Osgood <corey.osgood(a)gmail.com> Acked-by: Joseph Smith <joe(a)smittys.pointclark.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/LinuxBIOSv2/src/cpu/intel/model_6xx/model_6xx_init.c =================================================================== --- trunk/LinuxBIOSv2/src/cpu/intel/model_6xx/model_6xx_init.c 2007-06-12 22:54:41 UTC (rev 2718) +++ trunk/LinuxBIOSv2/src/cpu/intel/model_6xx/model_6xx_init.c 2007-06-14 06:10:57 UTC (rev 2719) @@ -44,6 +44,7 @@ .init = model_6xx_init, }; static struct cpu_device_id cpu_table[] = { + { X86_VENDOR_INTEL, 0x0665 }, /* Celeron (Mendocino) */ { X86_VENDOR_INTEL, 0x0672 }, { X86_VENDOR_INTEL, 0x0673 }, { X86_VENDOR_INTEL, 0x0681 }, Added: trunk/LinuxBIOSv2/src/mainboard/asus/mew-vm/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/asus/mew-vm/Config.lb (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/asus/mew-vm/Config.lb 2007-06-14 06:10:57 UTC (rev 2719) @@ -0,0 +1,182 @@ +## +## Compute the location and size of where this firmware image +## (linuxBIOS plus bootloader) will live in the boot rom chip. +## +if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) +else + default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) + default ROM_SECTION_OFFSET = 0 +end + +## +## Compute the start location and size size of +## The linuxBIOS bootloader. +## +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) +default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) + +## +## Compute where this copy of linuxBIOS will start in the boot rom +## +default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) + +## +## Compute a range of ROM that can cached to speed up linuxBIOS, +## execution speed. +## +## XIP_ROM_SIZE must be a power of 2. +## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE +## +default XIP_ROM_SIZE=65536 +default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) + +## +## Set all of the defaults for an x86 architecture +## + +arch i386 end + +## +## Build the objects we have code for in this directory. +## + +driver mainboard.o + +if HAVE_PIRQ_TABLE object irq_tables.o end +#object reset.o + +## +## Romcc output +## +makerule ./failover.E + depends "$(MAINBOARD)/failover.c ./romcc" + action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" +end + +makerule ./failover.inc + depends "$(MAINBOARD)/failover.c ./romcc" + action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" +end + +makerule ./auto.E + depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + action "./romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end +makerule ./auto.inc + depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + action "./romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end + +## +## Build our 16 bit and 32 bit linuxBIOS entry code +## +mainboardinit cpu/x86/16bit/entry16.inc +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/16bit/entry16.lds +ldscript /cpu/x86/32bit/entry32.lds + +## +## Build our reset vector (This is where linuxBIOS is entered) +## +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds +else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds +end + +### Should this be in the northbridge code? +mainboardinit arch/i386/lib/cpu_reset.inc + +## +## Include an id string (For safe flashing) +## +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds + +### +### This is the early phase of linuxBIOS startup +### Things are delicate and we test to see if we should +### failover to another image. +### +if USE_FALLBACK_IMAGE + ldscript /arch/i386/lib/failover.lds + mainboardinit ./failover.inc +end + +### +### O.k. We aren't just an intermediary anymore! +### + +## +## Setup RAM +## +mainboardinit cpu/x86/fpu/enable_fpu.inc +mainboardinit cpu/x86/mmx/enable_mmx.inc +mainboardinit ./auto.inc +mainboardinit cpu/x86/mmx/disable_mmx.inc + +## +## Include the secondary Configuration files +## +dir /pc80 +config chip.h + +chip northbridge/intel/i82810 + device pci_domain 0 on + device pci 0.0 on end # Host bridge + device pci 1.0 on # Onboard Video + #chip drivers/pci/onboard + # device pci 1.0 on end + # register "rom_address" = "0xfff80000" + #end + end + chip southbridge/intel/i82801xx # Southbridge + device pci 1e.0 on # PCI Bridge + #chip drivers/pci/onboard + # device pci 1.0 on end + # register "rom_address" = "0xfff80000" + #end + end + device pci 1f.0 on # ISA/LPC? Bridge + chip superio/smsc/lpc47b272 + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.3 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.5 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.7 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # Keyboard interrupt + irq 0x72 = 12 # Mouse interrupt + end + device pnp 2e.a off end # ACPI + end + end + device pci 1f.1 on end # IDE + device pci 1f.2 on end # USB + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # AC'97, no header on MEW-VM + device pci 1f.6 off end # AC'97 Modem (MC'97) + end + end + chip cpu/intel/socket_PGA370 + end +end + Added: trunk/LinuxBIOSv2/src/mainboard/asus/mew-vm/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/asus/mew-vm/Options.lb (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/asus/mew-vm/Options.lb 2007-06-14 06:10:57 UTC (rev 2719) @@ -0,0 +1,159 @@ +uses HAVE_MP_TABLE +uses HAVE_PIRQ_TABLE +uses USE_FALLBACK_IMAGE +uses HAVE_FALLBACK_BOOT +uses HAVE_HARD_RESET +uses HAVE_OPTION_TABLE +uses USE_OPTION_TABLE +uses CONFIG_ROM_PAYLOAD +uses IRQ_SLOT_COUNT +uses MAINBOARD +uses MAINBOARD_VENDOR +uses MAINBOARD_PART_NUMBER +uses LINUXBIOS_EXTRA_VERSION +uses ARCH +uses FALLBACK_SIZE +uses STACK_SIZE +uses HEAP_SIZE +uses ROM_SIZE +uses ROM_SECTION_SIZE +uses ROM_IMAGE_SIZE +uses ROM_SECTION_SIZE +uses ROM_SECTION_OFFSET +uses CONFIG_ROM_PAYLOAD_START +uses CONFIG_COMPRESSED_PAYLOAD_LZMA +uses PAYLOAD_SIZE +uses _ROMBASE +uses _RAMBASE +uses XIP_ROM_SIZE +uses XIP_ROM_BASE +uses HAVE_MP_TABLE +uses CROSS_COMPILE +uses CC +uses HOSTCC +uses OBJCOPY +uses DEFAULT_CONSOLE_LOGLEVEL +uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_CONSOLE_SERIAL8250 +uses TTYS0_BAUD +uses TTYS0_BASE +uses TTYS0_LCS +uses CONFIG_UDELAY_TSC +uses CONFIG_IDE + +## ROM_SIZE is the size of boot ROM that this board will use. +default ROM_SIZE = 512*1024 + +### +### Build options +### + +## +## Build code for the fallback boot +## +default HAVE_FALLBACK_BOOT = 1 + +## +## no MP table +## +default HAVE_MP_TABLE = 0 + +## +## Build code to reset the motherboard from linuxBIOS +## +default HAVE_HARD_RESET = 0 + +## +## Build code to export a programmable irq routing table +## +default HAVE_PIRQ_TABLE = 1 +default IRQ_SLOT_COUNT = 4 + +## +## Build code to export a CMOS option table +## +default HAVE_OPTION_TABLE = 0 + +## IDE Support +default CONFIG_IDE = 1 + +### +### LinuxBIOS layout values +### + +## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +default ROM_IMAGE_SIZE = 65536 +default FALLBACK_SIZE = 131072 + +## +## Use a small 8K stack +## +default STACK_SIZE=0x2000 + +## +## Use a small 16K heap +## +default HEAP_SIZE=0x4000 + +## +## Only use the option table in a normal image +## +#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default USE_OPTION_TABLE = 0 + +default _RAMBASE = 0x00004000 + +default CONFIG_ROM_PAYLOAD = 1 + +## +## The default compiler +## +default CROSS_COMPILE="" +default CC="$(CROSS_COMPILE)gcc -m32" +default HOSTCC="gcc" + +## +## The Serial Console +## + +# To Enable the Serial Console +default CONFIG_CONSOLE_SERIAL8250=1 + +## Select the serial console baud rate +default TTYS0_BAUD=115200 +#default TTYS0_BAUD=57600 +#default TTYS0_BAUD=38400 +#default TTYS0_BAUD=19200 +#default TTYS0_BAUD=9600 +#default TTYS0_BAUD=4800 +#default TTYS0_BAUD=2400 +#default TTYS0_BAUD=1200 + +# Select the serial console base port +default TTYS0_BASE=0x3f8 + +# Select the serial protocol +# This defaults to 8 data bits, 1 stop bit, and no parity +default TTYS0_LCS=0x3 + +## +### Select the linuxBIOS loglevel +## +## EMERG 1 system is unusable +## ALERT 2 action must be taken immediately +## CRIT 3 critical conditions +## ERR 4 error conditions +## WARNING 5 warning conditions +## NOTICE 6 normal but significant condition +## INFO 7 informational +## DEBUG 8 debug-level messages +## SPEW 9 Way too many details + +## Request this level of debugging output +default DEFAULT_CONSOLE_LOGLEVEL=9 +## At a maximum only compile in this level of debugging +default MAXIMUM_CONSOLE_LOGLEVEL=9 + +default CONFIG_UDELAY_TSC=1 +end + Added: trunk/LinuxBIOSv2/src/mainboard/asus/mew-vm/auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/asus/mew-vm/auto.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/asus/mew-vm/auto.c 2007-06-14 06:10:57 UTC (rev 2719) @@ -0,0 +1,106 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Corey Osgood <corey(a)slightlyhackish.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define ASSEMBLY 1 + +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <arch/hlt.h> +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" +#include "superio/smsc/lpc47b272/lpc47b272_early_serial.c" +#include "northbridge/intel/i82810/raminit.h" +#include "cpu/x86/mtrr/earlymtrr.c" +#include "cpu/x86/bist.h" + +#define SERIAL_DEV PNP_DEV(0x2e, LPC47B272_SP1) + +#include "southbridge/intel/i82801xx/i82801xx_early_smbus.c" + +void udelay(int usecs) +{ + int i; + for(i = 0; i < usecs; i++) + outb(i&0xff, 0x80); +} + +#include "debug.c" +#include "lib/delay.c" + +#include "northbridge/intel/i82810/raminit.c" +#include "northbridge/intel/i82810/debug.c" +#include "sdram/generic_sdram.c" + +static void main(unsigned long bist) +{ + static const struct mem_controller memctrl[] = { + { + .d0 = PCI_DEV(0, 0, 0), + .channel0 = { + (0xa << 3) | 0, + (0xa << 3) | 1, + }, + } + }; + + if (bist == 0) { + early_mtrr_init(); + } + + enable_smbus(); + + lpc47b272_enable_serial(SERIAL_DEV, TTYS0_BASE); + uart_init(); + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + //enable_shadow_ram(); + + //dump_spd_registers(&memctrl[0]); + + /* sdram_initialize runs out of registers */ + //sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl); + + sdram_set_registers(memctrl); + sdram_set_spd_registers(memctrl); + sdram_enable(0, memctrl); + + /* Check whether RAM is working. + * + * Do _not_ check the area from 640 KB - 1 MB, as that's not really + * RAM, but rather reserved for various other things: + * + * - 640 KB - 768 KB: Video Buffer Area + * - 768 KB - 896 KB: Expansion Area + * - 896 KB - 960 KB: Extended System BIOS Area + * - 960 KB - 1 MB: Memory (BIOS Area) - System BIOS Area + * + * Trying to check these areas will fail. + */ + /* TODO: This is currently hardcoded to check 64 MB. */ + //ram_check(0x00000000, 0x0009ffff); /* 0 - 640 KB */ + //ram_check(0x00100000, 0x007c0000); /* 1 MB - 64 MB */ +} Added: trunk/LinuxBIOSv2/src/mainboard/asus/mew-vm/chip.h =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/asus/mew-vm/chip.h (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/asus/mew-vm/chip.h 2007-06-14 06:10:57 UTC (rev 2719) @@ -0,0 +1,5 @@ +extern struct chip_operations mainboard_asus_mew_vm_ops; + +struct mainboard_asus_mew_vm_config { + int nothing; +}; Added: trunk/LinuxBIOSv2/src/mainboard/asus/mew-vm/cmos.layout =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/asus/mew-vm/cmos.layout (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/asus/mew-vm/cmos.layout 2007-06-14 06:10:57 UTC (rev 2719) @@ -0,0 +1,74 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +1008 16 h 0 check_sum + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM + +checksums + +checksum 392 1007 1008 + + Added: trunk/LinuxBIOSv2/src/mainboard/asus/mew-vm/debug.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/asus/mew-vm/debug.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/asus/mew-vm/debug.c 2007-06-14 06:10:57 UTC (rev 2719) @@ -0,0 +1,66 @@ + +static void print_debug_pci_dev(unsigned dev) +{ + print_debug("PCI: "); + print_debug_hex8((dev >> 16) & 0xff); + print_debug_char(':'); + print_debug_hex8((dev >> 11) & 0x1f); + print_debug_char('.'); + print_debug_hex8((dev >> 8) & 7); +} + +static void print_pci_devices(void) +{ + device_t dev; + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); + dev += PCI_DEV(0,0,1)) { + uint32_t id; + id = pci_read_config32(dev, PCI_VENDOR_ID); + if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0x0000)) { + continue; + } + print_debug_pci_dev(dev); + print_debug("\r\n"); + } +} + +static void dump_pci_device(unsigned dev) +{ + int i; + print_debug_pci_dev(dev); + print_debug("\r\n"); + + for(i = 0; i <= 255; i++) { + unsigned char val; + if ((i & 0x0f) == 0) { + print_debug_hex8(i); + print_debug_char(':'); + } + val = pci_read_config8(dev, i); + print_debug_char(' '); + print_debug_hex8(val); + if ((i & 0x0f) == 0x0f) { + print_debug("\r\n"); + } + } +} + +static void dump_pci_devices(void) +{ + device_t dev; + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); + dev += PCI_DEV(0,0,1)) { + uint32_t id; + id = pci_read_config32(dev, PCI_VENDOR_ID); + if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0x0000)) { + continue; + } + dump_pci_device(dev); + } +} Added: trunk/LinuxBIOSv2/src/mainboard/asus/mew-vm/failover.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/asus/mew-vm/failover.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/asus/mew-vm/failover.c 2007-06-14 06:10:57 UTC (rev 2719) @@ -0,0 +1,32 @@ +#define ASSEMBLY 1 +#include <stdint.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include "arch/romcc_io.h" +#include "pc80/mc146818rtc_early.c" + +static unsigned long main(unsigned long bist) +{ + /* This is the primary cpu how should I boot? */ + if (do_normal_boot()) { + goto normal_image; + } + else { + goto fallback_image; + } + normal_image: + asm volatile ("jmp __normal_image" + : /* outputs */ + : "a" (bist) /* inputs */ + : /* clobbers */ + ); + cpu_reset: + asm volatile ("jmp __cpu_reset" + : /* outputs */ + : "a"(bist) /* inputs */ + : /* clobbers */ + ); + fallback_image: + return bist; +} Added: trunk/LinuxBIOSv2/src/mainboard/asus/mew-vm/irq_tables.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/asus/mew-vm/irq_tables.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/asus/mew-vm/irq_tables.c 2007-06-14 06:10:57 UTC (rev 2719) @@ -0,0 +1,42 @@ +/* This file was generated by getpir.c, do not modify! + * (but if you do, please run checkpir on it to verify) + * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up + * + * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM +*/ + +#include <arch/pirq_routing.h> + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32+16*11, /* there can be total 11 devices on the bus */ + 0x00, /* Where the interrupt router lies (bus) */ + (0x11<<3)|0x0, /* Where the interrupt router lies (dev) */ + 0xe20, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x7120, /* Device */ + 0, /* Crap (miniport) */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0x89, /* u8 checksum , this has to set to some value +that would give 0 after the sum of all bytes for this structure (including checksum) */ + { + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00,(0x08<<3)|0x0, {{0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0xdea0}, {0x01, 0x0dea0}}, 0x1, 0x0}, + {0x00,(0x09<<3)|0x0, {{0x03, 0xdea0}, {0x04, 0xdea0}, {0x01, 0xdea0}, {0x02, 0x0dea0}}, 0x2, 0x0}, + {0x00,(0x0a<<3)|0x0, {{0x04, 0xdea0}, {0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0x0dea0}}, 0x3, 0x0}, + {0x00,(0x0b<<3)|0x0, {{0x04, 0xdea0}, {0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0x0dea0}}, 0x4, 0x0}, + {0x00,(0x0c<<3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x5, 0x0}, + {0x00,(0x0d<<3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x6, 0x0}, + {0x00,(0x11<<3)|0x0, {{0x00, 0xdea0}, {0x00, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x0, 0x0}, + {0x00,(0x0f<<3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x0, 0x0}, + {0x00,(0x01<<3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x0, 0x0}, + {0x00,(0x10<<3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x0, 0x0}, + {0x00,(0x12<<3)|0x0, {{0x01, 0xdea0}, {0x00, 0xdea0}, {0x00, 0xdea0}, {0x00, 0x0dea0}}, 0x0, 0x0}, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} Added: trunk/LinuxBIOSv2/src/mainboard/asus/mew-vm/mainboard.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/asus/mew-vm/mainboard.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/asus/mew-vm/mainboard.c 2007-06-14 06:10:57 UTC (rev 2719) @@ -0,0 +1,7 @@ +#include <device/device.h> +#include "chip.h" + +struct chip_operations mainboard_asus_mew_vm_ops = { + CHIP_NAME("ASUS MEW-VM Mainboard") +}; + Added: trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/Config.lb (rev 0) +++ trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/Config.lb 2007-06-14 06:10:57 UTC (rev 2719) @@ -0,0 +1,30 @@ +## +## This file is part of the LinuxBIOS project. +## +## Copyright (C) 2007 Corey Osgood <corey.osgood(a)gmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## +driver i82801xx.o +driver i82801xx_usb.o +driver i82801xx_lpc.o +driver i82801xx_ide.o +driver i82801xx_usb_ehci.o +driver i82801xx_ac97.o +driver i82801xx_nic.o +driver i82801xx_pci.o +driver i82801xx_sata.o +object i82801xx_reset.o +object i82801xx_watchdog.o Added: trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/chip.h =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/chip.h (rev 0) +++ trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/chip.h 2007-06-14 06:10:57 UTC (rev 2719) @@ -0,0 +1,39 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Corey Osgood <corey_osgood(a)verizon.net> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef IGNORE_I82801XX_DEVICE_LIST +#warning "The i82801xx code currently supports, on a testing/experimental basis," +#warning "these devices:" +#warning "i82801aa, i82801ab, i82801ba, i82801ca, i82801db, i82801dbm, i82801eb," +#warning "and i82801er." +#warning "Using this without modification on any other i82801 version will probably" +#warning "work until ram init, but will fail after that" +#endif + +#ifndef SOUTHBRIDGE_INTEL_I82801XX_CHIP_H +#define SOUTHBRIDGE_INTEL_I82801XX_CHIP_H + +struct southbridge_intel_i82801xx_config +{ +}; + +extern struct chip_operations southbridge_intel_i82801xx_ops; + +#endif /* SOUTHBRIDGE_INTEL_I82801XX_CHIP_H */ Added: trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/cmos_failover.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/cmos_failover.c (rev 0) +++ trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/cmos_failover.c 2007-06-14 06:10:57 UTC (rev 2719) @@ -0,0 +1,32 @@ +/* + * This file is part of the LinuxBIOS project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "i82801xx.h" + +static void check_cmos_failed(void) +{ + uint8_t byte; + byte = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); + if( byte & RTC_FAILED) { + //clear bit 1 and bit 2 + byte = cmos_read(RTC_BOOT_BYTE); + byte &= 0x0c; + byte |= MAX_REBOOT_CNT << 4; + cmos_write(byte, RTC_BOOT_BYTE); + } +} Added: trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx.c (rev 0) +++ trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx.c 2007-06-14 06:10:57 UTC (rev 2719) @@ -0,0 +1,67 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2005 Digital Design Corporation + * (Written by Steven J. Magnani <steve(a)digidescorp.com> for Digital Design Corp) + * Copyright (C) 2007 Corey Osgood <corey.osgood(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include "i82801xx.h" + +void i82801xx_enable(device_t dev) +{ + unsigned int index = 0; + uint16_t cur_disable_mask, new_disable_mask; + + // All 82801 devices should be on bus 0 + unsigned int devfn = PCI_DEVFN(0x1f, 0); // lpc + device_t lpc_dev = dev_find_slot(0, devfn); // 0 + if (!lpc_dev) + return; + + /* We're going to assume, perhaps incorrectly, that if a function exists + it can be disabled. Workarounds for ICH variants that don't follow this + should be done by checking the device ID */ + + if (PCI_SLOT(dev->path.u.pci.devfn) == 31) { + index = PCI_FUNC(dev->path.u.pci.devfn); + } else if (PCI_SLOT(dev->path.u.pci.devfn) == 29) { + index = 8 + PCI_FUNC(dev->path.u.pci.devfn); + } + + /* Function 0 is a bit of an exception */ + if(index == 0) + { + index = 14; + } + cur_disable_mask = pci_read_config16(lpc_dev, FUNC_DIS); + new_disable_mask = cur_disable_mask & ~(1 << index); // enable it + if (!dev->enabled) { + new_disable_mask |= (1 << index); // disable it, if desired + } + if (new_disable_mask != cur_disable_mask) { + pci_write_config16(lpc_dev, FUNC_DIS, new_disable_mask); + } +} + +struct chip_operations southbridge_intel_i82801xx_ops = { + CHIP_NAME("Intel i82801 Series Southbridge") + .enable_dev = i82801xx_enable, +}; Added: trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx.h =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx.h (rev 0) +++ trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx.h 2007-06-14 06:10:57 UTC (rev 2719) @@ -0,0 +1,106 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Corey Osgood <corey.osgood(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef I82801XX_H +#define I82801XX_H + +#ifndef __ROMCC__ +#include "chip.h" +extern void i82801xx_enable(device_t dev); +#endif + +#define PCI_DMA_CFG 0x90 +#define SERIRQ_CNTL 0x64 +#define GEN_CNTL 0xd0 +#define GEN_STS 0xd4 +#define RTC_CONF 0xd8 +#define GEN_PMCON_3 0xa4 + +#define PCICMD 0x04 +#define PMBASE 0x40 +#define PM_BASE_ADDR 0x1100 +#define ACPI_CNTL 0x44 +#define BIOS_CNTL 0x4E +#define GPIO_BASE 0x58 +#define GPIO_BASE_ADDR 0x1180 +#define GPIO_CNTL 0x5C +#define PIRQA_ROUT 0x60 +#define PIRQE_ROUT 0x68 +#define COM_DEC 0xE0 +#define LPC_EN 0xE6 +#define FUNC_DIS 0xF2 + +#define CMD 0x04 +#define SBUS_NUM 0x19 +#define SUB_BUS_NUM 0x1A +#define SMLT 0x1B +#define IOBASE 0x1C +#define IOLIM 0x1D +#define MEMBASE 0x20 +#define MEMLIM 0x22 +#define CNF 0x50 +#define MTT 0x70 +#define PCI_MAST_STS 0x82 + +// GEN_PMCON_3 bits +#define RTC_BATTERY_DEAD (1 << 2) +#define RTC_POWER_FAILED (1 << 1) +#define SLEEP_AFTER_POWER_FAIL (1 << 0) + +// PCI Configuration Space (D31:F1) +#define IDE_TIM_PRI 0x40 // IDE timings, primary +#define IDE_TIM_SEC 0x42 // IDE timings, secondary + +// IDE_TIM bits +#define IDE_DECODE_ENABLE (1 << 15) + +// PCI Configuration Space (D31:F3) +#define SMB_BASE 0x20 +#define HOSTC 0x40 + +// HOSTC bits +#define I2C_EN (1 << 2) +#define SMB_SMI_EN (1 << 1) +#define HST_EN (1 << 0) + +// SMBus IO bits +/* TODO: Does it matter where we put the SMBus IO base, as long as we keep + consistent and don't interfere with anything else? */ +//#define SMBUS_IO_BASE 0x1000 +#define SMBUS_IO_BASE 0x0f00 + +#define SMBHSTSTAT 0x0 +#define SMBHSTCTL 0x2 +#define SMBHSTCMD 0x3 +#define SMBXMITADD 0x4 +#define SMBHSTDAT0 0x5 +#define SMBHSTDAT1 0x6 +#define SMBBLKDAT 0x7 +#define SMBTRNSADD 0x9 +#define SMBSLVDATA 0xa +#define SMLINK_PIN_CTL 0xe +#define SMBUS_PIN_CTL 0xf + +#define SMBUS_TIMEOUT (10 * 1000 * 100) + +//HPET, if present +#define HPET_ADDR 0xfed0000 + +#endif /* I82801XX_H */ Added: trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_ac97.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_ac97.c (rev 0) +++ trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_ac97.c 2007-06-14 06:10:57 UTC (rev 2719) @@ -0,0 +1,113 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2005 Tyan Computer + * (Written by Yinghai Lu <yinghailu(a)gmail.com> for Tyan Computer) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include "i82801xx.h" + +static struct device_operations ac97_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = 0, + .enable = i82801xx_enable, +}; + +/* i82801aa */ +static struct pci_driver i82801aa_ac97_audio __pci_driver = { + .ops = &ac97_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x2415, +}; + +static struct pci_driver i82801aa_ac97_modem __pci_driver = { + .ops = &ac97_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x2416, +}; + +/* i82801ab */ +static struct pci_driver i82801ab_ac97_audio __pci_driver = { + .ops = &ac97_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x2425, +}; + +static struct pci_driver i82801ab_ac97_modem __pci_driver = { + .ops = &ac97_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x2426, +}; + +/* i82801ba */ +static struct pci_driver i82801ba_ac97_audio __pci_driver = { + .ops = &ac97_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x2445, +}; + +static struct pci_driver i82801ba_ac97_modem __pci_driver = { + .ops = &ac97_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x2446, +}; + +/* i82801ca */ +static struct pci_driver i82801ca_ac97_audio __pci_driver = { + .ops = &ac97_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x2485, +}; + +static struct pci_driver i82801ca_ac97_modem __pci_driver = { + .ops = &ac97_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x2486, +}; + +/* i82801db & i82801dbm */ +static struct pci_driver i82801db_ac97_audio __pci_driver = { + .ops = &ac97_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x24c5, +}; + +static struct pci_driver i82801db_ac97_modem __pci_driver = { + .ops = &ac97_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x24c6, +}; + +/* i82801eb & i82801er */ +static struct pci_driver i82801ex_ac97_audio __pci_driver = { + .ops = &ac97_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x24d5, +}; + +static struct pci_driver i82801ex_ac97_modem __pci_driver = { + .ops = &ac97_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x24d6, +}; Added: trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_early_smbus.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_early_smbus.c (rev 0) +++ trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_early_smbus.c 2007-06-14 06:10:57 UTC (rev 2719) @@ -0,0 +1,74 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2005 Tyan Computer + * (Written by Yinghai Lu <yinghailu(a)gmail.com> for Tyan Computer) + * Copyright (C) 2007 Corey Osgood <corey.osgood(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/pci_ids.h> +#include "i82801xx.h" +#include "i82801xx_smbus.h" + +static void enable_smbus(void) +{ + device_t dev; + uint16_t device_id; + + /* Set the SMBus device staticly */ + dev = PCI_DEV(0x0, 0x1f, 0x3); + + /* Check to make sure we've got the right device */ + device_id = pci_read_config16(dev, 0x2); + + /* Clear bits 7-4, since those are the only bits that vary between models */ + device_id &= 0xff0f; + + if(device_id != 0x2403) + { + die("Device not found, Corey probably screwed up!"); + } + + /* Set SMBus I/O base */ + pci_write_config32(dev, SMB_BASE, SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); + /* Set SMBus enable */ + pci_write_config8(dev, HOSTC, HST_EN); + /* Set SMBus I/O space enable */ + pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); + /* Disable interrupt generation */ + outb(0, SMBUS_IO_BASE + SMBHSTCTL); + /* Clear any lingering errors, so transactions can run */ + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); + print_debug("SMBus controller enabled\r\n"); +} + +static inline int smbus_read_byte(unsigned device, unsigned address) +{ + return do_smbus_read_byte(device, address); +} + +static void smbus_write_byte(unsigned device, unsigned address, unsigned char val) +{ + print_err("Unimplemented smbus_write_byte() called\r\n"); + return; +} + +static inline int smbus_write_block(unsigned device, unsigned length, unsigned cmd, + unsigned data1, unsigned data2) +{ + return do_smbus_write_block(device, length, cmd, data1, data2); +} Added: trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_ide.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_ide.c (rev 0) +++ trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_ide.c 2007-06-14 06:10:57 UTC (rev 2719) @@ -0,0 +1,113 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2005 Tyan Computer + * (Written by Yinghai Lu <yinghailu(a)gmail.com> for Tyan Computer) + * Copyright (C) 2005 Digital Design Corporation + * (Written by Steven J. Magnani <steve(a)digidescorp.com> for Digital Design Corp) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include "i82801xx.h" + +static void ide_init(struct device *dev) +{ + /* TODO: Needs to be tested for compatibility with ICH5(R) */ + /* Enable ide devices so the linux ide driver will work */ + uint16_t ideTimingConfig; + int enable_primary = 1; + int enable_secondary = 1; + + ideTimingConfig = pci_read_config16(dev, IDE_TIM_PRI); + ideTimingConfig &= ~IDE_DECODE_ENABLE; + if (enable_primary) { + /* Enable primary ide interface */ + ideTimingConfig |= IDE_DECODE_ENABLE; + printk_debug("IDE0 "); + } + pci_write_config16(dev, IDE_TIM_PRI, ideTimingConfig); + + ideTimingConfig = pci_read_config16(dev, IDE_TIM_SEC); + ideTimingConfig &= ~IDE_DECODE_ENABLE; + if (enable_secondary) { + /* Enable secondary ide interface */ + ideTimingConfig |= IDE_DECODE_ENABLE; + printk_debug("IDE1 "); + } + pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig); +} + +static struct device_operations ide_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = ide_init, + .scan_bus = 0, + .enable = i82801xx_enable, +}; + +/* i82801aa */ +static struct pci_driver i82801aa_ide __pci_driver = { + .ops = &ide_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x2411, +}; + +/* i82801ab */ +static struct pci_driver i82801ab_ide __pci_driver = { + .ops = &ide_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x2421, +}; + +/* i82801ba */ +static struct pci_driver i82801ba_ide __pci_driver = { + .ops = &ide_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x244b, +}; + +/* i82801ca */ +static struct pci_driver i82801ca_ide __pci_driver = { + .ops = &ide_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x248b, +}; + +/* i82801db */ +static struct pci_driver i82801db_ide __pci_driver = { + .ops = &ide_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x24cb, +}; + +/* i82801dbm */ +static struct pci_driver i82801dbm_ide __pci_driver = { + .ops = &ide_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x24ca, +}; + +/* i82801eb & i82801er */ +static struct pci_driver i82801ex_ide __pci_driver = { + .ops = &ide_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x24db, +}; Added: trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_lpc.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_lpc.c (rev 0) +++ trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_lpc.c 2007-06-14 06:10:57 UTC (rev 2719) @@ -0,0 +1,289 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2003 Linux Networx + * Copyright (C) 2003 SuSE Linux AG + * Copyright (C) 2005 Tyan Computer + * (Written by Yinghai Lu <yinghailu(a)gmail.com> for Tyan Computer) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* from i82801dbm, needs to be fixed to support everything the i82801er does */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <pc80/mc146818rtc.h> +#include <pc80/isa-dma.h> +#include <arch/io.h> +#include "i82801xx.h" + +#define NMI_OFF 0 + +void i82801xx_enable_ioapic( struct device *dev) +{ + uint32_t reg32; + volatile uint32_t *ioapic_index = (volatile uint32_t *)0xfec00000; + volatile uint32_t *ioapic_data = (volatile uint32_t *)0xfec00010; + + reg32 = pci_read_config32(dev, GEN_CNTL); + reg32 |= (3 << 7); /* Enable IOAPIC */ + reg32 |= (1 << 13); /* Coprocessor error enable */ + reg32 |= (1 << 1); /* Delayed transaction enable */ + reg32 |= (1 << 2); /* DMA collection buffer enable */ + pci_write_config32(dev, GEN_CNTL, reg32); + printk_debug("IOAPIC Southbridge enabled %x\n", reg32); + + *ioapic_index = 0; + *ioapic_data = (1 << 25); + + *ioapic_index = 0; + reg32 = *ioapic_data; + printk_debug("Southbridge APIC ID = %x\n", reg32); + if(reg32 != (1 << 25)) + die("APIC Error\n"); + + /* TODO: From i82801ca, needed/useful on other ICH? */ + *ioapic_index = 3; // Select Boot Configuration register + *ioapic_data = 1; // Use Processor System Bus to deliver interrupts +} + +void i82801xx_enable_serial_irqs( struct device *dev) +{ + /* set packet length and toggle silent mode bit */ + pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0 << 0)); + pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(0 << 6)|((21 - 17) << 2)|(0 << 0)); + /* TODO: Explain/#define the real meaning of these magic numbers ^^^ */ +} + +void i82801xx_lpc_route_dma( struct device *dev, uint8_t mask) +{ + uint16_t reg16; + int i; + reg16 = pci_read_config16(dev, PCI_DMA_CFG); + reg16 &= 0x300; + for(i = 0; i < 8; i++) { + if (i == 4) + continue; + reg16 |= ((mask & (1 << i))? 3:1) << (i * 2); + } + pci_write_config16(dev, PCI_DMA_CFG, reg16); +} + +void i82801xx_rtc_init(struct device *dev) +{//todo:needs serious cleanup/comments + uint8_t reg8; + uint32_t reg32; + int rtc_failed; + byte = pci_read_config8(dev, GEN_PMCON_3); + rtc_failed = byte & RTC_BATTERY_DEAD; + if (rtc_failed) { + reg8 &= ~(1 << 1); /* preserve the power fail state */ + pci_write_config8(dev, GEN_PMCON_3, reg8); + } + reg32 = pci_read_config32(dev, GEN_STS); + rtc_failed |= reg32 & (1 << 2); + rtc_init(rtc_failed); +} + + +void i82801xx_1f0_misc(struct device *dev) +{ + /* TODO: break this down into smaller functions */ + + //move to acpi_enable or something + /* Set ACPI base address to 0x1100 (I/O space) */ + pci_write_config32(dev, PMBASE, PM_BASE_ADDR | 1); + /* Enable ACPI I/O and power management */ + pci_write_config8(dev, ACPI_CNTL, 0x10); + /* Set GPIO base address to 0x1180 (I/O space) */ + pci_write_config32(dev, GPIO_BASE, GPIO_BASE_ADDR | 1); + /* Enable GPIO */ + pci_write_config8(dev, GPIO_CNTL, 0x10); + + //get rid of? + /* Route PIRQA to IRQ11, PIRQB to IRQ3, PIRQC to IRQ5, PIRQD to IRQ10 */ + pci_write_config32(dev, PIRQA_ROUT, 0x0A05030B); + /* Route PIRQE to IRQ7. Leave PIRQF - PIRQH unrouted */ + pci_write_config8(dev, PIRQE_ROUT, 0x07); + + //move to i82801xx_init + /* Prevent LPC disabling, enable parity errors, and SERR# (System Error) */ + pci_write_config16(dev, PCI_COMMAND, 0x014f); + /* Enable access to the upper 128 byte bank of CMOS RAM */ + pci_write_config8(dev, RTC_CONF, 0x04); + /* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB */ + pci_write_config8(dev, COM_DEC, 0x10); + /* LPT decode defaults to 0x378-0x37F and 0x778-0x77F + * Floppy decode defaults to 0x3F0-0x3F5, 0x3F7 */ + /* Enable: COMA, COMB, LPT, Floppy + * Disable: Microcontroller, Sound, Gameport */ + pci_write_config16(dev, LPC_EN, 0x000F); +} + +static void enable_hpet(struct device *dev) +{ +#ifdef HPET_PRESENT + uint32_t reg32; + uint32_t code = (0 & 0x3); + + reg32 = pci_read_config32(dev, GEN_CNTL); + reg32 |= (1 << 17); /* Enable HPET */ + /*Bits [16:15]Memory Address Range + 00 FED0_0000h - FED0_03FFh + 01 FED0_1000h - FED0_13FFh + 10 FED0_2000h - FED0_23FFh + 11 FED0_3000h - FED0_33FFh*/ + + reg32 &= ~(3 << 15); /* Clear it */ + reg32 |= (code << 15); + /* reg32 is never written to anywhere?? */ + printk_debug("Enabling HPET @0x%x\n", HPET_ADDR | (code << 12)); +#endif +} + + +static void lpc_init(struct device *dev) +{ + uint8_t byte; + int pwr_on = -1; + int nmi_option; + + /* IO APIC initialization */ + i82801xx_enable_ioapic(dev); + + i82801xx_enable_serial_irqs(dev); + + /* TODO: Find out if this is being used/works */ +#ifdef SUSPICIOUS_LOOKING_CODE + /* The ICH-4 datasheet does not mention this configuration register. */ + /* This code may have been inherited (incorrectly) from code for + the AMD 766 southbridge, which *does* support this functionality. */ + + /* Posted memory write enable */ + byte = pci_read_config8(dev, 0x46); + pci_write_config8(dev, 0x46, byte | (1<<0)); +#endif + + /* power after power fail */ + /* FIXME this doesn't work! */ + /* Which state do we want to goto after g3 (power restored)? + * 0 == S0 Full On + * 1 == S5 Soft Off + */ + pci_write_config8(dev, GEN_PMCON_3, pwr_on?0:1); + printk_info("Set power %s if power fails\n", pwr_on?"on":"off"); + + /* Set up NMI on errors */ + byte = inb(0x61); + byte &= ~(1 << 3); /* IOCHK# NMI Enable */ + byte &= ~(1 << 2); /* PCI SERR# Enable */ + outb(byte, 0x61); + byte = inb(0x70); + + nmi_option = NMI_OFF; + get_option(&nmi_option, "nmi"); + if (nmi_option) { + byte &= ~(1 << 7); /* set NMI */ + outb(byte, 0x70); + } + + /* Initialize the real time clock */ + i82801xx_rtc_init(dev); + + i82801xx_lpc_route_dma(dev, 0xff); + + /* Initialize isa dma */ + isa_dma_init(); + + i82801xx_1f0_misc(dev); + /* Initialize the High Precision Event Timers, if present */ + enable_hpet(dev); +} + +static void i82801xx_lpc_read_resources(device_t dev) +{ + struct resource *res; + + /* Get the normal pci resources of this device */ + pci_dev_read_resources(dev); + + /* Add an extra subtractive resource for both memory and I/O */ + res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + + res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; +} + +static void i82801xx_lpc_enable_resources(device_t dev) +{ + pci_dev_enable_resources(dev); + enable_childrens_resources(dev); +} + +static struct device_operations lpc_ops = { + .read_resources = i82801xx_lpc_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = i82801xx_lpc_enable_resources, + .init = lpc_init, + .scan_bus = scan_static_bus, + .enable = i82801xx_enable, +}; + +static struct pci_driver i82801aa_lpc __pci_driver = { + .ops = &lpc_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x2410, +}; + +static struct pci_driver i82801ab_lpc __pci_driver = { + .ops = &lpc_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x2420, +}; + +static struct pci_driver i82801ba_lpc __pci_driver = { + .ops = &lpc_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x2440, +}; + +static struct pci_driver i82801ca_lpc __pci_driver = { + .ops = &lpc_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x2480, +}; + +static struct pci_driver i82801db_lpc __pci_driver = { + .ops = &lpc_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x24c0, +}; + +static struct pci_driver i82801dbm_lpc __pci_driver = { + .ops = &lpc_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x24cc, +}; + +/* i82801eb and er */ +static struct pci_driver i82801ex_lpc __pci_driver = { + .ops = &lpc_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x24d0, +}; Added: trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_nic.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_nic.c (rev 0) +++ trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_nic.c 2007-06-14 06:10:57 UTC (rev 2719) @@ -0,0 +1,44 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Corey Osgood <corey.osgood(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +static struct device_operations nic_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = 0, +}; + +static struct pci_driver i82801dbm_nic __pci_driver = { + .ops = &nic_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x103a, +}; + +static struct pci_driver i82801ex_nic __pci_driver = { + .ops = &nic_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x1051, +}; Added: trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_pci.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_pci.c (rev 0) +++ trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_pci.c 2007-06-14 06:10:57 UTC (rev 2719) @@ -0,0 +1,80 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2005 Tyan Computer + * (Written by Yinghai Lu <yinghailu(a)gmail.com> for Tyan Computer) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +static void pci_init(struct device *dev) +{ + uint32_t reg32; + uint16_t reg16; + + /* Clear system errors */ + reg16 = pci_read_config16(dev, 0x06); + reg16 |= 0xf900; /* Clear possible errors */ + pci_write_config16(dev, 0x06, reg16); + + /* i82801er has this commented out, wonder why? */ + /* System error enable */ + reg32 = pci_read_config32(dev, 0x04); + reg32 |= (1 << 8); /* SERR# Enable */ + reg32 |= (1 << 6); /* Parity Error Response */ + pci_write_config32(dev, 0x04, reg32); + + reg16 = pci_read_config16(dev, 0x1e); + reg16 |= 0xf800; /* Clear possible errors */ + pci_write_config16(dev, 0x1e, reg16); +} + +static struct device_operations pci_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = pci_init, + .scan_bus = pci_scan_bridge, +}; + +static struct pci_driver i82801aa_pci __pci_driver = { + .ops = &pci_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x2418, +}; + +static struct pci_driver i82801ab_pci __pci_driver = { + .ops = &pci_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x2428, +}; + +/* i82801ba, ca, db, eb, and er */ +static struct pci_driver i82801misc_pci __pci_driver = { + .ops = &pci_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x244e, +}; + +static struct pci_driver i82801dbm_pci __pci_driver = { + .ops = &pci_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x2448, +}; Added: trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_reset.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_reset.c (rev 0) +++ trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_reset.c 2007-06-14 06:10:57 UTC (rev 2719) @@ -0,0 +1,27 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2002 Eric Biederman <ebiederm(a)xmission.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> + +void hard_reset(void) +{ + /* Try rebooting through port 0xcf9 */ + outb((1 << 2)|(1 << 1), 0xcf9); +} Added: trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_sata.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_sata.c (rev 0) +++ trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_sata.c 2007-06-14 06:10:57 UTC (rev 2719) @@ -0,0 +1,82 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2005 Tyan Computer + * (Written by Yinghai Lu <yinghailu(a)gmail.com> for Tyan Computer) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include "i82801xx.h" + +/* TODO: set dynamically, if the user only wants one sata channel or none at all */ + +static void sata_init(struct device *dev) +{ + /* SATA configuration */ + pci_write_config8(dev, 0x04, 0x07); + pci_write_config8(dev, 0x09, 0x8f); + + /* Set timmings */ + pci_write_config16(dev, 0x40, 0x0a307); + pci_write_config16(dev, 0x42, 0x0a307); + + /* Sync DMA */ + pci_write_config16(dev, 0x48, 0x000f); + pci_write_config16(dev, 0x4a, 0x1111); + + /* 66 mhz */ + pci_write_config16(dev, 0x54, 0xf00f); + + /* Combine ide - sata configuration */ + pci_write_config8(dev, 0x90, 0x0); + + /* port 0 & 1 enable */ + pci_write_config8(dev, 0x92, 0x33); + + /* initialize SATA */ + pci_write_config16(dev, 0xa0, 0x0018); + pci_write_config32(dev, 0xa4, 0x00000264); + pci_write_config16(dev, 0xa0, 0x0040); + pci_write_config32(dev, 0xa4, 0x00220043); +} + +static struct device_operations sata_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = sata_init, + .scan_bus = 0, + .enable = i82801xx_enable, +}; + +/* i82801eb */ +static struct pci_driver i82801eb_sata_driver __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x24d1, +}; + +/* i82801er */ +static struct pci_driver i82801er_sata_driver __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x24df, +}; Added: trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_smbus.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_smbus.c (rev 0) +++ trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_smbus.c 2007-06-14 06:10:57 UTC (rev 2719) @@ -0,0 +1,94 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2005 Yinghai Lu <yinghailu(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <smbus.h> +#include <pci.h> +#include <arch/io.h> +#include "i82801_model_specific.h" +#include "i82801xx.h" +#include "i82801_smbus.h" + +static int smbus_read_byte(struct bus *bus, device_t dev, uint8_t address) +{ + unsigned device; + struct resource *res; + + device = dev->path.u.i2c.device; + res = find_resource(bus->dev, 0x20); + + return do_smbus_read_byte(res->base, device, address); +} + +static struct smbus_bus_operations lops_smbus_bus = { + .read_byte = smbus_read_byte, +}; + +static struct device_operations smbus_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = scan_static_bus, + .enable = i82801er_enable, + .ops_smbus_bus = &lops_smbus_bus, +}; + +/* i82801aa */ +static struct pci_driver smbus_driver __pci_driver = { + .ops = &smbus_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x2413, +}; + +/* i82801ab */ +static struct pci_driver smbus_driver __pci_driver = { + .ops = &smbus_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x2423, +}; + +/* i82801ba */ +static struct pci_driver smbus_driver __pci_driver = { + .ops = &smbus_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x2443, +}; + +/* i82801ca */ +static struct pci_driver smbus_driver __pci_driver = { + .ops = &smbus_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x2483, +}; + +/* i82801db and i82801dbm */ +static struct pci_driver smbus_driver __pci_driver = { + .ops = &smbus_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x24c3, +}; + +/* i82801eb and i82801er */ +static struct pci_driver smbus_driver __pci_driver = { + .ops = &smbus_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x24d3, +}; + Added: trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_smbus.h =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_smbus.h (rev 0) +++ trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_smbus.h 2007-06-14 06:10:57 UTC (rev 2719) @@ -0,0 +1,181 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2005 Yinghai Lu <yinghailu(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/smbus_def.h> + +static void smbus_delay(void) +{ + inb(0x80); +} + +static int smbus_wait_until_ready(void) +{ + unsigned loops = SMBUS_TIMEOUT; + unsigned char byte; + do { + smbus_delay(); + if (--loops == 0) + break; + byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); + } while(byte & 1); + return loops?0:-1; +} + +static int smbus_wait_until_done(void) +{ + unsigned loops = SMBUS_TIMEOUT; + unsigned char byte; + do { + smbus_delay(); + if (--loops == 0) + break; + byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); + } while((byte & 1) || (byte & ~((1<<6)|(1<<0))) == 0); + return loops?0:-1; +} + +static int smbus_wait_until_blk_done(void) +{ + unsigned loops = SMBUS_TIMEOUT; + unsigned char byte; + do { + smbus_delay(); + if (--loops == 0) + break; + byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); + } while((byte & (1 << 7)) == 0); + return loops?0:-1; +} + +static int do_smbus_read_byte(unsigned device, unsigned address) +{ + unsigned char global_status_register; + unsigned char byte; + + if (smbus_wait_until_ready() < 0) { + return SMBUS_WAIT_UNTIL_READY_TIMEOUT; + } + /* Setup transaction */ + /* Disable interrupts */ + outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL); + /* Set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBXMITADD); + /* Set the command/address... */ + outb(address & 0xff, SMBUS_IO_BASE + SMBHSTCMD); + /* Set up for a byte data read */ + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2 << 2), (SMBUS_IO_BASE + SMBHSTCTL)); + /* Clear any lingering errors, so the transaction will run */ + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); + + /* Clear the data byte...*/ + outb(0, SMBUS_IO_BASE + SMBHSTDAT0); + + /* Start the command */ + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL); + + /* Poll for transaction completion */ + if (smbus_wait_until_done() < 0) { + return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; + } + + global_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT); + + /* Ignore the "In Use" status... */ + global_status_register &= ~(3 << 5); + + /* Read results of transaction */ + byte = inb(SMBUS_IO_BASE + SMBHSTDAT0); + if (global_status_register != (1 << 1)) { + return SMBUS_ERROR; + } + return byte; +} + +/* This function is neither used nor tested by me (Corey Osgood), the author +(Yinghai) probably tested/used it on i82801er */ +static int do_smbus_write_block(unsigned device, unsigned length, unsigned cmd, + unsigned data1, unsigned data2) +{ +#warning "do_smbus_write_block is commented out" + print_err("Untested smbus_write_block called\r\n"); +#if 0 + unsigned char global_control_register; + unsigned char global_status_register; + unsigned char byte; + unsigned char stat; + int i; + + /* Clear the PM timeout flags, SECOND_TO_STS */ + outw(inw(0x0400 + 0x66), 0x0400 + 0x66); + + if (smbus_wait_until_ready(SMBUS_IO_BASE) < 0) { + return -2; + } + + /* Setup transaction */ + /* Obtain ownership */ + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); + for(stat = 0; (stat & 0x40) == 0; ) { + stat = inb(SMBUS_IO_BASE + SMBHSTSTAT); + } + /* Clear the done bit */ + outb(0x80, SMBUS_IO_BASE + SMBHSTSTAT); + /* Disable interrupts */ + outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL); + + /* Set the device I'm talking too */ + outb(((device & 0x7f) << 1), SMBUS_IO_BASE + SMBXMITADD); + + /* Set the command address */ + outb(cmd & 0xff, SMBUS_IO_BASE + SMBHSTCMD); + + /* Set the block length */ + outb(length & 0xff, SMBUS_IO_BASE + SMBHSTDAT0); + + /* Try sending out the first byte of data here */ + byte = (data1 >> (0)) & 0x0ff; + outb(byte, SMBUS_IO_BASE + SMBBLKDAT); + /* Issue a block write command */ + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x5 << 2) | 0x40, + SMBUS_IO_BASE + SMBHSTCTL); + + for(i = 0;i < length; i++) { + + /* Poll for transaction completion */ + if (smbus_wait_until_blk_done(SMBUS_IO_BASE) < 0) { + return -3; + } + + /* Load the next byte */ + if(i > 3) + byte = (data2 >> (i % 4)) & 0x0ff; + else + byte = (data1 >> (i)) & 0x0ff; + outb(byte, SMBUS_IO_BASE + SMBBLKDAT); + + /* Clear the done bit */ + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), + SMBUS_IO_BASE + SMBHSTSTAT); + } + + print_debug("SMBUS Block complete\r\n"); + return 0; +#endif +} Added: trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_usb.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_usb.c (rev 0) +++ trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_usb.c 2007-06-14 06:10:57 UTC (rev 2719) @@ -0,0 +1,130 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Corey Osgood <corey.osgood(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include "i82801xx.h" + +static void usb_init(struct device *dev) +{ +/* TODO: Any init needed? Some ports have it, others don't */ +} + +static struct device_operations usb_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = usb_init, + .scan_bus = 0, + .enable = i82801xx_enable, +}; + +/* i82801aa */ +static struct pci_driver i82801aa_usb_1 __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x2412, +}; + +/* i82801ab */ +static struct pci_driver i82801ab_usb_1 __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x2422, +}; + +/* i82801ba */ +static struct pci_driver i82801ba_usb_1 __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x2442, +}; + +static struct pci_driver i82801ba_usb_2 __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x2444, +}; + +/* i82801ca */ +static struct pci_driver i82801ca_usb_1 __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x2482, +}; + +static struct pci_driver i82801ca_usb_2 __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x2484, +}; + +static struct pci_driver i82801ca_usb_3 __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x2487, +}; + +/* i82801db and i82801dbm */ +static struct pci_driver i82801db_usb_1 __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x24c2, +}; + +static struct pci_driver i82801db_usb_2 __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x24c4, +}; + +static struct pci_driver i82801db_usb_3 __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x24c7, +}; + +/* i82801eb and i82801er */ +static struct pci_driver i82801ex_usb_1 __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x24d2, +}; + +static struct pci_driver i82801ex_usb_2 __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x24d4, +}; + +static struct pci_driver i82801ex_usb_3 __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x24d7, +}; + +static struct pci_driver i82801ex_usb_4 __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x24de, +}; Added: trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_usb_ehci.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_usb_ehci.c (rev 0) +++ trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_usb_ehci.c 2007-06-14 06:10:57 UTC (rev 2719) @@ -0,0 +1,81 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2005 Tyan Computer + * (Written by Yinghai Lu <yinghailu(a)gmail.com> for Tyan Computer> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include "i82801xx.h" + +static void usb_ehci_init(struct device *dev) +{ + /* TODO: Is any special init really needed? */ + uint32_t cmd; + + printk_debug("EHCI: Setting up controller.. "); + cmd = pci_read_config32(dev, PCI_COMMAND); + pci_write_config32(dev, PCI_COMMAND, + cmd | PCI_COMMAND_MASTER); + + printk_debug("done.\n"); +} + +static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + uint8_t access_cntl; + access_cntl = pci_read_config8(dev, 0x80); + /* Enable writes to protected registers */ + pci_write_config8(dev, 0x80, access_cntl | 1); + /* Write the subsystem vendor and device id */ + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); + /* Restore protection */ + pci_write_config8(dev, 0x80, access_cntl); +} + +static struct pci_operations lops_pci = { + .set_subsystem = &usb_ehci_set_subsystem, +}; + +static struct device_operations usb_ehci_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = usb_ehci_init, + .scan_bus = 0, + .enable = i82801xx_enable, + .ops_pci = &lops_pci, +}; + +/* i82801db and i82801dbm */ +static struct pci_driver i82801db_usb_ehci __pci_driver = { + .ops = &usb_ehci_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x24cd, +}; + +/* i82801eb and i82801er */ +static struct pci_driver i82801ex_usb_ehci __pci_driver = { + .ops = &usb_ehci_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x24dd, +}; Added: trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_watchdog.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_watchdog.c (rev 0) +++ trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_watchdog.c 2007-06-14 06:10:57 UTC (rev 2719) @@ -0,0 +1,51 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2006 John Dufresne <jon.dufresne(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <console/console.h> +#include <arch/io.h> +#include <device/device.h> +#include <device/pci.h> + +/* TODO: I'm fairly sure the same functionality is provided elsewhere */ + +void watchdog_off(void) +{ + device_t dev; + unsigned long value,base; + + /* turn off the ICH5 watchdog */ + dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); + + /* Enable I/O space */ + value = pci_read_config16(dev, 0x04); + value |= (1 << 10); + pci_write_config16(dev, 0x04, value); + /* Get TCO base */ + base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60; + /* Disable the watchdog timer */ + value = inw(base + 0x08); + value |= 1 << 11; + outw(value, base + 0x08); + /* Clear TCO timeout status */ + outw(0x0008, base + 0x04); + outw(0x0002, base + 0x06); + printk_debug("ICH Watchdog disabled\r\n"); +} + + Added: trunk/LinuxBIOSv2/targets/asus/mew-vm/Config.lb =================================================================== --- trunk/LinuxBIOSv2/targets/asus/mew-vm/Config.lb (rev 0) +++ trunk/LinuxBIOSv2/targets/asus/mew-vm/Config.lb 2007-06-14 06:10:57 UTC (rev 2719) @@ -0,0 +1,28 @@ +# Config file for asus mew-vm board +# This will make a target directory of ./mew-vm + +target mew-vm +mainboard asus/mew-vm + +## Without VGA BIOS +option ROM_SIZE = 512 * 1024 +## With VGA BIOS (32k) +#option ROM_SIZE = (512 * 1024) - (32 * 1024) + +romimage "normal" + option USE_FALLBACK_IMAGE=0 + option ROM_IMAGE_SIZE=0x10000 + option LINUXBIOS_EXTRA_VERSION=".0Normal" +# payload /etc/hosts + payload /home/amp/filo-0.5/filo.elf +end + +romimage "fallback" + option USE_FALLBACK_IMAGE=1 + option ROM_IMAGE_SIZE=0x10000 + option LINUXBIOS_EXTRA_VERSION=".0Fallback" +# payload /etc/hosts + payload /home/amp/filo-0.5/filo.elf +end + +buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"

1 0

Re: [LinuxBIOS] r349 - LinuxBIOSv3/include
by Peter Stuge 13 Jun '07

13 Jun '07

On Thu, Jun 07, 2007 at 07:34:17PM +0200, svn(a)openbios.org wrote: > +void ram_initialize(int controllers, void *ctrl); I never got any comment on that void * - why was it memory controllers could not have a unified struct? //Peter

4 17

Re: [LinuxBIOS] EPIA hang after patch
by ben＠hewson-venieri.co.uk 13 Jun '07

13 Jun '07

Can you try using just 1 memory module to start with and see if that helps. >Hi! > >I checked out r2717 and at first it behaved like Markus Boas Epia V >but then I applied Ben's patch to the vt8231_early_serial.c and it >booted into filo, once, then hanged at the dram setup. then I applied >the vt8231_lpc.c patch and it hangs on this: > >LinuxBIOS-2.0.0.0Normal Mon Jun 11 22:28:57 CEST 2007 starting... >87 is the comm register >SMBus controller enabled >vt8601 init starting >00000000 is the north > 1106 0601 >0120d4 is the computed timing > NOP >PRECHARGE >DUMMY READS >CBR >MRS >NORMAL >set ref. rate >enable multi-page open >Slot 00 is SDRAM 10000000 bytes >000e is the MA type >Slot 01 is SDRAM 08000000 bytes x2 >000c is the MA type >Slot 02 is empty >Slot 03 is empty >vt8601 done >Copying LinuxBIOS to RAM. >Jumping to LinuxBIOS. >LinuxBIOS-2.0.0.0Normal Mon Jun 11 22:28:57 CEST 2007 booting... >Enumerating buses... >scan_static_bus for Root Device >Finding PCI configuration type. >PCI: Using configuration type 1 >PCI_DOMAIN: 0000 enabled >APIC_CLUSTER: 0 enabled >PCI_DOMAIN: 0000 scanning... >PCI: pci_scan_bus for bus 00 >PCI: 00:00.0 [1106/0601] ops >PCI: 00:00.0 [1106/0601] enabled >malloc Enter, size 668, free_mem_ptr 00018000 >malloc 0x00018000 >Capability: 0x07 @ 0x80 >Capability: 0x08 @ 0x80 >Capability: 0x10 @ 0x80 >PCI: 00:01.0 [1106/8601] enabled >PCI: devfn 0x10, bad id 0xffffffff >PCI: devfn 0x18, bad id 0xffffffff >PCI: devfn 0x20, bad id 0xffffffff >PCI: devfn 0x28, bad id 0xffffffff >PCI: devfn 0x30, bad id 0xffffffff >PCI: devfn 0x38, bad id 0xffffffff >PCI: devfn 0x40, bad id 0xffffffff >PCI: devfn 0x48, bad id 0xffffffff >PCI: devfn 0x50, bad id 0xffffffff >PCI: devfn 0x58, bad id 0xffffffff >PCI: devfn 0x60, bad id 0xffffffff >PCI: devfn 0x68, bad id 0xffffffff >PCI: devfn 0x70, bad id 0xffffffff >PCI: devfn 0x78, bad id 0xffffffff >PCI: devfn 0x80, bad id 0xffffffff >PCI: 00:11.0 [1106/8231] bus ops >PCI: 00:11.0 [1106/8231] enabled >PCI: 00:11.1 [1106/0571] ops >PCI: 00:11.1 [1106/0571] enabled >PCI: 00:11.2 [1106/3038] disabled >PCI: 00:11.3 [1106/3038] disabled >PCI: 00:11.4 [1106/8235] ops >PCI: 00:11.4 [1106/8235] disabled >PCI: 00:11.5 [1106/3058] disabled >PCI: 00:11.6 [1106/3068] enabled >PCI: devfn 0x8f, bad id 0xffffffff >PCI: 00:12.0 [1106/3065] ops >PCI: 00:12.0 [1106/3065] enabled >PCI: devfn 0x98, bad id 0xffffffff >malloc Enter, size 668, free_mem_ptr 0001829c >malloc 0x0001829c >PCI: 00:14.0 [1106/3065] ops >PCI: 00:14.0 [1106/3065] enabled >PCI: devfn 0xa8, bad id 0xffffffff >PCI: devfn 0xb0, bad id 0xffffffff >PCI: devfn 0xb8, bad id 0xffffffff >PCI: devfn 0xc0, bad id 0xffffffff >PCI: devfn 0xc8, bad id 0xffffffff >PCI: devfn 0xd0, bad id 0xffffffff >PCI: devfn 0xd8, bad id 0xffffffff >PCI: devfn 0xe0, bad id 0xffffffff >PCI: devfn 0xe8, bad id 0xffffffff >PCI: devfn 0xf0, bad id 0xffffffff >PCI: devfn 0xf8, bad id 0xffffffff >do_pci_scan_bridge for PCI: 00:01.0 >PCI: pci_scan_bus for bus 01 >PCI: devfn 0x0, bad id 0xffffffff >PCI: devfn 0x8, bad id 0xffffffff >PCI: devfn 0x10, bad id 0xffffffff >PCI: devfn 0x18, bad id 0xffffffff >PCI: devfn 0x20, bad id 0xffffffff >PCI: devfn 0x28, bad id 0xffffffff >PCI: devfn 0x30, bad id 0xffffffff >PCI: devfn 0x38, bad id 0xffffffff >PCI: devfn 0x40, bad id 0xffffffff >PCI: devfn 0x48, bad id 0xffffffff >PCI: devfn 0x50, bad id 0xffffffff >PCI: devfn 0x58, bad id 0xffffffff >PCI: devfn 0x60, bad id 0xffffffff >PCI: devfn 0x68, bad id 0xffffffff >PCI: devfn 0x70, bad id 0xffffffff >PCI: devfn 0x78, bad id 0xffffffff >PCI: devfn 0x80, bad id 0xffffffff >PCI: devfn 0x88, bad id 0xffffffff >PCI: devfn 0x90, bad id 0xffffffff >PCI: devfn 0x98, bad id 0xffffffff >PCI: devfn 0xa0, bad id 0xffffffff >PCI: devfn 0xa8, bad id 0xffffffff >PCI: devfn 0xb0, bad id 0xffffffff >PCI: devfn 0xb8, bad id 0xffffffff >PCI: devfn 0xc0, bad id 0xffffffff >PCI: devfn 0xc8, bad id 0xffffffff >PCI: devfn 0xd0, bad id 0xffffffff >PCI: devfn 0xd8, bad id 0xffffffff >PCI: devfn 0xe0, bad id 0xffffffff >PCI: devfn 0xe8, bad id 0xffffffff >PCI: devfn 0xf0, bad id 0xffffffff >PCI: devfn 0xf8, bad id 0xffffffff >PCI: pci_scan_bus returning with max=001 >do_pci_scan_bridge returns max 1 >scan_static_bus for PCI: 00:11.0 >malloc Enter, size 668, free_mem_ptr 00018538 >malloc 0x00018538 >malloc Enter, size 668, free_mem_ptr 000187d4 >malloc 0x000187d4 >malloc Enter, size 668, free_mem_ptr 00018a70 >malloc 0x00018a70 >malloc Enter, size 668, free_mem_ptr 00018d0c >malloc 0x00018d0c >malloc Enter, size 668, free_mem_ptr 00018fa8 >malloc 0x00018fa8 >malloc Enter, size 668, free_mem_ptr 00019244 >malloc 0x00019244 >malloc Enter, size 668, free_mem_ptr 000194e0 >malloc 0x000194e0 >malloc Enter, size 668, free_mem_ptr 0001977c >malloc 0x0001977c >malloc Enter, size 668, free_mem_ptr 00019a18 >malloc 0x00019a18 >malloc Enter, size 668, free_mem_ptr 00019cb4 >malloc 0x00019cb4 >malloc Enter, size 668, free_mem_ptr 00019f50 >malloc 0x00019f50 >PNP: 002e.0 disabled >PNP: 002e.1 disabled >PNP: 002e.2 enabled >PNP: 002e.3 disabled >PNP: 002e.5 enabled >PNP: 002e.6 disabled >PNP: 002e.7 disabled >PNP: 002e.8 disabled >PNP: 002e.9 disabled >PNP: 002e.a disabled >PNP: 002e.b enabled >PNP: 607a.0 enabled >PNP: 607a.1 enabled >PNP: 607a.2 enabled >PNP: 607a.3 enabled >PNP: 607a.5 enabled >PNP: 607a.6 enabled >PNP: 607a.7 enabled >PNP: 607a.8 enabled >PNP: 607a.9 enabled >PNP: 607a.a enabled >PNP: 607a.b enabled >scan_static_bus for PCI: 00:11.0 done >PCI: pci_scan_bus returning with max=001 >Unexpected Exception: 6 @ 10:e2c3f00a - Halting >Code: 0 eflags: 00010093 >eax: ffffff00 ebx: 00000000 ecx: 000003f8 edx: 00017eec >edi: 00000000 esi: 00000000 ebp: 00000000 esp: 00010004 > > >Any ideas would be great! > >Thanks! >/Thomas > >-- >linuxbios mailing list >linuxbios(a)linuxbios.org >http://www.linuxbios.org/mailman/listinfo/linuxbios

4 3

[LinuxBIOS] [PATCH] Intel 82371EB improvements
by Uwe Hermann 13 Jun '07

13 Jun '07

See patch. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

1 0

[LinuxBIOS] r2718 build service
by LinuxBIOS information 13 Jun '07

13 Jun '07

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "uwe" checked in revision 2718 to the LinuxBIOS source repository and caused the following changes: Change Log: Add the AMD DB800 (AKA Salsa) mainboard. The DB800 is the AMD LX Reference Design Kit platform. For details see: http://www.amd.com/geodelxdb800 Signed-off-by: Marc Jones <marc.jones(a)amd.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of arima:hdama is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2718&device=hdama&vendor=… Configuration of artecgroup:dbe61 is still broken Compilation of ibm:e325 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2718&device=e325&vendor=i… Compilation of ibm:e326 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2718&device=e326&vendor=i… Compilation of iei:juki-511p is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2718&device=juki-511p&ven… Compilation of iwill:dk8s2 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2718&device=dk8s2&vendor=… Compilation of iwill:dk8x is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2718&device=dk8x&vendor=i… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, LinuxBIOS automatic build system

1 0

[LinuxBIOS] [PATCH] AMD DB800 mainboard
by Marc Jones 13 Jun '07

13 Jun '07

Add the AMD DB800 (AKA Salsa) mainboard. The DB800 is the AMD LX Reference Design Kit platform. For details see: http://www.amd.com/geodelxdb800 Signed-off-by: Marc Jones <marc.jones(a)amd.com> -- Marc Jones Senior Software Engineer (970) 226-9684 Office mailto:Marc.Jones@amd.com http://www.amd.com/embeddedprocessors Add the AMD DB800 (AKA Salsa) mainboard. The DB800 is the AMD LX Reference Design Kit platform. For details see: http://www.amd.com/geodelxdb800 Signed-off-by: Marc Jones <marc.jones(a)amd.com> Index: LinuxBIOSv2/src/mainboard/amd/db800/Config.lb =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ LinuxBIOSv2/src/mainboard/amd/db800/Config.lb 2007-06-04 16:24:25.000000000 -0600 @@ -0,0 +1,189 @@ +## +## Compute the location and size of where this firmware image +## (linuxBIOS plus bootloader) will live in the boot rom chip. +## +if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) +else + default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) + default ROM_SECTION_OFFSET = 0 +end + +## +## Compute the start location and size size of +## The linuxBIOS bootloader. +## + +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) +default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) + +## +## Compute where this copy of linuxBIOS will start in the boot rom +## +default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) + +## +## Compute a range of ROM that can cached to speed up linuxBIOS, +## execution speed. +## +## XIP_ROM_SIZE must be a power of 2. +## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE +## +default XIP_ROM_SIZE=65536 +default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) + + +## +## Set all of the defaults for an x86 architecture +## + +arch i386 end + +## +## Build the objects we have code for in this directory. +## + +driver mainboard.o + +if HAVE_PIRQ_TABLE + object irq_tables.o +end + +if USE_DCACHE_RAM + #compile cache_as_ram.c to auto.inc + makerule ./cache_as_ram_auto.inc + depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@" + action "perl -e 's/.rodata/.rom.data/g' -pi $@" + action "perl -e 's/.text/.section .rom.text/g' -pi $@" + end +end + + +## +## Build our 16 bit and 32 bit linuxBIOS entry code +## +mainboardinit cpu/x86/16bit/entry16.inc +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/16bit/entry16.lds +ldscript /cpu/x86/32bit/entry32.lds + +## +## Build our reset vector (This is where linuxBIOS is entered) +## +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds +else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds +end + +### Should this be in the northbridge code? +#not in serengeti_cheetah mainboardinit arch/i386/lib/cpu_reset.inc + +## +## Include an id string (For safe flashing) +## +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds + +### +### This is the early phase of linuxBIOS startup +### Things are delicate and we test to see if we should +### failover to another image. +### +if USE_FALLBACK_IMAGE + ldscript /arch/i386/lib/failover.lds +# mainboardinit ./failover.inc +end + +### +### O.k. We aren't just an intermediary anymore! +### + +## +## Setup RAM +## +mainboardinit cpu/x86/fpu/enable_fpu.inc + +if USE_DCACHE_RAM + mainboardinit cpu/amd/model_lx/cache_as_ram.inc + mainboardinit ./cache_as_ram_auto.inc +end + +## +## Include the secondary Configuration files +## +dir /pc80 +config chip.h + +chip northbridge/amd/lx + device pci_domain 0 on + device pci 1.0 on end # Northbridge + device pci 1.1 on end # Graphics + chip southbridge/amd/cs5536 + # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK + # SIRQ Mode = Active(Quiet) mode. Save power.... + # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK + register "lpc_serirq_enable" = "0x000010da" + register "lpc_serirq_polarity" = "0x0000EF25" + register "lpc_serirq_mode" = "1" + register "enable_gpio_int_route" = "0x0D0C0700" + register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash + register "enable_USBP4_device" = "1" #0: host, 1:device + register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) + register "com1_enable" = "0" + register "com1_address" = "0x3F8" + register "com1_irq" = "4" + register "com2_enable" = "0" + register "com2_address" = "0x2F8" + register "com2_irq" = "3" + register "unwanted_vpci[0]" = "0" # End of list has a zero + device pci d.0 on end # Ethernet + device pci e.0 on end # Slot1 + device pci f.0 on # ISA Bridge + chip superio/winbond/w83627hf + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # Com2 + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GAME_MIDI_GIPO1 + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b off end # HW Monitor + end + end + device pci f.2 on end # IDE Controller + device pci f.3 on end # Audio + device pci f.4 on end # OHCI + device pci f.5 on end # EHCI + end + end + # APIC cluster is late CPU init. + device apic_cluster 0 on + chip cpu/amd/model_lx + device apic 0 on end + end + end +end + Index: LinuxBIOSv2/src/mainboard/amd/db800/Options.lb =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ LinuxBIOSv2/src/mainboard/amd/db800/Options.lb 2007-06-04 16:24:25.000000000 -0600 @@ -0,0 +1,179 @@ +uses HAVE_MP_TABLE +uses HAVE_PIRQ_TABLE +uses USE_FALLBACK_IMAGE +uses HAVE_FALLBACK_BOOT +uses HAVE_HARD_RESET +uses HAVE_OPTION_TABLE +uses USE_OPTION_TABLE +uses CONFIG_ROM_PAYLOAD +uses IRQ_SLOT_COUNT +uses MAINBOARD +uses MAINBOARD_VENDOR +uses MAINBOARD_PART_NUMBER +uses LINUXBIOS_EXTRA_VERSION +uses ARCH +uses FALLBACK_SIZE +uses STACK_SIZE +uses HEAP_SIZE +uses ROM_SIZE +uses ROM_SECTION_SIZE +uses ROM_IMAGE_SIZE +uses ROM_SECTION_SIZE +uses ROM_SECTION_OFFSET +uses CONFIG_ROM_PAYLOAD_START +uses CONFIG_COMPRESSED_PAYLOAD_NRV2B +uses CONFIG_COMPRESSED_PAYLOAD_LZMA +uses CONFIG_PRECOMPRESSED_PAYLOAD +uses PAYLOAD_SIZE +uses _ROMBASE +uses _RAMBASE +uses XIP_ROM_SIZE +uses XIP_ROM_BASE +uses HAVE_MP_TABLE +uses CROSS_COMPILE +uses CC +uses HOSTCC +uses OBJCOPY +uses DEFAULT_CONSOLE_LOGLEVEL +uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_CONSOLE_SERIAL8250 +uses TTYS0_BAUD +uses TTYS0_BASE +uses TTYS0_LCS +uses CONFIG_UDELAY_TSC +uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 +uses CONFIG_CONSOLE_VGA +uses CONFIG_PCI_ROM_RUN +uses CONFIG_VIDEO_MB +uses USE_DCACHE_RAM +uses DCACHE_RAM_BASE +uses DCACHE_RAM_SIZE + +## ROM_SIZE is the size of boot ROM that this board will use. +default ROM_SIZE = 256*1024 + +### +### Build options +### +default CONFIG_CONSOLE_VGA=0 +default CONFIG_VIDEO_MB=8 +default CONFIG_PCI_ROM_RUN=0 + +## +## Build code for the fallback boot +## +default HAVE_FALLBACK_BOOT=1 + +## +## no MP table +## +default HAVE_MP_TABLE=0 + +## +## Build code to reset the motherboard from linuxBIOS +## +default HAVE_HARD_RESET=0 + +## Delay timer options +## +default CONFIG_UDELAY_TSC=1 +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 + +## +## Build code to export a programmable irq routing table +## +default HAVE_PIRQ_TABLE=1 +default IRQ_SLOT_COUNT=4 +#object irq_tables.o + +## +## Build code to export a CMOS option table +## +default HAVE_OPTION_TABLE=0 + +### +### LinuxBIOS layout values +### + +## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +default ROM_IMAGE_SIZE = 65536 +default FALLBACK_SIZE = 131072 + +## +## enable CACHE_AS_RAM specifics +## +default USE_DCACHE_RAM=1 +default DCACHE_RAM_BASE=0xc8000 +default DCACHE_RAM_SIZE=0x08000 + +## +## Use a small 8K stack +## +default STACK_SIZE=0x2000 + +## +## Use a small 16K heap +## +default HEAP_SIZE=0x4000 + +## +## Only use the option table in a normal image +## +#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default USE_OPTION_TABLE = 0 + +default _RAMBASE = 0x00004000 + +default CONFIG_ROM_PAYLOAD = 1 + +## +## The default compiler +## +default CROSS_COMPILE="" +default CC="$(CROSS_COMPILE)gcc -m32" +default HOSTCC="gcc" + +## +## The Serial Console +## + +# To Enable the Serial Console +default CONFIG_CONSOLE_SERIAL8250=1 + +## Select the serial console baud rate +default TTYS0_BAUD=115200 +#default TTYS0_BAUD=57600 +#default TTYS0_BAUD=38400 +#default TTYS0_BAUD=19200 +#default TTYS0_BAUD=9600 +#default TTYS0_BAUD=4800 +#default TTYS0_BAUD=2400 +#default TTYS0_BAUD=1200 + +# Select the serial console base port +default TTYS0_BASE=0x3f8 + +# Select the serial protocol +# This defaults to 8 data bits, 1 stop bit, and no parity +default TTYS0_LCS=0x3 + +## +### Select the linuxBIOS loglevel +## +## EMERG 1 system is unusable +## ALERT 2 action must be taken immediately +## CRIT 3 critical conditions +## ERR 4 error conditions +## WARNING 5 warning conditions +## NOTICE 6 normal but significant condition +## INFO 7 informational +## DEBUG 8 debug-level messages +## SPEW 9 Way too many details + +## Request this level of debugging output +default DEFAULT_CONSOLE_LOGLEVEL=8 +## At a maximum only compile in this level of debugging +default MAXIMUM_CONSOLE_LOGLEVEL=8 + +end + Index: LinuxBIOSv2/src/mainboard/amd/db800/cache_as_ram_auto.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ LinuxBIOSv2/src/mainboard/amd/db800/cache_as_ram_auto.c 2007-06-04 16:24:24.000000000 -0600 @@ -0,0 +1,135 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define ASSEMBLY 1 + +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/hlt.h> +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" +#include "cpu/x86/bist.h" +#include "cpu/x86/msr.h" +#include <cpu/amd/lxdef.h> +#include <cpu/amd/geode_post_code.h> +#include "southbridge/amd/cs5536/cs5536.h" + +#define POST_CODE(x) outb(x, 0x80) +#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) + +#include "southbridge/amd/cs5536/cs5536_early_smbus.c" +#include "southbridge/amd/cs5536/cs5536_early_setup.c" +#include "superio/winbond/w83627hf/w83627hf_early_serial.c" + +static inline int spd_read_byte(unsigned int device, unsigned int address) +{ + return smbus_read_byte(device, address); +} + +#define ManualConf 0 /* Do automatic strapped PLL config */ +#define PLLMSRhi 0x00001490 /* manual settings for the PLL */ +#define PLLMSRlo 0x02000030 +#define DIMM0 0xA0 +#define DIMM1 0xA2 + +#include "northbridge/amd/lx/raminit.h" +#include "northbridge/amd/lx/pll_reset.c" +#include "northbridge/amd/lx/raminit.c" +#include "sdram/generic_sdram.c" +#include "cpu/amd/model_lx/cpureginit.c" +#include "cpu/amd/model_lx/syspreinit.c" + +static void msr_init(void) +{ + msr_t msr; + + /* Setup access to the cache for under 1MB. */ + msr.hi = 0x24fffc02; + msr.lo = 0x1000A000; /* 0-A0000 write back */ + wrmsr(CPU_RCONF_DEFAULT, msr); + + msr.hi = 0x0; /* write back */ + msr.lo = 0x0; + wrmsr(CPU_RCONF_A0_BF, msr); + wrmsr(CPU_RCONF_C0_DF, msr); + wrmsr(CPU_RCONF_E0_FF, msr); + + /* Setup access to the cache for under 640K. Note MC not setup yet. */ + msr.hi = 0x20000000; + msr.lo = 0xfff80; + wrmsr(MSR_GLIU0 + 0x20, msr); + + msr.hi = 0x20000000; + msr.lo = 0x80fffe0; + wrmsr(MSR_GLIU0 + 0x21, msr); + + msr.hi = 0x20000000; + msr.lo = 0xfff80; + wrmsr(MSR_GLIU1 + 0x20, msr); + + msr.hi = 0x20000000; + msr.lo = 0x80fffe0; + wrmsr(MSR_GLIU1 + 0x21, msr); +} + +static void mb_gpio_init(void) +{ + /* Early mainboard specific GPIO setup. */ +} + +void cache_as_ram_main(void) +{ + POST_CODE(0x01); + + static const struct mem_controller memctrl[] = { + {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}} + }; + + SystemPreInit(); + msr_init(); + + cs5536_early_setup(); + + /* Note: must do this AFTER the early_setup! It is counting on some + * early MSR setup for CS5536. + */ + /* cs5536_disable_internal_uart: disable them for now, set them + * up later... + */ + w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + mb_gpio_init(); + uart_init(); + console_init(); + + pll_reset(ManualConf); + + cpuRegInit(); + + sdram_initialize(1, memctrl); + + /* Check memory. */ + /* ram_check(0x00000000, 640 * 1024); */ + + /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */ + return; +} Index: LinuxBIOSv2/src/mainboard/amd/db800/chip.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ LinuxBIOSv2/src/mainboard/amd/db800/chip.h 2007-06-04 16:24:24.000000000 -0600 @@ -0,0 +1,25 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_amd_db800_ops; + +struct mainboard_amd_db800_config { + int nothing; +}; Index: LinuxBIOSv2/src/mainboard/amd/db800/cmos.layout =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ LinuxBIOSv2/src/mainboard/amd/db800/cmos.layout 2007-06-04 16:24:25.000000000 -0600 @@ -0,0 +1,74 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +1008 16 h 0 check_sum + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM + +checksums + +checksum 392 1007 1008 + + Index: LinuxBIOSv2/src/mainboard/amd/db800/failover.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ LinuxBIOSv2/src/mainboard/amd/db800/failover.c 2007-06-04 16:24:25.000000000 -0600 @@ -0,0 +1,32 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define ASSEMBLY 1 + +#include <stdint.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include "pc80/mc146818rtc_early.c" + +static unsigned long main(unsigned long bist) +{ + return bist; +} Index: LinuxBIOSv2/src/mainboard/amd/db800/irq_tables.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ LinuxBIOSv2/src/mainboard/amd/db800/irq_tables.c 2007-06-04 16:24:25.000000000 -0600 @@ -0,0 +1,106 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> +#include <console/console.h> +#include <arch/io.h> +#include <arch/pirq_routing.h> +#include "../../../southbridge/amd/cs5536/cs5536.h" + +/* Platform IRQs */ +#define PIRQA 10 +#define PIRQB 11 +#define PIRQC 10 +#define PIRQD 11 + +/* Map */ +#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */ +#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */ +#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */ +#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */ + +/* Link */ +#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */ +#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */ +#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */ +#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */ + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * IRQ_SLOT_COUNT, /* there can be total 6 devices on the bus */ + 0x00, /* Where the interrupt router lies (bus) */ + (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ + 0x00, /* IRQs devoted exclusively to PCI usage */ + 0x100B, /* Vendor */ + 0x002B, /* Device */ + 0, /* Crap (miniport) */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ + 0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + { + /* If you change the number of entries, change the IRQ_SLOT_COUNT above! */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */ + {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */ + {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */ + {0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x1, 0x0}, /* slot1 */ + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + int i, j, k, num_entries; + unsigned char pirq[4]; + uint16_t chipset_irq_map; + uint32_t pciAddr, pirtable_end; + struct irq_routing_table *pirq_tbl; + + pirtable_end = copy_pirq_routing_table(addr); + + /* Set up chipset IRQ steering. */ + pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C; + chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA); + printk_debug("%s(%08X, %04X)\n", __FUNCTION__, pciAddr, + chipset_irq_map); + outl(pciAddr & ~3, 0xCF8); + outl(chipset_irq_map, 0xCFC); + + pirq_tbl = (struct irq_routing_table *)(addr); + num_entries = (pirq_tbl->size - 32) / 16; + + /* Set PCI IRQs. */ + for (i = 0; i < num_entries; i++) { + printk_debug("PIR Entry %d Dev/Fn: %X Slot: %d\n", i, + pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot); + for (j = 0; j < 4; j++) { + printk_debug("INT: %c bitmap: %x ", 'A' + j, + pirq_tbl->slots[i].irq[j].bitmap); + for (k = 0; (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1)) && (pirq_tbl->slots[i].irq[j].bitmap != 0); k++) ; /* Finds lsb in bitmap to IRQ#. */ + pirq[j] = k; + printk_debug("PIRQ: %d\n", k); + } + + /* Bus, device, slots IRQs for {A,B,C,D}. */ + pci_assign_irqs(pirq_tbl->slots[i].bus, + pirq_tbl->slots[i].devfn >> 3, pirq); + } + + /* Put the PIR table in memory and checksum. */ + return pirtable_end; +} Index: LinuxBIOSv2/src/mainboard/amd/db800/mainboard.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ LinuxBIOSv2/src/mainboard/amd/db800/mainboard.c 2007-06-04 16:24:25.000000000 -0600 @@ -0,0 +1,193 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <arch/io.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/lxdef.h> +#include <device/pci_def.h> +#include "../../../southbridge/amd/cs5536/cs5536.h" +#include "chip.h" + +/* Print the platform configuration - do before PCI init or it will not + * work right. + */ +void print_conf(void) +{ +#if DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR + int i; + unsigned long iol; + msr_t msr; + + int cpu_msr_defs[] = { CPU_BC_L2_CONF, CPU_IM_CONFIG, CPU_DM_CONFIG0, + CPU_RCONF_DEFAULT, CPU_RCONF_BYPASS, CPU_RCONF_A0_BF, + CPU_RCONF_C0_DF, CPU_RCONF_E0_FF, CPU_RCONF_SMM, CPU_RCONF_DMM, + GLCP_DELAY_CONTROLS, GL_END + }; + + int gliu0_msr_defs[] = { MSR_GLIU0_BASE1, MSR_GLIU0_BASE2, + MSR_GLIU0_BASE4, MSR_GLIU0_BASE5, MSR_GLIU0_BASE6, + GLIU0_P2D_BMO_0, GLIU0_P2D_BMO_1, MSR_GLIU0_SYSMEM, + GLIU0_P2D_RO_0, GLIU0_P2D_RO_1, GLIU0_P2D_RO_2, + MSR_GLIU0_SHADOW, GLIU0_IOD_BM_0, GLIU0_IOD_BM_1, + GLIU0_IOD_BM_2, GLIU0_IOD_SC_0, GLIU0_IOD_SC_1, GLIU0_IOD_SC_2, + GLIU0_IOD_SC_3, GLIU0_IOD_SC_4, GLIU0_IOD_SC_5, + GLIU0_GLD_MSR_COH, GL_END + }; + + int gliu1_msr_defs[] = { MSR_GLIU1_BASE1, MSR_GLIU1_BASE2, + MSR_GLIU1_BASE3, MSR_GLIU1_BASE4, MSR_GLIU1_BASE5, + MSR_GLIU1_BASE6, MSR_GLIU1_BASE7, MSR_GLIU1_BASE8, + MSR_GLIU1_BASE9, MSR_GLIU1_BASE10, GLIU1_P2D_R_0, + GLIU1_P2D_R_1, GLIU1_P2D_R_2, GLIU1_P2D_R_3, MSR_GLIU1_SHADOW, + GLIU1_IOD_BM_0, GLIU1_IOD_BM_1, GLIU1_IOD_BM_2, GLIU1_IOD_SC_0, + GLIU1_IOD_SC_1, GLIU1_IOD_SC_2, GLIU1_IOD_SC_3, + GLIU1_GLD_MSR_COH, GL_END + }; + + int rconf_msr[] = { CPU_RCONF0, CPU_RCONF1, CPU_RCONF2, CPU_RCONF3, + CPU_RCONF4, CPU_RCONF5, CPU_RCONF6, CPU_RCONF7, GL_END + }; + + int cs5536_msr[] = { MDD_LBAR_GPIO, MDD_LBAR_FLSH0, MDD_LBAR_FLSH1, + MDD_LEG_IO, MDD_PIN_OPT, MDD_IRQM_ZLOW, MDD_IRQM_ZHIGH, + MDD_IRQM_PRIM, GL_END + }; + + int pci_msr[] = { GLPCI_CTRL, GLPCI_ARB, GLPCI_REN, GLPCI_A0_BF, + GLPCI_C0_DF, GLPCI_E0_FF, GLPCI_RC0, GLPCI_RC1, GLPCI_RC2, + GLPCI_RC3, GLPCI_ExtMSR, GLPCI_SPARE, GL_END + }; + + int dma_msr[] = { MDD_DMA_MAP, MDD_DMA_SHAD1, MDD_DMA_SHAD2, + MDD_DMA_SHAD3, MDD_DMA_SHAD4, MDD_DMA_SHAD5, MDD_DMA_SHAD6, + MDD_DMA_SHAD7, MDD_DMA_SHAD8, MDD_DMA_SHAD9, GL_END + }; + + printk_debug("---------- CPU ------------\n"); + + for (i = 0; cpu_msr_defs[i] != GL_END; i++) { + msr = rdmsr(cpu_msr_defs[i]); + printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", + cpu_msr_defs[i], msr.hi, msr.lo); + } + + printk_debug("---------- GLIU 0 ------------\n"); + + for (i = 0; gliu0_msr_defs[i] != GL_END; i++) { + msr = rdmsr(gliu0_msr_defs[i]); + printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", + gliu0_msr_defs[i], msr.hi, msr.lo); + } + + printk_debug("---------- GLIU 1 ------------\n"); + + for (i = 0; gliu1_msr_defs[i] != GL_END; i++) { + msr = rdmsr(gliu1_msr_defs[i]); + printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", + gliu1_msr_defs[i], msr.hi, msr.lo); + } + + printk_debug("---------- RCONF ------------\n"); + + for (i = 0; rconf_msr[i] != GL_END; i++) { + msr = rdmsr(rconf_msr[i]); + printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", rconf_msr[i], + msr.hi, msr.lo); + } + + printk_debug("---------- VARIA ------------\n"); + msr = rdmsr(0x51300010); + printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51300010, msr.hi, + msr.lo); + + msr = rdmsr(0x51400015); + printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51400015, msr.hi, + msr.lo); + + printk_debug("---------- DIVIL IRQ ------------\n"); + msr = rdmsr(MDD_IRQM_YLOW); + printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YLOW, msr.hi, + msr.lo); + msr = rdmsr(MDD_IRQM_YHIGH); + printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YHIGH, + msr.hi, msr.lo); + msr = rdmsr(MDD_IRQM_ZLOW); + printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZLOW, msr.hi, + msr.lo); + msr = rdmsr(MDD_IRQM_ZHIGH); + printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZHIGH, + msr.hi, msr.lo); + + printk_debug("---------- PCI ------------\n"); + + for (i = 0; pci_msr[i] != GL_END; i++) { + msr = rdmsr(pci_msr[i]); + printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", pci_msr[i], + msr.hi, msr.lo); + } + + printk_debug("---------- LPC/UART DMA ------------\n"); + + for (i = 0; dma_msr[i] != GL_END; i++) { + msr = rdmsr(dma_msr[i]); + printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", dma_msr[i], + msr.hi, msr.lo); + } + + printk_debug("---------- CS5536 ------------\n"); + + for (i = 0; cs5536_msr[i] != GL_END; i++) { + msr = rdmsr(cs5536_msr[i]); + printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", cs5536_msr[i], + msr.hi, msr.lo); + } + + iol = inl(GPIO_IO_BASE + GPIOL_INPUT_ENABLE); + printk_debug("IOR 0x%08X is now 0x%08X\n", + GPIO_IO_BASE + GPIOL_INPUT_ENABLE, iol); + iol = inl(GPIOL_EVENTS_ENABLE); + printk_debug("IOR 0x%08X is now 0x%08X\n", + GPIO_IO_BASE + GPIOL_EVENTS_ENABLE, iol); + iol = inl(GPIOL_INPUT_INVERT_ENABLE); + printk_debug("IOR 0x%08X is now 0x%08X\n", + GPIO_IO_BASE + GPIOL_INPUT_INVERT_ENABLE, iol); + iol = inl(GPIO_MAPPER_X); + printk_debug("IOR 0x%08X is now 0x%08X\n", GPIO_IO_BASE + GPIO_MAPPER_X, + iol); +#endif //DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR +} + +static void init(struct device *dev) +{ + printk_debug("AMD DB800 ENTER %s\n", __FUNCTION__); + printk_debug("AMD DB800 EXIT %s\n", __FUNCTION__); +} + +static void enable_dev(struct device *dev) +{ + dev->ops->init = init; +} + +struct chip_operations mainboard_amd_db800_ops = { + CHIP_NAME("AMD DB800 Mainboard") + .enable_dev = enable_dev, + +}; Index: LinuxBIOSv2/targets/amd/db800/Config.lb =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ LinuxBIOSv2/targets/amd/db800/Config.lb 2007-06-04 16:24:25.000000000 -0600 @@ -0,0 +1,49 @@ +## +## This file is part of the LinuxBIOS project. +## +## Copyright (C) 2007 Advanced Micro Devices, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +# Config file for the AMD Geode LX/5536 DB800 Platform. + +target db800 +mainboard amd/db800 + +# HACK to get the right TSC support. +option CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 + +# Leave 36k for VSA. +option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0 +option CONFIG_COMPRESSED_PAYLOAD_LZMA=0 + +option ROM_SIZE=512*1024-36*1024 +#option ROM_SIZE=256*1024-36*1024 +option FALLBACK_SIZE=ROM_SIZE + +option DEFAULT_CONSOLE_LOGLEVEL = 11 +option MAXIMUM_CONSOLE_LOGLEVEL = 11 +#option DEFAULT_CONSOLE_LOGLEVEL = 4 +#option MAXIMUM_CONSOLE_LOGLEVEL = 4 + +romimage "fallback" + option USE_FALLBACK_IMAGE=1 + option ROM_IMAGE_SIZE=64*1024 + option LINUXBIOS_EXTRA_VERSION=".0Fallback" + payload ../payload.elf +end + +buildrom ./db800.rom ROM_SIZE "fallback"

2 1

[LinuxBIOS] r2718 - in trunk/LinuxBIOSv2: src/mainboard/amd src/mainboard/amd/db800 targets/amd targets/amd/db800
by svn＠openbios.org 13 Jun '07

13 Jun '07

Author: uwe Date: 2007-06-13 00:54:41 +0200 (Wed, 13 Jun 2007) New Revision: 2718 Added: trunk/LinuxBIOSv2/src/mainboard/amd/db800/ trunk/LinuxBIOSv2/src/mainboard/amd/db800/Config.lb trunk/LinuxBIOSv2/src/mainboard/amd/db800/Options.lb trunk/LinuxBIOSv2/src/mainboard/amd/db800/cache_as_ram_auto.c trunk/LinuxBIOSv2/src/mainboard/amd/db800/chip.h trunk/LinuxBIOSv2/src/mainboard/amd/db800/cmos.layout trunk/LinuxBIOSv2/src/mainboard/amd/db800/failover.c trunk/LinuxBIOSv2/src/mainboard/amd/db800/irq_tables.c trunk/LinuxBIOSv2/src/mainboard/amd/db800/mainboard.c trunk/LinuxBIOSv2/targets/amd/db800/ trunk/LinuxBIOSv2/targets/amd/db800/Config.lb Log: Add the AMD DB800 (AKA Salsa) mainboard. The DB800 is the AMD LX Reference Design Kit platform. For details see: http://www.amd.com/geodelxdb800 Signed-off-by: Marc Jones <marc.jones(a)amd.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Added: trunk/LinuxBIOSv2/src/mainboard/amd/db800/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/db800/Config.lb (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/amd/db800/Config.lb 2007-06-12 22:54:41 UTC (rev 2718) @@ -0,0 +1,189 @@ +## +## Compute the location and size of where this firmware image +## (linuxBIOS plus bootloader) will live in the boot rom chip. +## +if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE ) +else + default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE ) + default ROM_SECTION_OFFSET = 0 +end + +## +## Compute the start location and size size of +## The linuxBIOS bootloader. +## + +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) +default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) + +## +## Compute where this copy of linuxBIOS will start in the boot rom +## +default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) + +## +## Compute a range of ROM that can cached to speed up linuxBIOS, +## execution speed. +## +## XIP_ROM_SIZE must be a power of 2. +## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE +## +default XIP_ROM_SIZE=65536 +default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) + + +## +## Set all of the defaults for an x86 architecture +## + +arch i386 end + +## +## Build the objects we have code for in this directory. +## + +driver mainboard.o + +if HAVE_PIRQ_TABLE + object irq_tables.o +end + +if USE_DCACHE_RAM + #compile cache_as_ram.c to auto.inc + makerule ./cache_as_ram_auto.inc + depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" + action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@" + action "perl -e 's/.rodata/.rom.data/g' -pi $@" + action "perl -e 's/.text/.section .rom.text/g' -pi $@" + end +end + + +## +## Build our 16 bit and 32 bit linuxBIOS entry code +## +mainboardinit cpu/x86/16bit/entry16.inc +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/16bit/entry16.lds +ldscript /cpu/x86/32bit/entry32.lds + +## +## Build our reset vector (This is where linuxBIOS is entered) +## +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds +else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds +end + +### Should this be in the northbridge code? +#not in serengeti_cheetah mainboardinit arch/i386/lib/cpu_reset.inc + +## +## Include an id string (For safe flashing) +## +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds + +### +### This is the early phase of linuxBIOS startup +### Things are delicate and we test to see if we should +### failover to another image. +### +if USE_FALLBACK_IMAGE + ldscript /arch/i386/lib/failover.lds +# mainboardinit ./failover.inc +end + +### +### O.k. We aren't just an intermediary anymore! +### + +## +## Setup RAM +## +mainboardinit cpu/x86/fpu/enable_fpu.inc + +if USE_DCACHE_RAM + mainboardinit cpu/amd/model_lx/cache_as_ram.inc + mainboardinit ./cache_as_ram_auto.inc +end + +## +## Include the secondary Configuration files +## +dir /pc80 +config chip.h + +chip northbridge/amd/lx + device pci_domain 0 on + device pci 1.0 on end # Northbridge + device pci 1.1 on end # Graphics + chip southbridge/amd/cs5536 + # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK + # SIRQ Mode = Active(Quiet) mode. Save power.... + # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK + register "lpc_serirq_enable" = "0x000010da" + register "lpc_serirq_polarity" = "0x0000EF25" + register "lpc_serirq_mode" = "1" + register "enable_gpio_int_route" = "0x0D0C0700" + register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash + register "enable_USBP4_device" = "1" # 0: host, 1:device + register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) + register "com1_enable" = "0" + register "com1_address" = "0x3F8" + register "com1_irq" = "4" + register "com2_enable" = "0" + register "com2_address" = "0x2F8" + register "com2_irq" = "3" + register "unwanted_vpci[0]" = "0" # End of list has a zero + device pci d.0 on end # Ethernet + device pci e.0 on end # Slot1 + device pci f.0 on # ISA Bridge + chip superio/winbond/w83627hf + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # Com2 + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GAME_MIDI_GIPO1 + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b off end # HW Monitor + end + end + device pci f.2 on end # IDE Controller + device pci f.3 on end # Audio + device pci f.4 on end # OHCI + device pci f.5 on end # EHCI + end + end + # APIC cluster is late CPU init. + device apic_cluster 0 on + chip cpu/amd/model_lx + device apic 0 on end + end + end +end + Added: trunk/LinuxBIOSv2/src/mainboard/amd/db800/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/db800/Options.lb (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/amd/db800/Options.lb 2007-06-12 22:54:41 UTC (rev 2718) @@ -0,0 +1,179 @@ +uses HAVE_MP_TABLE +uses HAVE_PIRQ_TABLE +uses USE_FALLBACK_IMAGE +uses HAVE_FALLBACK_BOOT +uses HAVE_HARD_RESET +uses HAVE_OPTION_TABLE +uses USE_OPTION_TABLE +uses CONFIG_ROM_PAYLOAD +uses IRQ_SLOT_COUNT +uses MAINBOARD +uses MAINBOARD_VENDOR +uses MAINBOARD_PART_NUMBER +uses LINUXBIOS_EXTRA_VERSION +uses ARCH +uses FALLBACK_SIZE +uses STACK_SIZE +uses HEAP_SIZE +uses ROM_SIZE +uses ROM_SECTION_SIZE +uses ROM_IMAGE_SIZE +uses ROM_SECTION_SIZE +uses ROM_SECTION_OFFSET +uses CONFIG_ROM_PAYLOAD_START +uses CONFIG_COMPRESSED_PAYLOAD_NRV2B +uses CONFIG_COMPRESSED_PAYLOAD_LZMA +uses CONFIG_PRECOMPRESSED_PAYLOAD +uses PAYLOAD_SIZE +uses _ROMBASE +uses _RAMBASE +uses XIP_ROM_SIZE +uses XIP_ROM_BASE +uses HAVE_MP_TABLE +uses CROSS_COMPILE +uses CC +uses HOSTCC +uses OBJCOPY +uses DEFAULT_CONSOLE_LOGLEVEL +uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_CONSOLE_SERIAL8250 +uses TTYS0_BAUD +uses TTYS0_BASE +uses TTYS0_LCS +uses CONFIG_UDELAY_TSC +uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 +uses CONFIG_CONSOLE_VGA +uses CONFIG_PCI_ROM_RUN +uses CONFIG_VIDEO_MB +uses USE_DCACHE_RAM +uses DCACHE_RAM_BASE +uses DCACHE_RAM_SIZE + +## ROM_SIZE is the size of boot ROM that this board will use. +default ROM_SIZE = 256*1024 + +### +### Build options +### +default CONFIG_CONSOLE_VGA=0 +default CONFIG_VIDEO_MB=8 +default CONFIG_PCI_ROM_RUN=0 + +## +## Build code for the fallback boot +## +default HAVE_FALLBACK_BOOT=1 + +## +## no MP table +## +default HAVE_MP_TABLE=0 + +## +## Build code to reset the motherboard from linuxBIOS +## +default HAVE_HARD_RESET=0 + +## Delay timer options +## +default CONFIG_UDELAY_TSC=1 +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 + +## +## Build code to export a programmable irq routing table +## +default HAVE_PIRQ_TABLE=1 +default IRQ_SLOT_COUNT=4 +#object irq_tables.o + +## +## Build code to export a CMOS option table +## +default HAVE_OPTION_TABLE=0 + +### +### LinuxBIOS layout values +### + +## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +default ROM_IMAGE_SIZE = 65536 +default FALLBACK_SIZE = 131072 + +## +## enable CACHE_AS_RAM specifics +## +default USE_DCACHE_RAM=1 +default DCACHE_RAM_BASE=0xc8000 +default DCACHE_RAM_SIZE=0x08000 + +## +## Use a small 8K stack +## +default STACK_SIZE=0x2000 + +## +## Use a small 16K heap +## +default HEAP_SIZE=0x4000 + +## +## Only use the option table in a normal image +## +#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default USE_OPTION_TABLE = 0 + +default _RAMBASE = 0x00004000 + +default CONFIG_ROM_PAYLOAD = 1 + +## +## The default compiler +## +default CROSS_COMPILE="" +default CC="$(CROSS_COMPILE)gcc -m32" +default HOSTCC="gcc" + +## +## The Serial Console +## + +# To Enable the Serial Console +default CONFIG_CONSOLE_SERIAL8250=1 + +## Select the serial console baud rate +default TTYS0_BAUD=115200 +#default TTYS0_BAUD=57600 +#default TTYS0_BAUD=38400 +#default TTYS0_BAUD=19200 +#default TTYS0_BAUD=9600 +#default TTYS0_BAUD=4800 +#default TTYS0_BAUD=2400 +#default TTYS0_BAUD=1200 + +# Select the serial console base port +default TTYS0_BASE=0x3f8 + +# Select the serial protocol +# This defaults to 8 data bits, 1 stop bit, and no parity +default TTYS0_LCS=0x3 + +## +### Select the linuxBIOS loglevel +## +## EMERG 1 system is unusable +## ALERT 2 action must be taken immediately +## CRIT 3 critical conditions +## ERR 4 error conditions +## WARNING 5 warning conditions +## NOTICE 6 normal but significant condition +## INFO 7 informational +## DEBUG 8 debug-level messages +## SPEW 9 Way too many details + +## Request this level of debugging output +default DEFAULT_CONSOLE_LOGLEVEL=8 +## At a maximum only compile in this level of debugging +default MAXIMUM_CONSOLE_LOGLEVEL=8 + +end + Added: trunk/LinuxBIOSv2/src/mainboard/amd/db800/cache_as_ram_auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/db800/cache_as_ram_auto.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/amd/db800/cache_as_ram_auto.c 2007-06-12 22:54:41 UTC (rev 2718) @@ -0,0 +1,132 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define ASSEMBLY 1 + +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/hlt.h> +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" +#include "cpu/x86/bist.h" +#include "cpu/x86/msr.h" +#include <cpu/amd/lxdef.h> +#include <cpu/amd/geode_post_code.h> +#include "southbridge/amd/cs5536/cs5536.h" + +#define POST_CODE(x) outb(x, 0x80) +#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) + +#include "southbridge/amd/cs5536/cs5536_early_smbus.c" +#include "southbridge/amd/cs5536/cs5536_early_setup.c" +#include "superio/winbond/w83627hf/w83627hf_early_serial.c" + +static inline int spd_read_byte(unsigned int device, unsigned int address) +{ + return smbus_read_byte(device, address); +} + +#define ManualConf 0 /* Do automatic strapped PLL config */ +#define PLLMSRhi 0x00001490 /* Manual settings for the PLL */ +#define PLLMSRlo 0x02000030 +#define DIMM0 0xA0 +#define DIMM1 0xA2 + +#include "northbridge/amd/lx/raminit.h" +#include "northbridge/amd/lx/pll_reset.c" +#include "northbridge/amd/lx/raminit.c" +#include "sdram/generic_sdram.c" +#include "cpu/amd/model_lx/cpureginit.c" +#include "cpu/amd/model_lx/syspreinit.c" + +static void msr_init(void) +{ + msr_t msr; + + /* Setup access to the cache for under 1MB. */ + msr.hi = 0x24fffc02; + msr.lo = 0x1000A000; /* 0-A0000 write back */ + wrmsr(CPU_RCONF_DEFAULT, msr); + + msr.hi = 0x0; /* Write back */ + msr.lo = 0x0; + wrmsr(CPU_RCONF_A0_BF, msr); + wrmsr(CPU_RCONF_C0_DF, msr); + wrmsr(CPU_RCONF_E0_FF, msr); + + /* Setup access to the cache for under 640K. Note MC not setup yet. */ + msr.hi = 0x20000000; + msr.lo = 0xfff80; + wrmsr(MSR_GLIU0 + 0x20, msr); + + msr.hi = 0x20000000; + msr.lo = 0x80fffe0; + wrmsr(MSR_GLIU0 + 0x21, msr); + + msr.hi = 0x20000000; + msr.lo = 0xfff80; + wrmsr(MSR_GLIU1 + 0x20, msr); + + msr.hi = 0x20000000; + msr.lo = 0x80fffe0; + wrmsr(MSR_GLIU1 + 0x21, msr); +} + +static void mb_gpio_init(void) +{ + /* Early mainboard specific GPIO setup. */ +} + +void cache_as_ram_main(void) +{ + POST_CODE(0x01); + + static const struct mem_controller memctrl[] = { + {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}} + }; + + SystemPreInit(); + msr_init(); + + cs5536_early_setup(); + + /* Note: must do this AFTER the early_setup! It is counting on some + * early MSR setup for CS5536. + */ + w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + mb_gpio_init(); + uart_init(); + console_init(); + + pll_reset(ManualConf); + + cpuRegInit(); + + sdram_initialize(1, memctrl); + + /* Check memory. */ + /* ram_check(0x00000000, 640 * 1024); */ + + /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */ + return; +} Added: trunk/LinuxBIOSv2/src/mainboard/amd/db800/chip.h =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/db800/chip.h (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/amd/db800/chip.h 2007-06-12 22:54:41 UTC (rev 2718) @@ -0,0 +1,25 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_amd_db800_ops; + +struct mainboard_amd_db800_config { + int nothing; +}; Added: trunk/LinuxBIOSv2/src/mainboard/amd/db800/cmos.layout =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/db800/cmos.layout (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/amd/db800/cmos.layout 2007-06-12 22:54:41 UTC (rev 2718) @@ -0,0 +1,74 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +1008 16 h 0 check_sum + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM + +checksums + +checksum 392 1007 1008 + + Added: trunk/LinuxBIOSv2/src/mainboard/amd/db800/failover.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/db800/failover.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/amd/db800/failover.c 2007-06-12 22:54:41 UTC (rev 2718) @@ -0,0 +1,32 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define ASSEMBLY 1 + +#include <stdint.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include "pc80/mc146818rtc_early.c" + +static unsigned long main(unsigned long bist) +{ + return bist; +} Added: trunk/LinuxBIOSv2/src/mainboard/amd/db800/irq_tables.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/db800/irq_tables.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/amd/db800/irq_tables.c 2007-06-12 22:54:41 UTC (rev 2718) @@ -0,0 +1,106 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> +#include <console/console.h> +#include <arch/io.h> +#include <arch/pirq_routing.h> +#include "../../../southbridge/amd/cs5536/cs5536.h" + +/* Platform IRQs */ +#define PIRQA 10 +#define PIRQB 11 +#define PIRQC 10 +#define PIRQD 11 + +/* Map */ +#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */ +#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */ +#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */ +#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */ + +/* Link */ +#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */ +#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */ +#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */ +#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */ + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * IRQ_SLOT_COUNT, /* there can be total 6 devices on the bus */ + 0x00, /* Where the interrupt router lies (bus) */ + (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ + 0x00, /* IRQs devoted exclusively to PCI usage */ + 0x100B, /* Vendor */ + 0x002B, /* Device */ + 0, /* Crap (miniport) */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ + 0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + { + /* If you change the number of entries, change the IRQ_SLOT_COUNT above! */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */ + {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */ + {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */ + {0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x1, 0x0}, /* slot1 */ + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + int i, j, k, num_entries; + unsigned char pirq[4]; + uint16_t chipset_irq_map; + uint32_t pciAddr, pirtable_end; + struct irq_routing_table *pirq_tbl; + + pirtable_end = copy_pirq_routing_table(addr); + + /* Set up chipset IRQ steering. */ + pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C; + chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA); + printk_debug("%s(%08X, %04X)\n", __FUNCTION__, pciAddr, + chipset_irq_map); + outl(pciAddr & ~3, 0xCF8); + outl(chipset_irq_map, 0xCFC); + + pirq_tbl = (struct irq_routing_table *)(addr); + num_entries = (pirq_tbl->size - 32) / 16; + + /* Set PCI IRQs. */ + for (i = 0; i < num_entries; i++) { + printk_debug("PIR Entry %d Dev/Fn: %X Slot: %d\n", i, + pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot); + for (j = 0; j < 4; j++) { + printk_debug("INT: %c bitmap: %x ", 'A' + j, + pirq_tbl->slots[i].irq[j].bitmap); + for (k = 0; (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1)) && (pirq_tbl->slots[i].irq[j].bitmap != 0); k++) ; /* Finds lsb in bitmap to IRQ#. */ + pirq[j] = k; + printk_debug("PIRQ: %d\n", k); + } + + /* Bus, device, slots IRQs for {A,B,C,D}. */ + pci_assign_irqs(pirq_tbl->slots[i].bus, + pirq_tbl->slots[i].devfn >> 3, pirq); + } + + /* Put the PIR table in memory and checksum. */ + return pirtable_end; +} Added: trunk/LinuxBIOSv2/src/mainboard/amd/db800/mainboard.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/db800/mainboard.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/amd/db800/mainboard.c 2007-06-12 22:54:41 UTC (rev 2718) @@ -0,0 +1,193 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <arch/io.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/lxdef.h> +#include <device/pci_def.h> +#include "../../../southbridge/amd/cs5536/cs5536.h" +#include "chip.h" + +/* Print the platform configuration - do before PCI init or it will not + * work right. + */ +void print_conf(void) +{ +#if DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR + int i; + unsigned long iol; + msr_t msr; + + int cpu_msr_defs[] = { CPU_BC_L2_CONF, CPU_IM_CONFIG, CPU_DM_CONFIG0, + CPU_RCONF_DEFAULT, CPU_RCONF_BYPASS, CPU_RCONF_A0_BF, + CPU_RCONF_C0_DF, CPU_RCONF_E0_FF, CPU_RCONF_SMM, CPU_RCONF_DMM, + GLCP_DELAY_CONTROLS, GL_END + }; + + int gliu0_msr_defs[] = { MSR_GLIU0_BASE1, MSR_GLIU0_BASE2, + MSR_GLIU0_BASE4, MSR_GLIU0_BASE5, MSR_GLIU0_BASE6, + GLIU0_P2D_BMO_0, GLIU0_P2D_BMO_1, MSR_GLIU0_SYSMEM, + GLIU0_P2D_RO_0, GLIU0_P2D_RO_1, GLIU0_P2D_RO_2, + MSR_GLIU0_SHADOW, GLIU0_IOD_BM_0, GLIU0_IOD_BM_1, + GLIU0_IOD_BM_2, GLIU0_IOD_SC_0, GLIU0_IOD_SC_1, GLIU0_IOD_SC_2, + GLIU0_IOD_SC_3, GLIU0_IOD_SC_4, GLIU0_IOD_SC_5, + GLIU0_GLD_MSR_COH, GL_END + }; + + int gliu1_msr_defs[] = { MSR_GLIU1_BASE1, MSR_GLIU1_BASE2, + MSR_GLIU1_BASE3, MSR_GLIU1_BASE4, MSR_GLIU1_BASE5, + MSR_GLIU1_BASE6, MSR_GLIU1_BASE7, MSR_GLIU1_BASE8, + MSR_GLIU1_BASE9, MSR_GLIU1_BASE10, GLIU1_P2D_R_0, + GLIU1_P2D_R_1, GLIU1_P2D_R_2, GLIU1_P2D_R_3, MSR_GLIU1_SHADOW, + GLIU1_IOD_BM_0, GLIU1_IOD_BM_1, GLIU1_IOD_BM_2, GLIU1_IOD_SC_0, + GLIU1_IOD_SC_1, GLIU1_IOD_SC_2, GLIU1_IOD_SC_3, + GLIU1_GLD_MSR_COH, GL_END + }; + + int rconf_msr[] = { CPU_RCONF0, CPU_RCONF1, CPU_RCONF2, CPU_RCONF3, + CPU_RCONF4, CPU_RCONF5, CPU_RCONF6, CPU_RCONF7, GL_END + }; + + int cs5536_msr[] = { MDD_LBAR_GPIO, MDD_LBAR_FLSH0, MDD_LBAR_FLSH1, + MDD_LEG_IO, MDD_PIN_OPT, MDD_IRQM_ZLOW, MDD_IRQM_ZHIGH, + MDD_IRQM_PRIM, GL_END + }; + + int pci_msr[] = { GLPCI_CTRL, GLPCI_ARB, GLPCI_REN, GLPCI_A0_BF, + GLPCI_C0_DF, GLPCI_E0_FF, GLPCI_RC0, GLPCI_RC1, GLPCI_RC2, + GLPCI_RC3, GLPCI_ExtMSR, GLPCI_SPARE, GL_END + }; + + int dma_msr[] = { MDD_DMA_MAP, MDD_DMA_SHAD1, MDD_DMA_SHAD2, + MDD_DMA_SHAD3, MDD_DMA_SHAD4, MDD_DMA_SHAD5, MDD_DMA_SHAD6, + MDD_DMA_SHAD7, MDD_DMA_SHAD8, MDD_DMA_SHAD9, GL_END + }; + + printk_debug("---------- CPU ------------\n"); + + for (i = 0; cpu_msr_defs[i] != GL_END; i++) { + msr = rdmsr(cpu_msr_defs[i]); + printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", + cpu_msr_defs[i], msr.hi, msr.lo); + } + + printk_debug("---------- GLIU 0 ------------\n"); + + for (i = 0; gliu0_msr_defs[i] != GL_END; i++) { + msr = rdmsr(gliu0_msr_defs[i]); + printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", + gliu0_msr_defs[i], msr.hi, msr.lo); + } + + printk_debug("---------- GLIU 1 ------------\n"); + + for (i = 0; gliu1_msr_defs[i] != GL_END; i++) { + msr = rdmsr(gliu1_msr_defs[i]); + printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", + gliu1_msr_defs[i], msr.hi, msr.lo); + } + + printk_debug("---------- RCONF ------------\n"); + + for (i = 0; rconf_msr[i] != GL_END; i++) { + msr = rdmsr(rconf_msr[i]); + printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", rconf_msr[i], + msr.hi, msr.lo); + } + + printk_debug("---------- VARIA ------------\n"); + msr = rdmsr(0x51300010); + printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51300010, msr.hi, + msr.lo); + + msr = rdmsr(0x51400015); + printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51400015, msr.hi, + msr.lo); + + printk_debug("---------- DIVIL IRQ ------------\n"); + msr = rdmsr(MDD_IRQM_YLOW); + printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YLOW, msr.hi, + msr.lo); + msr = rdmsr(MDD_IRQM_YHIGH); + printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YHIGH, + msr.hi, msr.lo); + msr = rdmsr(MDD_IRQM_ZLOW); + printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZLOW, msr.hi, + msr.lo); + msr = rdmsr(MDD_IRQM_ZHIGH); + printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZHIGH, + msr.hi, msr.lo); + + printk_debug("---------- PCI ------------\n"); + + for (i = 0; pci_msr[i] != GL_END; i++) { + msr = rdmsr(pci_msr[i]); + printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", pci_msr[i], + msr.hi, msr.lo); + } + + printk_debug("---------- LPC/UART DMA ------------\n"); + + for (i = 0; dma_msr[i] != GL_END; i++) { + msr = rdmsr(dma_msr[i]); + printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", dma_msr[i], + msr.hi, msr.lo); + } + + printk_debug("---------- CS5536 ------------\n"); + + for (i = 0; cs5536_msr[i] != GL_END; i++) { + msr = rdmsr(cs5536_msr[i]); + printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", cs5536_msr[i], + msr.hi, msr.lo); + } + + iol = inl(GPIO_IO_BASE + GPIOL_INPUT_ENABLE); + printk_debug("IOR 0x%08X is now 0x%08X\n", + GPIO_IO_BASE + GPIOL_INPUT_ENABLE, iol); + iol = inl(GPIOL_EVENTS_ENABLE); + printk_debug("IOR 0x%08X is now 0x%08X\n", + GPIO_IO_BASE + GPIOL_EVENTS_ENABLE, iol); + iol = inl(GPIOL_INPUT_INVERT_ENABLE); + printk_debug("IOR 0x%08X is now 0x%08X\n", + GPIO_IO_BASE + GPIOL_INPUT_INVERT_ENABLE, iol); + iol = inl(GPIO_MAPPER_X); + printk_debug("IOR 0x%08X is now 0x%08X\n", GPIO_IO_BASE + GPIO_MAPPER_X, + iol); +#endif //DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR +} + +static void init(struct device *dev) +{ + printk_debug("AMD DB800 ENTER %s\n", __FUNCTION__); + printk_debug("AMD DB800 EXIT %s\n", __FUNCTION__); +} + +static void enable_dev(struct device *dev) +{ + dev->ops->init = init; +} + +struct chip_operations mainboard_amd_db800_ops = { + CHIP_NAME("AMD DB800 Mainboard") + .enable_dev = enable_dev, + +}; Added: trunk/LinuxBIOSv2/targets/amd/db800/Config.lb =================================================================== --- trunk/LinuxBIOSv2/targets/amd/db800/Config.lb (rev 0) +++ trunk/LinuxBIOSv2/targets/amd/db800/Config.lb 2007-06-12 22:54:41 UTC (rev 2718) @@ -0,0 +1,49 @@ +## +## This file is part of the LinuxBIOS project. +## +## Copyright (C) 2007 Advanced Micro Devices, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +# Config file for the AMD Geode LX/5536 DB800 platform. + +target db800 +mainboard amd/db800 + +# HACK to get the right TSC support. +option CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 + +option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0 +option CONFIG_COMPRESSED_PAYLOAD_LZMA=0 + +# Leave 36k for VSA. +option ROM_SIZE=512*1024-36*1024 +# option ROM_SIZE=256*1024-36*1024 +option FALLBACK_SIZE=ROM_SIZE + +option DEFAULT_CONSOLE_LOGLEVEL = 11 +option MAXIMUM_CONSOLE_LOGLEVEL = 11 +# option DEFAULT_CONSOLE_LOGLEVEL = 4 +# option MAXIMUM_CONSOLE_LOGLEVEL = 4 + +romimage "fallback" + option USE_FALLBACK_IMAGE=1 + option ROM_IMAGE_SIZE=64*1024 + option LINUXBIOS_EXTRA_VERSION=".0Fallback" + payload ../payload.elf +end + +buildrom ./db800.rom ROM_SIZE "fallback"

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[LinuxBIOS] dmidecode & lspci for new MSI P35 Platinum (Rollercoaster)
by Bob CFC 12 Jun '07

12 Jun '07

I read a post on a forum asking people to run these commands and post the results here to support the LinuxBios project. dmidecode lspci -n lspci -v lspci -t I have the new MSI P35 Platinum, E6600 Core2Duo at stock speed, 8gb (4x2) DDR2 pc2-6400 cas5 at stock speed (OCZ2G8004GK), Overclocked BFG Geforce 8800GTS 320mb Single PATA drive on the Marvell chip and no SATA devices yet. Running Ubuntu 7.04 (Feisty Fawn) x86_64. Hope this helps. Just ask if there is anything else that you need. Bob, London

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coreboot June 2007