coreboot June 2007

coreboot@coreboot.org

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[LinuxBIOS] r2724 build service
by LinuxBIOS information 15 Jun '07

15 Jun '07

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "stepan" checked in revision 2724 to the LinuxBIOS source repository and caused the following changes: Change Log: small agami aruma configuration updates (trivial) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of arima:hdama is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2724&device=hdama&vendor=… Configuration of artecgroup:dbe61 is still broken Compilation of ibm:e325 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2724&device=e325&vendor=i… Compilation of ibm:e326 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2724&device=e326&vendor=i… Compilation of iei:juki-511p is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2724&device=juki-511p&ven… Compilation of iwill:dk8s2 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2724&device=dk8s2&vendor=… Compilation of iwill:dk8x is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2724&device=dk8x&vendor=i… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, LinuxBIOS automatic build system

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Re: [LinuxBIOS] r351 - LinuxBIOSv3/arch/x86
by Peter Stuge 15 Jun '07

15 Jun '07

On Thu, Jun 14, 2007 at 07:45:36PM +0200, svn(a)openbios.org wrote: > New Revision: 351 > > Added: > LinuxBIOSv3/arch/x86/geodelx.c In general very nice! But.. :) > Per new standards, naming conventions have changed. Not new by any means I think, they were just ignored for the rather big initial LX patches to get them in before they bitrotted. > +void pll_reset(int manualconf, u32 pll_hi, u32 pll_lo) > +{ > + msr_t msrGlcpSysRstpll; Variable name casing? > +void set_delay_control(u8 dimm0, u8 dimm1) I like the simpler comments in here, but .. > +/* The current thinking. Subject to change... > + > +; "FUTURE ROBUSTNESS" PROPOSAL > +; ---------------------------- > +; DIMM Max MBUS MC 0x2000001A bits 26:24 > +;DIMMs devices Frequency MCP 0x4C00000F Setting vvv > +;----- ------- --------- ---------------------- ---------- > +;1 4 400MHz 0x82*100FF 0x56960004 4 > +;1 8 400MHz 0x82*100AA 0x56960004 4 > +;1 16 400MHz 0x82*10055 0x56960004 4 > +; > +;2 4,4 400MHz 0x82710000 0x56960004 4 > +;2 8,8 400MHz 0xC27100A5 0x56960004 4 *** OUT OF PUBLISHED ENVELOPE *** > +; > +;2 16,4 >333 0xB27100A5 0x56960004 4 *** OUT OF PUBLISHED ENVELOPE *** > +;2 16,8 >333 0xB27100A5 0x56960004 4 *** OUT OF PUBLISHED ENVELOPE *** > +;2 16,16 >333 0xB2710000 0x56960004 4 *** OUT OF PUBLISHED ENVELOPE *** > +; > +;1 4 <=333MHz 0x83*100FF 0x56960004 3 > +;1 8 <=333MHz 0x83*100AA 0x56960004 3 > +;1 16 <=333MHz 0x83*100AA 0x56960004 3 > +; > +;2 4,4 <=333MHz 0x837100A5 0x56960004 3 > +;2 8,8 <=333MHz 0x937100A5 0x56960004 3 > +; > +;2 16,4 <=333MHz 0xB37100A5 0x56960004 3 *** OUT OF PUBLISHED ENVELOPE *** > +;2 16,8 <=333MHz 0xB37100A5 0x56960004 3 *** OUT OF PUBLISHED ENVELOPE *** > +;2 16,16 <=333MHz 0xB37100A5 0x56960004 3 *** OUT OF PUBLISHED ENVELOPE *** > +;========================================================================= > +;* - Bit 55 (disable SDCLK 1,3,5) should be set if there is a single DIMM in slot 0, > +; but it should be clear for all 2 DIMM settings and if a single DIMM is in slot 1. > +; Bits 54:52 should always be set to '111'. > + > +;No VTT termination > +;------------------------------------- > +;ADDR/CTL have 22 ohm series R > +;DQ/DQM/DQS have 33 ohm series R > +; > +; DIMM Max MBUS > +;DIMMs devices Frequency MCP 0x4C00000F Setting > +;----- ------- --------- ---------------------- > +;1 4 400MHz 0xF2F100FF 0x56960004 4 The MC changes improve Salsa. > +;1 8 400MHz 0xF2F100FF 0x56960004 4 Delay controls no real change, > +;1 4 <=333MHz 0xF2F100FF 0x56960004 3 just fixing typo in left side. > +;1 8 <=333MHz 0xF2F100FF 0x56960004 3 > +;1 16 <=333MHz 0xF2F100FF 0x56960004 3 > +*/ This thing is pretty misplaced. It's lovely documentation that deserves a better home than smack dab in the midst of code. At the very least doxygen? > + * cpu_reg_init. All cpu register settings, here in one place, and > + * done in the proper order. > + * > + * @param debug_clock_disable Disable the debug clock to save power. Currently ignored, but we need to > + * pick this up from a CMOS setting in future. Long line. > + /* GLIU port active enable, limit south pole masters (AES and PCI) to one outstanding transaction. */ ..again.. and maybe a few more places too. Enthousiastic thumbs up from me anyway. :) //Peter

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[LinuxBIOS] [patch 0/6] BuildROM updates
by jordan.crouse＠amd.com 15 Jun '07

15 Jun '07

Hey all - following are some updates for BuildROM, including support for the DB800 from Marc Jones. Enjoy. Jordan -- Jordan Crouse Senior Linux Engineer Advanced Micro Devices, Inc. <www.amd.com/embeddedprocessors>

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[LinuxBIOS] Opteron caching of device memory
by Myles Watson 15 Jun '07

15 Jun '07

I'm using LinuxBIOS on my Tyan s2892. I have a device that maps a lot of the memory space, but I'm struggling trying to get the Opteron to read and write to my device in larger blocks. I have set the variable MTRRs in the device driver to writeback (witnessed by /proc/mtrr), but I still get 64-bit accesses instead of 64-byte (cache line). Any suggestions? Thanks, Myles

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[LinuxBIOS] r2724 - in trunk/LinuxBIOSv2: src/mainboard/agami/aruma targets/agami/aruma
by svn＠openbios.org 14 Jun '07

14 Jun '07

Author: stepan Date: 2007-06-14 23:45:21 +0200 (Thu, 14 Jun 2007) New Revision: 2724 Modified: trunk/LinuxBIOSv2/src/mainboard/agami/aruma/Options.lb trunk/LinuxBIOSv2/src/mainboard/agami/aruma/acpi_tables_static.c trunk/LinuxBIOSv2/targets/agami/aruma/Config.lb Log: small agami aruma configuration updates (trivial) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/LinuxBIOSv2/src/mainboard/agami/aruma/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/agami/aruma/Options.lb 2007-06-14 19:52:27 UTC (rev 2723) +++ trunk/LinuxBIOSv2/src/mainboard/agami/aruma/Options.lb 2007-06-14 21:45:21 UTC (rev 2724) @@ -73,6 +73,10 @@ uses APIC_ID_OFFSET uses LIFT_BSP_APIC_ID +uses HW_MEM_HOLE_SIZEK +uses CONFIG_PCI_64BIT_PREF_MEM + + ### ### Build options ### @@ -100,6 +104,12 @@ default HAVE_HARD_RESET=1 ## +## set memory hole size +## +default HW_MEM_HOLE_SIZEK=0x300000 +#default HW_MEM_HOLE_SIZEK=0x200000 + +## ## Build code to export a programmable irq routing table ## default HAVE_PIRQ_TABLE=1 @@ -129,7 +139,6 @@ ## ## Build code for SMP support -## Only worry about 2 micro processors ## default CONFIG_SMP=1 default CONFIG_MAX_CPUS=8 @@ -139,7 +148,7 @@ default ENABLE_APIC_EXT_ID=1 default APIC_ID_OFFSET=0x10 -default LIFT_BSP_APIC_ID=0 +default LIFT_BSP_APIC_ID=1 # SDE was 0 #HT Unit ID offset #default HT_CHAIN_UNITID_BASE=0xa Modified: trunk/LinuxBIOSv2/src/mainboard/agami/aruma/acpi_tables_static.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/agami/aruma/acpi_tables_static.c 2007-06-14 19:52:27 UTC (rev 2723) +++ trunk/LinuxBIOSv2/src/mainboard/agami/aruma/acpi_tables_static.c 2007-06-14 21:45:21 UTC (rev 2724) @@ -21,11 +21,17 @@ unsigned int gsi_base=0x18, ioapic_nr=2, i; device_t dev=0; - /* create all subtables for 4p */ - current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 0); //SDE BSP APIC ID=0 + /* creare all subtables for 4p */ +#ifdef PRE_REVE + current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 0); current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 17); current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 2, 18); current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 3, 19); +#endif + current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 16); + current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 18); + current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 2, 20); + current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 3, 22); /* Write 8111 IOAPIC */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, 1, Modified: trunk/LinuxBIOSv2/targets/agami/aruma/Config.lb =================================================================== --- trunk/LinuxBIOSv2/targets/agami/aruma/Config.lb 2007-06-14 19:52:27 UTC (rev 2723) +++ trunk/LinuxBIOSv2/targets/agami/aruma/Config.lb 2007-06-14 21:45:21 UTC (rev 2724) @@ -12,7 +12,7 @@ romimage "normal" option ROM_SIZE = 512*1024-36*1024 option USE_FALLBACK_IMAGE=0 - option ROM_IMAGE_SIZE=0x16000 + option ROM_IMAGE_SIZE=0x17000 option XIP_ROM_SIZE=0x20000 option LINUXBIOS_EXTRA_VERSION=".0-normal" payload ../../../../../../filo.elf @@ -20,7 +20,7 @@ romimage "fallback" option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x16000 + option ROM_IMAGE_SIZE=0x17000 option XIP_ROM_SIZE=0x20000 option LINUXBIOS_EXTRA_VERSION=".0-fallback" payload ../../../../../../filo.elf

1 0

[LinuxBIOS] r2723 build service
by LinuxBIOS information 14 Jun '07

14 Jun '07

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "uwe" checked in revision 2723 to the LinuxBIOS source repository and caused the following changes: Change Log: Fix the static device tree of the ASI MB-5BLMP target. This was broken in more than just one way. This version should be (more) correct. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of arima:hdama is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2723&device=hdama&vendor=… Configuration of artecgroup:dbe61 is still broken Compilation of ibm:e325 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2723&device=e325&vendor=i… Compilation of ibm:e326 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2723&device=e326&vendor=i… Compilation of iei:juki-511p is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2723&device=juki-511p&ven… Compilation of iwill:dk8s2 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2723&device=dk8s2&vendor=… Compilation of iwill:dk8x is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2723&device=dk8x&vendor=i… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, LinuxBIOS automatic build system

1 0

[LinuxBIOS] r353 - LinuxBIOSv3/lib
by svn＠openbios.org 14 Jun '07

14 Jun '07

Author: rminnich Date: 2007-06-14 22:00:58 +0200 (Thu, 14 Jun 2007) New Revision: 353 Modified: LinuxBIOSv3/lib/ram.c Log: Add prototypes for things we call. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: LinuxBIOSv3/lib/ram.c =================================================================== --- LinuxBIOSv3/lib/ram.c 2007-06-14 17:50:58 UTC (rev 352) +++ LinuxBIOSv3/lib/ram.c 2007-06-14 20:00:58 UTC (rev 353) @@ -19,6 +19,7 @@ */ #include <hlt.h> +#include <console.h> /** * Print an error message which says why the RAM initialization failed, @@ -32,6 +33,10 @@ hlt(); } +/* Northbridge or memory controller code must define these functions */ +void ram_set_registers(void *ctrl, int i); +int ram_set_spd_registers(void *ctrl, int i); +void ram_enable(int controllers, void *ctrl); /** * ram_initialize() is is the main RAM init function. *

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[LinuxBIOS] [PATCH] Fix static device tree of ASI MB-5BLMP target
by Uwe Hermann 14 Jun '07

14 Jun '07

See patch. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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[LinuxBIOS] r2723 - trunk/LinuxBIOSv2/src/mainboard/asi/mb_5blmp
by svn＠openbios.org 14 Jun '07

14 Jun '07

Author: uwe Date: 2007-06-14 21:52:27 +0200 (Thu, 14 Jun 2007) New Revision: 2723 Modified: trunk/LinuxBIOSv2/src/mainboard/asi/mb_5blmp/Config.lb Log: Fix the static device tree of the ASI MB-5BLMP target. This was broken in more than just one way. This version should be (more) correct. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/LinuxBIOSv2/src/mainboard/asi/mb_5blmp/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/asi/mb_5blmp/Config.lb 2007-06-14 17:00:50 UTC (rev 2722) +++ trunk/LinuxBIOSv2/src/mainboard/asi/mb_5blmp/Config.lb 2007-06-14 19:52:27 UTC (rev 2723) @@ -128,67 +128,43 @@ chip northbridge/amd/gx1 # Northbridge device pci_domain 0 on - device pci 0.0 on end - chip southbridge/amd/cs5530 # Southbridge - device pci 12.0 on - chip superio/nsc/pc87351 # Super I/O - device pnp 2e.0 on # PIC - io 0x60 = 0x20 - io 0x62 = 0xa0 - irq 0x70 = 2 - end - device pnp 2e.1 on # DMA - end - device pnp 2e.2 on # System Timer - io 0x60 = 0x40 - irq 0x70 = 0 - end - device pnp 2e.3 on # RTC - io 0x60 = 0x70 - irq 0x70 = 8 - end - device pnp 2e.4 on # Keyboard + Mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.5 on # PC Speaker - end - device pnp 2e.6 on # Math Coprocessor (FPU) - io 0x60 = 0xf0 - irq 0x70 = 13 - end - device pnp 2e.7 on # System board - end - device pnp 2e.8 on # Motherboard resources - end - device pnp 2e.9 on # PCI bus - end - device pnp 2e.c on # Motherboard resources - end - device pnp 2e.d on # Motherboard resources - end - device pnp 2e.e on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.f off # FDC - end - device pnp 2e.10 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.12 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end + device pci 0.0 on end # Host bridge + chip southbridge/amd/cs5530 # Southbridge + device pci 0f.0 off end # Ethernet (Realtek RTL8139B) + device pci 12.0 on # ISA bridge + chip superio/nsc/pc87351 # Super I/O + device pnp 2e.4 on # PS/2 keyboard (+ mouse?) + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + # irq 0x72 = 12 end - device pci 12.1 off end # SMI - device pci 12.2 on end # IDE - device pci 12.3 off end # Audio - device pci 12.4 off end # Video (VGA) + device pnp 2e.a on # PS/2 mouse + irq 0x70 = 12 + end + device pnp 2e.e on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.f off # Floppy + io 0x60 = 0x3f2 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.10 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.12 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + end end + device pci 12.1 off end # SMI + device pci 12.2 on end # IDE + device pci 12.3 on end # Audio + device pci 12.4 on end # VGA (onboard) # device pci 12.4 on # VGA (onboard) # chip drivers/pci/onboard # device pci 12.4 on end @@ -197,13 +173,12 @@ # # register "rom_address" = "0xfff00000" # 1 MB image # end # end - device pci 0f.0 off end # Ethernet (Realtek RTL8139B) device pci 13.0 on end # USB + register "ide0_enable" = "1" + register "ide1_enable" = "1" end end - chip cpu/amd/model_gx1 # CPU end - end

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[LinuxBIOS] r352 - LinuxBIOSv3/include
by svn＠openbios.org 14 Jun '07

14 Jun '07

Author: rminnich Date: 2007-06-14 19:50:58 +0200 (Thu, 14 Jun 2007) New Revision: 352 Added: LinuxBIOSv3/include/spd.h Log: we need spd.h Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Added: LinuxBIOSv3/include/spd.h =================================================================== --- LinuxBIOSv3/include/spd.h (rev 0) +++ LinuxBIOSv3/include/spd.h 2007-06-14 17:50:58 UTC (rev 352) @@ -0,0 +1,143 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2005 Digital Design Corporation + * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Serial Presence Detect (SPD) data stored on SDRAM modules. + * + * Datasheet: + * - Name: PC SDRAM Serial Presence Detect (SPD) Specification + * Revision 1.2A, December, 1997 + * - PDF: http://www.intel.com/design/chipsets/memory/spdsd12a.pdf + * + * Datasheet (alternative): + * - Name: SERIAL PRESENCE DETECT STANDARD, General Standard + * JEDEC Standard No. 21-C + * - PDF: http://www.jedec.org/download/search/4_01_02_00R9.PDF + */ + +#ifndef _SPD_H_ +#define _SPD_H_ + +/* Byte numbers. */ +#define SPD_NUM_MANUFACTURER_BYTES 0 /* Number of bytes used by module manufacturer */ +#define SPD_TOTAL_SPD_MEMORY_SIZE 1 /* Total SPD memory size */ +#define SPD_MEMORY_TYPE 2 /* (Fundamental) memory type */ +#define SPD_NUM_ROWS 3 /* Number of row address bits */ +#define SPD_NUM_COLUMNS 4 /* Number of column address bits */ +#define SPD_NUM_DIMM_BANKS 5 /* Number of module rows (banks) */ +#define SPD_MODULE_DATA_WIDTH_LSB 6 /* Module data width (LSB) */ +#define SPD_MODULE_DATA_WIDTH_MSB 7 /* Module data width (MSB) */ +#define SPD_MODULE_VOLTAGE 8 /* Module interface signal levels */ +#define SPD_MIN_CYCLE_TIME_AT_CAS_MAX 9 /* SDRAM cycle time (highest CAS latency), RAS access time (tRAC) */ +#define SPD_ACCESS_TIME_FROM_CLOCK 10 /* SDRAM access time from clock (highest CAS latency), CAS access time (Tac, tCAC) */ +#define SPD_DIMM_CONFIG_TYPE 11 /* Module configuration type */ +#define SPD_REFRESH 12 /* Refresh rate/type */ +#define SPD_PRIMARY_SDRAM_WIDTH 13 /* SDRAM width (primary SDRAM) */ +#define SPD_ERROR_CHECKING_SDRAM_WIDTH 14 /* Error checking SDRAM (data) width */ +#define SPD_MIN_CLOCK_DELAY_B2B_RAND_COLUMN 15 /* SDRAM device attributes, minimum clock delay for back to back random column */ +#define SPD_SUPPORTED_BURST_LENGTHS 16 /* SDRAM device attributes, burst lengths supported */ +#define SPD_NUM_BANKS_PER_SDRAM 17 /* SDRAM device attributes, number of banks on SDRAM device */ +#define SPD_ACCEPTABLE_CAS_LATENCIES 18 /* SDRAM device attributes, CAS latency */ +#define SPD_CS_LATENCY 19 /* SDRAM device attributes, CS latency */ +#define SPD_WE_LATENCY 20 /* SDRAM device attributes, WE latency */ +#define SPD_MODULE_ATTRIBUTES 21 /* SDRAM module attributes */ +#define SPD_DEVICE_ATTRIBUTES_GENERAL 22 /* SDRAM device attributes, general */ +#define SPD_SDRAM_CYCLE_TIME_2ND 23 /* SDRAM cycle time (2nd highest CAS latency) */ +#define SPD_ACCESS_TIME_FROM_CLOCK_2ND 24 /* SDRAM access from clock (2nd highest CAS latency) */ +#define SPD_SDRAM_CYCLE_TIME_3RD 25 /* SDRAM cycle time (3rd highest CAS latency) */ +#define SPD_ACCESS_TIME_FROM_CLOCK_3RD 26 /* SDRAM access from clock (3rd highest CAS latency) */ +#define SPD_MIN_ROW_PRECHARGE_TIME 27 /* Minimum row precharge time (Trp) */ +#define SPD_MIN_ROWACTIVE_TO_ROWACTIVE 28 /* Minimum row active to row active (Trrd) */ +#define SPD_MIN_RAS_TO_CAS_DELAY 29 /* Minimum RAS to CAS delay (Trcd) */ +#define SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY 30 /* Minimum RAS pulse width (Tras) */ +#define SPD_DENSITY_OF_EACH_ROW_ON_MODULE 31 /* Density of each row on module */ +#define SPD_CMD_SIGNAL_INPUT_SETUP_TIME 32 /* Command and address signal input setup time */ +#define SPD_CMD_SIGNAL_INPUT_HOLD_TIME 33 /* Command and address signal input hold time */ +#define SPD_DATA_SIGNAL_INPUT_SETUP_TIME 34 /* Data signal input setup time */ +#define SPD_DATA_SIGNAL_INPUT_HOLD_TIME 35 /* Data signal input hold time */ +#define SPD_SPD_DATA_REVISION_CODE 62 /* SPD data revision code */ +#define SPD_CHECKSUM_FOR_BYTES_0_TO_62 63 /* Checksum for bytes 0-62 */ +#define SPD_MANUFACTURER_JEDEC_ID_CODE 64 /* Manufacturer's JEDEC ID code, per EIA/JEP106 (bytes 64-71) */ +#define SPD_MANUFACTURING_LOCATION 72 /* Manufacturing location */ +#define SPD_MANUFACTURER_PART_NUMBER 73 /* Manufacturer's part number, in 6-bit ASCII (bytes 73-90) */ +#define SPD_REVISION_CODE 91 /* Revision code (bytes 91-92) */ +#define SPD_MANUFACTURING_DATE 93 /* Manufacturing date (byte 93: year, byte 94: week) */ +#define SPD_ASSEMBLY_SERIAL_NUMBER 95 /* Assembly serial number (bytes 95-98) */ +#define SPD_MANUFACTURER_SPECIFIC_DATA 99 /* Manufacturer specific data (bytes 99-125) */ +#define SPD_INTEL_SPEC_FOR_FREQUENCY 126 /* Intel specification for frequency */ +#define SPD_INTEL_SPEC_100_MHZ 127 /* Intel specification details for 100MHz support */ + +/* DRAM specifications use the following naming conventions for SPD locations */ +#define SPD_tRP SPD_MIN_ROW_PRECHARGE_TIME +#define SPD_tRRD SPD_MIN_ROWACTIVE_TO_ROWACTIVE +#define SPD_tRCD SPD_MIN_RAS_TO_CAS_DELAY +#define SPD_tRAS SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY +#define SPD_BANK_DENSITY SPD_DENSITY_OF_EACH_ROW_ON_MODULE +#define SPD_ADDRESS_CMD_HOLD SPD_CMD_SIGNAL_INPUT_HOLD_TIME +#define SPD_tRC 41 /* SDRAM Device Minimum Active to Active/Auto Refresh Time (tRC) */ +#define SPD_tRFC 42 /* SDRAM Device Minimum Auto Refresh to Active/Auto Refresh (tRFC) */ + + +/* SPD_MEMORY_TYPE values. */ +#define SPD_MEMORY_TYPE_FPM_DRAM 1 +#define SPD_MEMORY_TYPE_EDO 2 +#define SPD_MEMORY_TYPE_PIPELINED_NIBBLE 3 +#define SPD_MEMORY_TYPE_SDRAM 4 +#define SPD_MEMORY_TYPE_MULTIPLEXED_ROM 5 +#define SPD_MEMORY_TYPE_SGRAM_DDR 6 +#define SPD_MEMORY_TYPE_SDRAM_DDR 7 +#define SPD_MEMORY_TYPE_SDRAM_DDR2 8 + +/* SPD_MODULE_VOLTAGE values. */ +#define SPD_VOLTAGE_TTL 0 /* 5.0 Volt/TTL */ +#define SPD_VOLTAGE_LVTTL 1 /* LVTTL */ +#define SPD_VOLTAGE_HSTL 2 /* HSTL 1.5 */ +#define SPD_VOLTAGE_SSTL3 3 /* SSTL 3.3 */ +#define SPD_VOLTAGE_SSTL2 4 /* SSTL 2.5 */ + +/* SPD_DIMM_CONFIG_TYPE values. */ +#define ERROR_SCHEME_NONE 0 +#define ERROR_SCHEME_PARITY 1 +#define ERROR_SCHEME_ECC 2 + +/* SPD_ACCEPTABLE_CAS_LATENCIES values. */ +// TODO: Check values. +#define SPD_CAS_LATENCY_1_0 0x01 +#define SPD_CAS_LATENCY_1_5 0x02 +#define SPD_CAS_LATENCY_2_0 0x04 +#define SPD_CAS_LATENCY_2_5 0x08 +#define SPD_CAS_LATENCY_3_0 0x10 +#define SPD_CAS_LATENCY_3_5 0x20 +#define SPD_CAS_LATENCY_4_0 0x40 + +/* SPD_SUPPORTED_BURST_LENGTHS values. */ +#define SPD_BURST_LENGTH_1 1 +#define SPD_BURST_LENGTH_2 2 +#define SPD_BURST_LENGTH_4 4 +#define SPD_BURST_LENGTH_8 8 +#define SPD_BURST_LENGTH_PAGE (1 << 7) + +/* SPD_MODULE_ATTRIBUTES values. */ +#define MODULE_BUFFERED 1 +#define MODULE_REGISTERED 2 + +#endif /* _SPD_H_ */ +

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coreboot June 2007