coreboot June 2007

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[LinuxBIOS] r2722 build service
by LinuxBIOS information 14 Jun '07

14 Jun '07

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "jcrouse" checked in revision 2722 to the LinuxBIOS source repository and caused the following changes: Change Log: his patch fixes the CAS map for -.5 and -1 CAS settings. The -.5 setting should only shift the mask one bit, not two. Signed-off-by: Marc Jones <marc.jones(a)amd.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Jordan Crouse <jordan.crouse(a)amd.com> Build Log: Compilation of arima:hdama is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2722&device=hdama&vendor=… Configuration of artecgroup:dbe61 is still broken Compilation of ibm:e325 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2722&device=e325&vendor=i… Compilation of ibm:e326 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2722&device=e326&vendor=i… Compilation of iei:juki-511p is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2722&device=juki-511p&ven… Compilation of iwill:dk8s2 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2722&device=dk8s2&vendor=… Compilation of iwill:dk8x is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2722&device=dk8x&vendor=i… If something broke during this checkin please be a pain in jcrouse's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, LinuxBIOS automatic build system

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[LinuxBIOS] r351 - LinuxBIOSv3/arch/x86
by svn＠openbios.org 14 Jun '07

14 Jun '07

Author: rminnich Date: 2007-06-14 19:45:35 +0200 (Thu, 14 Jun 2007) New Revision: 351 Added: LinuxBIOSv3/arch/x86/geodelx.c Log: This patch adds a file for geodelx cpu-specific support. It combines into one relatively small file (582 lines or so) all the tricky bits of the LX. This code is "known good" from V2. Per new standards, naming conventions have changed. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Added: LinuxBIOSv3/arch/x86/geodelx.c =================================================================== --- LinuxBIOSv3/arch/x86/geodelx.c (rev 0) +++ LinuxBIOSv3/arch/x86/geodelx.c 2007-06-14 17:45:35 UTC (rev 351) @@ -0,0 +1,577 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2006 Indrek Kruusa <indrek.kruusa(a)artecdesign.ee> + * Copyright (C) 2006 Ronald G. Minnich <rminnich(a)gmail.com> + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <types.h> +#include <lib.h> +#include <console.h> +#include <device/device.h> +#include <device/pci.h> +#include <string.h> +#include <msr.h> +#include <amd_geodelx.h> +#include <spd.h> +#include <io.h> + +/* all these functions used to be in a lot of fiddly little files. To + * make it easier to find functions, we are merging them here. This + * file is our first real cpu-specific support file and should serve + * as a model for v3 cpu-specific support. So, warning, you might + * think it makes sense to split this file up, but we've tried that, + * and it sucks. + */ + +/** + * geodelx_msr_init Set up Geode LX registers for sane behaviour. Set + * all low memory (under 1MB) to write back. Do some setup for cache + * as ram as well. + */ +void geodelx_msr_init(void) +{ + msr_t msr; + /* Setup access to the cache for under 1MB. */ + msr.hi = 0x24fffc02; + msr.lo = 0x1000A000; /* 0-A0000 write back */ + wrmsr(CPU_RCONF_DEFAULT, msr); + + msr.hi = 0x0; /* write back */ + msr.lo = 0x0; + wrmsr(CPU_RCONF_A0_BF, msr); + wrmsr(CPU_RCONF_C0_DF, msr); + wrmsr(CPU_RCONF_E0_FF, msr); + + /* Setup access to the cache for under 640K. Note MC not setup yet. */ + msr.hi = 0x20000000; + msr.lo = 0xfff80; + wrmsr(MSR_GLIU0 + 0x20, msr); + + msr.hi = 0x20000000; + msr.lo = 0x80fffe0; + wrmsr(MSR_GLIU0 + 0x21, msr); + + msr.hi = 0x20000000; + msr.lo = 0xfff80; + wrmsr(MSR_GLIU1 + 0x20, msr); + + msr.hi = 0x20000000; + msr.lo = 0x80fffe0; + wrmsr(MSR_GLIU1 + 0x21, msr); + +} + + +/** + * start_time1 Starts Timer 1 for port 61 use. FIXME try to figure + * out what these values mean. + */ +void start_timer1(void) +{ + outb(0x56, 0x43); + outb(0x12, 0x41); +} + +/** + * system_preinit Very early initialization needed for almost + * everything else. Currently, all we do is start timer1. + */ +void system_preinit(void) +{ + start_timer1(); +} + +/* cpu bug management */ +/** + * + * pci_deadlock Bugtool #465 and #609 PCI cache deadlock There is + * also fix code in cache and PCI functions. This bug is very is + * pervasive. + * + */ +static void pci_deadlock(void) +{ + msr_t msr; + + /* + * forces serialization of all load misses. Setting this bit prevents the + * DM pipe from backing up if a read request has to be held up waiting + * for PCI writes to complete. + */ + msr = rdmsr(CPU_DM_CONFIG0); + msr.lo |= DM_CONFIG0_LOWER_MISSER_SET; + wrmsr(CPU_DM_CONFIG0, msr); + + /* write serialize memory hole to PCI. Need to unWS when something is + * shadowed regardless of cachablility. + */ + msr.lo = 0x021212121; + msr.hi = 0x021212121; + wrmsr(CPU_RCONF_A0_BF, msr); + wrmsr(CPU_RCONF_C0_DF, msr); + wrmsr(CPU_RCONF_E0_FF, msr); +} + +/** disable_memory_reorder PBZ 3659: The MC reordered transactions + * incorrectly and breaks coherency. Disable reording and take a + * potential performance hit. This is safe to do here and not in + * MC init since there is nothing to maintain coherency with and + * the cache is not enabled yet. + */ +/****************************************************************************/ +static void disable_memory_reorder(void) +{ + msr_t msr; + + msr = rdmsr(MC_CF8F_DATA); + msr.hi |= CF8F_UPPER_REORDER_DIS_SET; + wrmsr(MC_CF8F_DATA, msr); +} + +/** + * Fix up register settings to manage known CPU bugs. For cpu + * version C3. Should be the only released version + */ +void cpu_bug(void) +{ + pci_deadlock(); + disable_memory_reorder(); + printk(BIOS_DEBUG, "Done cpubug fixes \n"); +} + +/** + * Reset the phase locked loop hardware. After power on as part of + * this operation, we have to set the clock hardware and reboot. Thus, + * we have to know if we have been here before. To do this, we use the + * RSTPLL_LOWER_SWFLAGS_SHIFT flag in the msrGlcpSysRstpll. Also, the + * clocks can either be configured via passed-in parameters or + * hardware straps. Once set, we yank the hardware reset line and + * hlt. We should never reach the hlt, but one never knows. + * + * @param manualconf If non-zero, use passed-in parameters to + * determine how to configure pll -- manual or automagic. + * If manual, use passed-in parameters pll_hi and pll_lo + * @param pll_hi value to use for the high 32 bits of the pll msr + * @param pll_lo value to use for the low 32 bits of the pll msr + */ +void pll_reset(int manualconf, u32 pll_hi, u32 pll_lo) +{ + msr_t msrGlcpSysRstpll; + + msrGlcpSysRstpll = rdmsr(GLCP_SYS_RSTPLL); + + printk(BIOS_DEBUG, + "_MSR GLCP_SYS_RSTPLL (%08x) value is: %08x:%08x\n", msrGlcpSysRstpll.hi, msrGlcpSysRstpll.lo); + post_code(POST_PLL_INIT); + + if (!(msrGlcpSysRstpll.lo & (1 << RSTPLL_LOWER_SWFLAGS_SHIFT))) { + printk(BIOS_DEBUG,"Configuring PLL\n"); + if (manualconf) { + post_code(POST_PLL_MANUAL); + /* CPU and GLIU mult/div (GLMC_CLK = GLIU_CLK / 2) */ + msrGlcpSysRstpll.hi = pll_hi; + + /* Hold Count - how long we will sit in reset */ + msrGlcpSysRstpll.lo = pll_lo; + } else { + /*automatic configuration (straps) */ + post_code(POST_PLL_STRAP); + msrGlcpSysRstpll.lo &= + ~(0xFF << RSTPPL_LOWER_HOLD_COUNT_SHIFT); + msrGlcpSysRstpll.lo |= + (0xDE << RSTPPL_LOWER_HOLD_COUNT_SHIFT); + msrGlcpSysRstpll.lo &= + ~(RSTPPL_LOWER_COREBYPASS_SET | + RSTPPL_LOWER_MBBYPASS_SET); + msrGlcpSysRstpll.lo |= + RSTPPL_LOWER_COREPD_SET | RSTPPL_LOWER_CLPD_SET; + } + /* Use SWFLAGS to remember: "we've already been here" */ + msrGlcpSysRstpll.lo |= (1 << RSTPLL_LOWER_SWFLAGS_SHIFT); + + /* "reset the chip" value */ + msrGlcpSysRstpll.lo |= RSTPPL_LOWER_CHIP_RESET_SET; + wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll); + + /* You should never get here..... The chip has reset. */ + printk(BIOS_EMERG,"CONFIGURING PLL FAILURE -- HALT\n"); + post_code(POST_PLL_RESET_FAIL); + __asm__ __volatile__("hlt\n"); + + } + printk(BIOS_DEBUG, "Done pll_reset\n"); + return; +} + + +/** + * Return the CPU clock rate. Rates in this system are always returned + * as multkiples of 33 Mhz. + * + */ +u32 cpu_speed(void) +{ + u32 speed; + msr_t msr; + + msr = rdmsr(GLCP_SYS_RSTPLL); + speed = ((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & 0x1F) + 1) * 333) / 10; + if ((((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & 0x1F) + 1) * 333) % 10) > 5) { + ++speed; + } + return (speed); +} + +/** + * Return the Geode Link clock rate. Rates in this system are always + * returned as multkiples of 33 Mhz. + * + */ +u32 geode_link_speed(void) +{ + unsigned int speed; + msr_t msr; + + msr = rdmsr(GLCP_SYS_RSTPLL); + speed = ((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & 0x1F) + 1) * 333) / 10; + if ((((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & 0x1F) + 1) * 333) % 10) > 5) { + ++speed; + } + return (speed); +} + + +/** + * Return the PCI bus clock rate. Rates in this system are always + * returned as multkiples of 33 Mhz. + * + */ +u32 pci_speed(void) +{ + msr_t msr; + + msr = rdmsr(GLCP_SYS_RSTPLL); + if (msr.hi & (1 << RSTPPL_LOWER_PCISPEED_SHIFT)) { + return (66); + } else { + return (33); + } +} + +/** + * set_delay_control. This is Black Magic DRAM timing + * juju(http://www.thefreedictionary.com/juju) Dram delay depends on + * cpu clock, memory bus clock, memory bus loading, memory bus + * termination, your middle initial (ha! caught you!), Geode Link + * clock rate, and dram timing specifications. From this the code + * computes a number which is "known to work". No, hardware is not an + * exact science. And, finally, if an FS2 (jtag debugger) is hooked + * up, then just don't to anything. This code was written by a master + * of the Dark Arts at AMD and should not be modified in any way. + * + * @param num_banks How many banks of DRAM there are + * @param dimm0 DIMM 0 SMBus address + * @param dimm1 DIMM 1 SMBus address + * @param sram_width Data width of the SDRAM + */ + +void set_delay_control(u8 dimm0, u8 dimm1) +{ + u32 msrnum, glspeed; + u8 spdbyte0, spdbyte1; + int numdimms = 0; + msr_t msr; + + glspeed = geode_link_speed(); + + /* fix delay controls for DM and IM arrays */ + msrnum = CPU_BC_MSS_ARRAY_CTL0; + msr.hi = 0; + msr.lo = 0x2814D352; + wrmsr(msrnum, msr); + + msrnum = CPU_BC_MSS_ARRAY_CTL1; + msr.hi = 0; + msr.lo = 0x1068334D; + wrmsr(msrnum, msr); + + msrnum = CPU_BC_MSS_ARRAY_CTL2; + msr.hi = 0x00000106; + msr.lo = 0x83104104; + wrmsr(msrnum, msr); + + msrnum = GLCP_FIFOCTL; + msr = rdmsr(msrnum); + msr.hi = 0x00000005; + wrmsr(msrnum, msr); + + /* Enable setting */ + msrnum = CPU_BC_MSS_ARRAY_CTL_ENA; + msr.hi = 0; + msr.lo = 0x00000001; + wrmsr(msrnum, msr); + + /* Debug Delay Control Setup Check + * + * Leave it alone if it has been setup. FS2 or something is here. + */ + msrnum = GLCP_DELAY_CONTROLS; + msr = rdmsr(msrnum); + if (msr.lo & ~(0x7C0)) { + return; + } + + /* + * Delay Controls based on DIMM loading. UGH! + * # of Devices = Module Width (SPD6) / Device Width(SPD13) * Physical Banks(SPD5) + * Note - We only support module width of 64. + */ + spdbyte0 = smbus_read_byte(dimm0, SPD_PRIMARY_SDRAM_WIDTH); + if (spdbyte0 != 0xFF) { + numdimms++; + spdbyte0 = (unsigned char)64 / spdbyte0 * + (unsigned char)(smbus_read_byte(dimm0, SPD_NUM_DIMM_BANKS)); + } else { + spdbyte0 = 0; + } + + spdbyte1 = smbus_read_byte(dimm1, SPD_PRIMARY_SDRAM_WIDTH); + if (spdbyte1 != 0xFF) { + numdimms++; + spdbyte1 = (unsigned char)64 / spdbyte1 * + (unsigned char)(smbus_read_byte(dimm1, SPD_NUM_DIMM_BANKS)); + } else { + spdbyte1 = 0; + } + +/* The current thinking. Subject to change... + +; "FUTURE ROBUSTNESS" PROPOSAL +; ---------------------------- +; DIMM Max MBUS MC 0x2000001A bits 26:24 +;DIMMs devices Frequency MCP 0x4C00000F Setting vvv +;----- ------- --------- ---------------------- ---------- +;1 4 400MHz 0x82*100FF 0x56960004 4 +;1 8 400MHz 0x82*100AA 0x56960004 4 +;1 16 400MHz 0x82*10055 0x56960004 4 +; +;2 4,4 400MHz 0x82710000 0x56960004 4 +;2 8,8 400MHz 0xC27100A5 0x56960004 4 *** OUT OF PUBLISHED ENVELOPE *** +; +;2 16,4 >333 0xB27100A5 0x56960004 4 *** OUT OF PUBLISHED ENVELOPE *** +;2 16,8 >333 0xB27100A5 0x56960004 4 *** OUT OF PUBLISHED ENVELOPE *** +;2 16,16 >333 0xB2710000 0x56960004 4 *** OUT OF PUBLISHED ENVELOPE *** +; +;1 4 <=333MHz 0x83*100FF 0x56960004 3 +;1 8 <=333MHz 0x83*100AA 0x56960004 3 +;1 16 <=333MHz 0x83*100AA 0x56960004 3 +; +;2 4,4 <=333MHz 0x837100A5 0x56960004 3 +;2 8,8 <=333MHz 0x937100A5 0x56960004 3 +; +;2 16,4 <=333MHz 0xB37100A5 0x56960004 3 *** OUT OF PUBLISHED ENVELOPE *** +;2 16,8 <=333MHz 0xB37100A5 0x56960004 3 *** OUT OF PUBLISHED ENVELOPE *** +;2 16,16 <=333MHz 0xB37100A5 0x56960004 3 *** OUT OF PUBLISHED ENVELOPE *** +;========================================================================= +;* - Bit 55 (disable SDCLK 1,3,5) should be set if there is a single DIMM in slot 0, +; but it should be clear for all 2 DIMM settings and if a single DIMM is in slot 1. +; Bits 54:52 should always be set to '111'. + +;No VTT termination +;------------------------------------- +;ADDR/CTL have 22 ohm series R +;DQ/DQM/DQS have 33 ohm series R +; +; DIMM Max MBUS +;DIMMs devices Frequency MCP 0x4C00000F Setting +;----- ------- --------- ---------------------- +;1 4 400MHz 0xF2F100FF 0x56960004 4 The MC changes improve Salsa. +;1 8 400MHz 0xF2F100FF 0x56960004 4 Delay controls no real change, +;1 4 <=333MHz 0xF2F100FF 0x56960004 3 just fixing typo in left side. +;1 8 <=333MHz 0xF2F100FF 0x56960004 3 +;1 16 <=333MHz 0xF2F100FF 0x56960004 3 +*/ + msr.hi = msr.lo = 0; + + if (spdbyte0 == 0 || spdbyte1 == 0) { + /* one dimm solution */ + if (spdbyte1 == 0) { + msr.hi |= 0x000800000; + } + spdbyte0 += spdbyte1; + if (spdbyte0 > 8) { + /* large dimm */ + if (glspeed < 334) { + msr.hi |= 0x0837100AA; + msr.lo |= 0x056960004; + } else { + msr.hi |= 0x082710055; + msr.lo |= 0x056960004; + } + } else if (spdbyte0 > 4) { + /* medium dimm */ + if (glspeed < 334) { + msr.hi |= 0x0837100AA; + msr.lo |= 0x056960004; + } else { + msr.hi |= 0x0827100AA; + msr.lo |= 0x056960004; + } + } else { + /* small dimm */ + if (glspeed < 334) { + msr.hi |= 0x0837100FF; + msr.lo |= 0x056960004; + } else { + msr.hi |= 0x0827100FF; + msr.lo |= 0x056960004; + } + } + } else { + /* two dimm solution */ + spdbyte0 += spdbyte1; + if (spdbyte0 > 24) { + /* huge dimms */ + if (glspeed < 334) { + msr.hi |= 0x0B37100A5; + msr.lo |= 0x056960004; + } else { + msr.hi |= 0x0B2710000; + msr.lo |= 0x056960004; + } + } else if (spdbyte0 > 16) { + /* large dimms */ + if (glspeed < 334) { + msr.hi |= 0x0B37100A5; + msr.lo |= 0x056960004; + } else { + msr.hi |= 0x0B27100A5; + msr.lo |= 0x056960004; + } + } else if (spdbyte0 >= 8) { + /* medium dimms */ + if (glspeed < 334) { + msr.hi |= 0x0937100A5; + msr.lo |= 0x056960004; + } else { + msr.hi |= 0x0C27100A5; + msr.lo |= 0x056960004; + } + } else { + /* small dimms */ + if (glspeed < 334) { + msr.hi |= 0x0837100A5; + msr.lo |= 0x056960004; + } else { + msr.hi |= 0x082710000; + msr.lo |= 0x056960004; + } + } + } + wrmsr(GLCP_DELAY_CONTROLS, msr); + return; +} + +/** + * cpu_reg_init. All cpu register settings, here in one place, and + * done in the proper order. + * + * @param debug_clock_disable Disable the debug clock to save power. Currently ignored, but we need to + * pick this up from a CMOS setting in future. + * @param dimm0 SMBus address of dimm0 (mainboard dependent) + * @param dimm1 SMBus address of dimm1 (mainboard dependent) + */ +void cpu_reg_init(int debug_clock_disable, u8 dimm0, u8 dimm1) +{ + int msrnum; + msr_t msr; + + /* Castle 2.0 BTM periodic sync period. */ + /* [40:37] 1 sync record per 256 bytes */ + msrnum = CPU_PF_CONF; + msr = rdmsr(msrnum); + msr.hi |= (0x8 << 5); + wrmsr(msrnum, msr); + + /* + ; Castle performance setting. + ; Enable Quack for fewer re-RAS on the MC + */ + msrnum = GLIU0_ARB; + msr = rdmsr(msrnum); + msr.hi &= ~ARB_UPPER_DACK_EN_SET; + msr.hi |= ARB_UPPER_QUACK_EN_SET; + wrmsr(msrnum, msr); + + msrnum = GLIU1_ARB; + msr = rdmsr(msrnum); + msr.hi &= ~ARB_UPPER_DACK_EN_SET; + msr.hi |= ARB_UPPER_QUACK_EN_SET; + wrmsr(msrnum, msr); + + /* GLIU port active enable, limit south pole masters (AES and PCI) to one outstanding transaction. */ + msrnum = GLIU1_PORT_ACTIVE; + msr = rdmsr(msrnum); + msr.lo &= ~0x880; + wrmsr(msrnum, msr); + + /* Set the Delay Control in GLCP */ + set_delay_control(dimm0, dimm1); + + /* Enable RSDC */ + msrnum = CPU_AC_SMM_CTL; + msr = rdmsr(msrnum); + msr.lo |= SMM_INST_EN_SET; + wrmsr(msrnum, msr); + + /* FPU imprecise exceptions bit */ + msrnum = CPU_FPU_MSR_MODE; + msr = rdmsr(msrnum); + msr.lo |= FPU_IE_SET; + wrmsr(msrnum, msr); + + /* Power Savers (Do after BIST) */ + /* Enable Suspend on HLT & PAUSE instructions */ + msrnum = CPU_XC_CONFIG; + msr = rdmsr(msrnum); + msr.lo |= XC_CONFIG_SUSP_ON_HLT | XC_CONFIG_SUSP_ON_PAUSE; + wrmsr(msrnum, msr); + + /* Enable SUSP and allow TSC to run in Suspend (keep speed detection happy) */ + msrnum = CPU_BC_CONF_0; + msr = rdmsr(msrnum); + msr.lo |= TSC_SUSP_SET | SUSP_EN_SET; + msr.lo &= 0x0F0FFFFFF; + msr.lo |= 0x002000000; /* PBZ213: Set PAUSEDLY = 2 */ + wrmsr(msrnum, msr); + + /* Disable the debug clock to save power. */ + /* NOTE: leave it enabled for fs2 debug */ + if (debug_clock_disable && 0){ + msrnum = GLCP_DBGCLKCTL; + msr.hi = 0; + msr.lo = 0; + wrmsr(msrnum, msr); + } + + /* Setup throttling delays to proper mode if it is ever enabled. */ + msrnum = GLCP_TH_OD; + msr.hi = 0; + msr.lo = 0x00000603C; + wrmsr(msrnum, msr); +}

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[LinuxBIOS] i440bx RAM initialization code (SPD)
by Alfred Wanga 14 Jun '07

14 Jun '07

Ok, so I've been working on porting the SPD code, and this patch is what I've got so far. Here are some of the outstanding issues/changes: * SPD register code (tested using PCI/SMBus Dumps) I ported the v1 assembly and made some modifications when the numbers didn't really add up on my machine (particularly the DRB registers) and added some minor functionality (CAS2/3 detection) that may or may not work, although based on the results from the dataset I used, it should work (at least for my current setup). * PMCR - When should it be updated? Looking at the assembly, it seems as though it's ok to just set the final value before the RAM refresh code instead of waiting until afterwards, but I don't know for sure, so I left the original code alone. Judging from some of the recent 440bx discussions, it may not make much of a difference anyway. * sdram_enable delays I changed all the RAM timing delays (tRP, tRC, tMRD) to 1usec, since the timings are on the order of hundreds of nanoseconds (according to SPD values) and the smallest resolution timer available seems to be udelay() anyway. It should work for any SDRAM, and shaves a few milliseconds off previous code. Incidentally, I noticed that the v1 assembly sets the clock idle value to 32 in the PGPOL register until SDRAM refresh is enabled, but it seems like it should eventually be set back to zero (which is what the patch does). Does it matter? Anyway, enough verbosity... take a look and see what you think. Unfortunately, besides testing the SPD code on memory dumps, I haven't tested the image. Alfred

5 8

[LinuxBIOS] [PATCH] Geode LX CAS setting fix
by Marc Jones 14 Jun '07

14 Jun '07

See attached patch. Thanks! Marc -- Marc Jones Senior Software Engineer (970) 226-9684 Office mailto:Marc.Jones@amd.com http://www.amd.com/embeddedprocessors This patch fixes the CAS map for -.5 and -1 CAS settings. The -.5 setting should only shift the mask one bit, not two. Signed-off-by: Marc Jones <marc.jones(a)amd.com> Index: LinuxBIOSv2/src/northbridge/amd/lx/raminit.c =================================================================== --- LinuxBIOSv2.orig/src/northbridge/amd/lx/raminit.c 2007-06-13 17:01:03.000000000 -0600 +++ LinuxBIOSv2/src/northbridge/amd/lx/raminit.c 2007-06-13 17:01:03.000000000 -0600 @@ -151,7 +151,7 @@ } /* I don't think you need this check. - if (spd_byte0 < 0xA0 || spd_byte0 < 0xA0){ + if (spd_byte0 >= 0xA0 || spd_byte1 >= 0xA0){ print_debug("DIMM overclocked. Check GeodeLink Speed\n"); POST_CODE(POST_PLL_MEM_FAIL); __asm__ __volatile__("hlt\n"); @@ -231,7 +231,7 @@ ;* Destroys: We really use everything ! ;*****************************************************************************/ uint16_t glspeed, dimm_speed; - uint8_t spd_byte, casmap0, casmap1; + uint8_t spd_byte, casmap0, casmap1, casmap_shift; msr_t msr; glspeed = GeodeLinkSpeed(); @@ -246,25 +246,24 @@ dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F))); if (dimm_speed >= glspeed) { + casmap_shift = 1; /* -.5 is a shift of 1 */ /* IF -1 timing is supported, check -1 timing > GeodeLink */ spd_byte = spd_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_3RD); if (spd_byte != 0) { /* Turn SPD ns time into MHZ. Check what the asm does to this math. */ dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F))); - if (dimm_speed <= glspeed) { - /* set we can use -.5 timing but not -1 */ - spd_byte = 31 - __builtin_clz((uint32_t) casmap0); - /* just want bits in the lower byte since we have to cast to a 32 */ - casmap0 &= 0xFF << (--spd_byte); + if (dimm_speed >= glspeed) { + casmap_shift = 2; /* -1 is a shift of 2 */ } - } /*MIN_CYCLE_10 !=0 */ + } /* SPD_SDRAM_CYCLE_TIME_3RD (-1) !=0 */ } else { - /* Timing_05 < GLspeed, can't use -.5 or -1 timing */ - spd_byte = 31 - __builtin_clz((uint32_t) casmap0); - /* just want bits in the lower byte since we have to cast to a 32 */ - casmap0 &= 0xFF << (spd_byte); + casmap_shift = 0; } - } /*MIN_CYCLE_05 !=0 */ + } /* SPD_SDRAM_CYCLE_TIME_2ND (-.5) !=0 */ + /* set the casmap based on the shift to limit possible CAS settings */ + spd_byte = 31 - __builtin_clz((uint32_t) casmap0); + /* just want bits in the lower byte since we have to cast to a 32 */ + casmap0 &= 0xFF << (spd_byte - casmap_shift); } else { /* No DIMM */ casmap0 = 0; } @@ -278,25 +277,25 @@ /* Turn SPD ns time into MHZ. Check what the asm does to this math. */ dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F))); if (dimm_speed >= glspeed) { + casmap_shift = 1; /* -.5 is a shift of 1 */ /* IF -1 timing is supported, check -1 timing > GeodeLink */ spd_byte = spd_read_byte(DIMM1, SPD_SDRAM_CYCLE_TIME_3RD); if (spd_byte != 0) { /* Turn SPD ns time into MHZ. Check what the asm does to this math. */ dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F))); - if (dimm_speed <= glspeed) { - /* set we can use -.5 timing but not -1 */ - spd_byte = 31 - __builtin_clz((uint32_t) casmap1); - /* just want bits in the lower byte since we have to cast to a 32 */ - casmap1 &= 0xFF << (--spd_byte); + if (dimm_speed >= glspeed) { + casmap_shift = 2; /* -1 is a shift of 2 */ } - } /*MIN_CYCLE_10 !=0 */ + /* note that the -1 result doesn't need to change the available CAS map */ + } /* SPD_SDRAM_CYCLE_TIME_3RD (-1) !=0 */ } else { - /* Timing_05 < GLspeed, can't use -.5 or -1 timing */ - spd_byte = 31 - __builtin_clz((uint32_t) casmap1); - /* just want bits in the lower byte since we have to cast to a 32 */ - casmap1 &= 0xFF << (spd_byte); + casmap_shift = 0; } - } /*MIN_CYCLE_05 !=0 */ + } /* SPD_SDRAM_CYCLE_TIME_2ND (-.5) !=0 */ + /* set the casmap based on the shift to limit possible CAS settings */ + spd_byte = 31 - __builtin_clz((uint32_t) casmap1); + /* just want bits in the lower byte since we have to cast to a 32 */ + casmap1 &= 0xFF << (spd_byte - casmap_shift); } else { /* No DIMM */ casmap1 = 0; }

3 2

[LinuxBIOS] r2722 - trunk/LinuxBIOSv2/src/northbridge/amd/lx
by svn＠openbios.org 14 Jun '07

14 Jun '07

Author: jcrouse Date: 2007-06-14 19:00:50 +0200 (Thu, 14 Jun 2007) New Revision: 2722 Modified: trunk/LinuxBIOSv2/src/northbridge/amd/lx/raminit.c Log: his patch fixes the CAS map for -.5 and -1 CAS settings. The -.5 setting should only shift the mask one bit, not two. Signed-off-by: Marc Jones <marc.jones(a)amd.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Jordan Crouse <jordan.crouse(a)amd.com> Modified: trunk/LinuxBIOSv2/src/northbridge/amd/lx/raminit.c =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/amd/lx/raminit.c 2007-06-14 12:04:19 UTC (rev 2721) +++ trunk/LinuxBIOSv2/src/northbridge/amd/lx/raminit.c 2007-06-14 17:00:50 UTC (rev 2722) @@ -151,7 +151,7 @@ } /* I don't think you need this check. - if (spd_byte0 < 0xA0 || spd_byte0 < 0xA0){ + if (spd_byte0 >= 0xA0 || spd_byte1 >= 0xA0){ print_debug("DIMM overclocked. Check GeodeLink Speed\n"); POST_CODE(POST_PLL_MEM_FAIL); __asm__ __volatile__("hlt\n"); @@ -231,7 +231,7 @@ ;* Destroys: We really use everything ! ;*****************************************************************************/ uint16_t glspeed, dimm_speed; - uint8_t spd_byte, casmap0, casmap1; + uint8_t spd_byte, casmap0, casmap1, casmap_shift; msr_t msr; glspeed = GeodeLinkSpeed(); @@ -246,25 +246,24 @@ dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F))); if (dimm_speed >= glspeed) { + casmap_shift = 1; /* -.5 is a shift of 1 */ /* IF -1 timing is supported, check -1 timing > GeodeLink */ spd_byte = spd_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_3RD); if (spd_byte != 0) { /* Turn SPD ns time into MHZ. Check what the asm does to this math. */ dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F))); - if (dimm_speed <= glspeed) { - /* set we can use -.5 timing but not -1 */ - spd_byte = 31 - __builtin_clz((uint32_t) casmap0); - /* just want bits in the lower byte since we have to cast to a 32 */ - casmap0 &= 0xFF << (--spd_byte); + if (dimm_speed >= glspeed) { + casmap_shift = 2; /* -1 is a shift of 2 */ } - } /*MIN_CYCLE_10 !=0 */ + } /* SPD_SDRAM_CYCLE_TIME_3RD (-1) !=0 */ } else { - /* Timing_05 < GLspeed, can't use -.5 or -1 timing */ - spd_byte = 31 - __builtin_clz((uint32_t) casmap0); - /* just want bits in the lower byte since we have to cast to a 32 */ - casmap0 &= 0xFF << (spd_byte); + casmap_shift = 0; } - } /*MIN_CYCLE_05 !=0 */ + } /* SPD_SDRAM_CYCLE_TIME_2ND (-.5) !=0 */ + /* set the casmap based on the shift to limit possible CAS settings */ + spd_byte = 31 - __builtin_clz((uint32_t) casmap0); + /* just want bits in the lower byte since we have to cast to a 32 */ + casmap0 &= 0xFF << (spd_byte - casmap_shift); } else { /* No DIMM */ casmap0 = 0; } @@ -278,25 +277,25 @@ /* Turn SPD ns time into MHZ. Check what the asm does to this math. */ dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F))); if (dimm_speed >= glspeed) { + casmap_shift = 1; /* -.5 is a shift of 1 */ /* IF -1 timing is supported, check -1 timing > GeodeLink */ spd_byte = spd_read_byte(DIMM1, SPD_SDRAM_CYCLE_TIME_3RD); if (spd_byte != 0) { /* Turn SPD ns time into MHZ. Check what the asm does to this math. */ dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F))); - if (dimm_speed <= glspeed) { - /* set we can use -.5 timing but not -1 */ - spd_byte = 31 - __builtin_clz((uint32_t) casmap1); - /* just want bits in the lower byte since we have to cast to a 32 */ - casmap1 &= 0xFF << (--spd_byte); + if (dimm_speed >= glspeed) { + casmap_shift = 2; /* -1 is a shift of 2 */ } - } /*MIN_CYCLE_10 !=0 */ + /* note that the -1 result doesn't need to change the available CAS map */ + } /* SPD_SDRAM_CYCLE_TIME_3RD (-1) !=0 */ } else { - /* Timing_05 < GLspeed, can't use -.5 or -1 timing */ - spd_byte = 31 - __builtin_clz((uint32_t) casmap1); - /* just want bits in the lower byte since we have to cast to a 32 */ - casmap1 &= 0xFF << (spd_byte); + casmap_shift = 0; } - } /*MIN_CYCLE_05 !=0 */ + } /* SPD_SDRAM_CYCLE_TIME_2ND (-.5) !=0 */ + /* set the casmap based on the shift to limit possible CAS settings */ + spd_byte = 31 - __builtin_clz((uint32_t) casmap1); + /* just want bits in the lower byte since we have to cast to a 32 */ + casmap1 &= 0xFF << (spd_byte - casmap_shift); } else { /* No DIMM */ casmap1 = 0; }

1 0

[LinuxBIOS] About CS5536 UART2 and USB boot !
by Gard xu 14 Jun '07

14 Jun '07

Hi all : My target is Geode LX800 + CS5536., Linuxbios rev2550 base on mainboard dbe61. It can boot linux(2.6.20) with IDE and work well.But now there are two questions trouble me some days. 1. MY target use CS5536's UART1 as COM1,It can work normally.When I try to use the CS5536's UART2 as a general serial COM2 but not the DDC(display data channel), It seem badly. I has set the registers about UART2 refer to CS5536 datashee in linuxbios( *1*. set bit 20:22 of msr 0x51400014 to 6 ; *2*. set msr 0x5140003e bit 1 and bit 4 as 1. * 3*. set GPIO3(RX) Input Enable and Input AUX1 select = 1 , set GPIO4(TX) output enable and output AUX1 select = 1.). After booting the OS, I read back the register above through my driver found that all preset value is zero,UART2 can't work. I try to set that registers again in my driver,this time it read back value is right, but UART2 still can't work. /dev/ttyS1, Line 1, UART: unknown, Port: 0x02f8, IRQ: 3 Baud_base: 115200, close_delay: 50, divisor: 0 closing_wait: 3000 Flags: spd_normal skip_test auto_irq why? maybe kernel use UART2's GPIO pin to act as DDC use,so it change my preset when linux is booting? or my configuration about UART2 is not correct ? 2. I has try to use ethboot5.2.6 to boot my system from USB Disk,when with the IDE on mainboard, It can boot well. but if without IDE,It will hang up at " checking if this processor honours the WP bit even in supervisor mode...ok " after starting the kernel. it seem strange.when I debug it in kernel, I found it cycle in calibrate.c---> function static unsigned long __devinit calibrate_delay_direct(void) all along. because the jiffies is not increase,so it cycle there. Here my question is: *1*.what diffrent about without IDE or not(PCI scanning will change some setup about linuxbios normal when without IDE? ),.why jiffies can't increase when withou IDE? it seems PIT 8254 interrupt problem lead it, what should I do to modify some setup in linuxbios to avoid this problem? Help me please :) thanks!!!

2 1

[LinuxBIOS] r2721 build service
by LinuxBIOS information 14 Jun '07

14 Jun '07

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "uwe" checked in revision 2721 to the LinuxBIOS source repository and caused the following changes: Change Log: Small bugfix in i82801xx_lpc.c. Signed-off-by: Corey Osgood <corey.osgood(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of arima:hdama is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2721&device=hdama&vendor=… Configuration of artecgroup:dbe61 is still broken Compilation of asus:mew-vm has been fixed Compilation of ibm:e325 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2721&device=e325&vendor=i… Compilation of ibm:e326 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2721&device=e326&vendor=i… Compilation of iei:juki-511p is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2721&device=juki-511p&ven… Compilation of iwill:dk8s2 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2721&device=dk8s2&vendor=… Compilation of iwill:dk8x is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2721&device=dk8x&vendor=i… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, LinuxBIOS automatic build system

1 0

[LinuxBIOS] r2720 build service
by LinuxBIOS information 14 Jun '07

14 Jun '07

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "uwe" checked in revision 2720 to the LinuxBIOS source repository and caused the following changes: Change Log: Add initial support for the Intel 82810 northbridge. Signed-off-by: Corey Osgood <corey.osgood(a)gmail.com> Acked-by: Joseph Smith <joe(a)smittys.pointclark.net> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of arima:hdama is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2720&device=hdama&vendor=… Configuration of artecgroup:dbe61 is still broken Configuration of asus:mew-vm has been fixed Compilation of ibm:e325 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2720&device=e325&vendor=i… Compilation of ibm:e326 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2720&device=e326&vendor=i… Compilation of iei:juki-511p is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2720&device=juki-511p&ven… Compilation of iwill:dk8s2 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2720&device=dk8s2&vendor=… Compilation of iwill:dk8x is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2720&device=dk8x&vendor=i… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, LinuxBIOS automatic build system

1 0

[LinuxBIOS] Strange reset loading linux on epia! was "EPIA hang after patch"
by Thomas Ekstrand 14 Jun '07

14 Jun '07

I got passed it! seemed to be a buggy flash and/or burn. The vt8231 is working with flashrom, except for the verify :/ Anyway I rebuilt and reflashed it and now it almost works. I get an immediate reset during linux startup I have no Idea what might cause it. I've attached the serial output Thanks for any help! Thomas 2007/6/12, ben(a)hewson-venieri.co.uk <ben(a)hewson-venieri.co.uk>: > Can you try using just 1 memory module to start with and see if that helps. > > > > >Hi! > > > >I checked out r2717 and at first it behaved like Markus Boas Epia V > >but then I applied Ben's patch to the vt8231_early_serial.c and it > >booted into filo, once, then hanged at the dram setup. then I applied > >the vt8231_lpc.c patch and it hangs on this: > > > >LinuxBIOS-2.0.0.0Normal Mon Jun 11 22:28:57 CEST 2007 starting... > >87 is the comm register > >SMBus controller enabled > >vt8601 init starting > >00000000 is the north > > 1106 0601 > >0120d4 is the computed timing > > NOP > >PRECHARGE > >DUMMY READS > >CBR > >MRS > >NORMAL > >set ref. rate > >enable multi-page open > >Slot 00 is SDRAM 10000000 bytes > >000e is the MA type > >Slot 01 is SDRAM 08000000 bytes x2 > >000c is the MA type > >Slot 02 is empty > >Slot 03 is empty > >vt8601 done > >Copying LinuxBIOS to RAM. > >Jumping to LinuxBIOS. > >LinuxBIOS-2.0.0.0Normal Mon Jun 11 22:28:57 CEST 2007 booting... > >Enumerating buses... > >scan_static_bus for Root Device > >Finding PCI configuration type. > >PCI: Using configuration type 1 > >PCI_DOMAIN: 0000 enabled > >APIC_CLUSTER: 0 enabled > >PCI_DOMAIN: 0000 scanning... > >PCI: pci_scan_bus for bus 00 > >PCI: 00:00.0 [1106/0601] ops > >PCI: 00:00.0 [1106/0601] enabled > >malloc Enter, size 668, free_mem_ptr 00018000 > >malloc 0x00018000 > >Capability: 0x07 @ 0x80 > >Capability: 0x08 @ 0x80 > >Capability: 0x10 @ 0x80 > >PCI: 00:01.0 [1106/8601] enabled > >PCI: devfn 0x10, bad id 0xffffffff > >PCI: devfn 0x18, bad id 0xffffffff > >PCI: devfn 0x20, bad id 0xffffffff > >PCI: devfn 0x28, bad id 0xffffffff > >PCI: devfn 0x30, bad id 0xffffffff > >PCI: devfn 0x38, bad id 0xffffffff > >PCI: devfn 0x40, bad id 0xffffffff > >PCI: devfn 0x48, bad id 0xffffffff > >PCI: devfn 0x50, bad id 0xffffffff > >PCI: devfn 0x58, bad id 0xffffffff > >PCI: devfn 0x60, bad id 0xffffffff > >PCI: devfn 0x68, bad id 0xffffffff > >PCI: devfn 0x70, bad id 0xffffffff > >PCI: devfn 0x78, bad id 0xffffffff > >PCI: devfn 0x80, bad id 0xffffffff > >PCI: 00:11.0 [1106/8231] bus ops > >PCI: 00:11.0 [1106/8231] enabled > >PCI: 00:11.1 [1106/0571] ops > >PCI: 00:11.1 [1106/0571] enabled > >PCI: 00:11.2 [1106/3038] disabled > >PCI: 00:11.3 [1106/3038] disabled > >PCI: 00:11.4 [1106/8235] ops > >PCI: 00:11.4 [1106/8235] disabled > >PCI: 00:11.5 [1106/3058] disabled > >PCI: 00:11.6 [1106/3068] enabled > >PCI: devfn 0x8f, bad id 0xffffffff > >PCI: 00:12.0 [1106/3065] ops > >PCI: 00:12.0 [1106/3065] enabled > >PCI: devfn 0x98, bad id 0xffffffff > >malloc Enter, size 668, free_mem_ptr 0001829c > >malloc 0x0001829c > >PCI: 00:14.0 [1106/3065] ops > >PCI: 00:14.0 [1106/3065] enabled > >PCI: devfn 0xa8, bad id 0xffffffff > >PCI: devfn 0xb0, bad id 0xffffffff > >PCI: devfn 0xb8, bad id 0xffffffff > >PCI: devfn 0xc0, bad id 0xffffffff > >PCI: devfn 0xc8, bad id 0xffffffff > >PCI: devfn 0xd0, bad id 0xffffffff > >PCI: devfn 0xd8, bad id 0xffffffff > >PCI: devfn 0xe0, bad id 0xffffffff > >PCI: devfn 0xe8, bad id 0xffffffff > >PCI: devfn 0xf0, bad id 0xffffffff > >PCI: devfn 0xf8, bad id 0xffffffff > >do_pci_scan_bridge for PCI: 00:01.0 > >PCI: pci_scan_bus for bus 01 > >PCI: devfn 0x0, bad id 0xffffffff > >PCI: devfn 0x8, bad id 0xffffffff > >PCI: devfn 0x10, bad id 0xffffffff > >PCI: devfn 0x18, bad id 0xffffffff > >PCI: devfn 0x20, bad id 0xffffffff > >PCI: devfn 0x28, bad id 0xffffffff > >PCI: devfn 0x30, bad id 0xffffffff > >PCI: devfn 0x38, bad id 0xffffffff > >PCI: devfn 0x40, bad id 0xffffffff > >PCI: devfn 0x48, bad id 0xffffffff > >PCI: devfn 0x50, bad id 0xffffffff > >PCI: devfn 0x58, bad id 0xffffffff > >PCI: devfn 0x60, bad id 0xffffffff > >PCI: devfn 0x68, bad id 0xffffffff > >PCI: devfn 0x70, bad id 0xffffffff > >PCI: devfn 0x78, bad id 0xffffffff > >PCI: devfn 0x80, bad id 0xffffffff > >PCI: devfn 0x88, bad id 0xffffffff > >PCI: devfn 0x90, bad id 0xffffffff > >PCI: devfn 0x98, bad id 0xffffffff > >PCI: devfn 0xa0, bad id 0xffffffff > >PCI: devfn 0xa8, bad id 0xffffffff > >PCI: devfn 0xb0, bad id 0xffffffff > >PCI: devfn 0xb8, bad id 0xffffffff > >PCI: devfn 0xc0, bad id 0xffffffff > >PCI: devfn 0xc8, bad id 0xffffffff > >PCI: devfn 0xd0, bad id 0xffffffff > >PCI: devfn 0xd8, bad id 0xffffffff > >PCI: devfn 0xe0, bad id 0xffffffff > >PCI: devfn 0xe8, bad id 0xffffffff > >PCI: devfn 0xf0, bad id 0xffffffff > >PCI: devfn 0xf8, bad id 0xffffffff > >PCI: pci_scan_bus returning with max=001 > >do_pci_scan_bridge returns max 1 > >scan_static_bus for PCI: 00:11.0 > >malloc Enter, size 668, free_mem_ptr 00018538 > >malloc 0x00018538 > >malloc Enter, size 668, free_mem_ptr 000187d4 > >malloc 0x000187d4 > >malloc Enter, size 668, free_mem_ptr 00018a70 > >malloc 0x00018a70 > >malloc Enter, size 668, free_mem_ptr 00018d0c > >malloc 0x00018d0c > >malloc Enter, size 668, free_mem_ptr 00018fa8 > >malloc 0x00018fa8 > >malloc Enter, size 668, free_mem_ptr 00019244 > >malloc 0x00019244 > >malloc Enter, size 668, free_mem_ptr 000194e0 > >malloc 0x000194e0 > >malloc Enter, size 668, free_mem_ptr 0001977c > >malloc 0x0001977c > >malloc Enter, size 668, free_mem_ptr 00019a18 > >malloc 0x00019a18 > >malloc Enter, size 668, free_mem_ptr 00019cb4 > >malloc 0x00019cb4 > >malloc Enter, size 668, free_mem_ptr 00019f50 > >malloc 0x00019f50 > >PNP: 002e.0 disabled > >PNP: 002e.1 disabled > >PNP: 002e.2 enabled > >PNP: 002e.3 disabled > >PNP: 002e.5 enabled > >PNP: 002e.6 disabled > >PNP: 002e.7 disabled > >PNP: 002e.8 disabled > >PNP: 002e.9 disabled > >PNP: 002e.a disabled > >PNP: 002e.b enabled > >PNP: 607a.0 enabled > >PNP: 607a.1 enabled > >PNP: 607a.2 enabled > >PNP: 607a.3 enabled > >PNP: 607a.5 enabled > >PNP: 607a.6 enabled > >PNP: 607a.7 enabled > >PNP: 607a.8 enabled > >PNP: 607a.9 enabled > >PNP: 607a.a enabled > >PNP: 607a.b enabled > >scan_static_bus for PCI: 00:11.0 done > >PCI: pci_scan_bus returning with max=001 > >Unexpected Exception: 6 @ 10:e2c3f00a - Halting > >Code: 0 eflags: 00010093 > >eax: ffffff00 ebx: 00000000 ecx: 000003f8 edx: 00017eec > >edi: 00000000 esi: 00000000 ebp: 00000000 esp: 00010004 > > > > > >Any ideas would be great! > > > >Thanks! > >/Thomas > > > >-- > >linuxbios mailing list > >linuxbios(a)linuxbios.org > >http://www.linuxbios.org/mailman/listinfo/linuxbios >

7 16

[LinuxBIOS] r2721 - trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx
by svn＠openbios.org 14 Jun '07

14 Jun '07

Author: uwe Date: 2007-06-14 14:04:19 +0200 (Thu, 14 Jun 2007) New Revision: 2721 Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_lpc.c Log: Small bugfix in i82801xx_lpc.c. Signed-off-by: Corey Osgood <corey.osgood(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_lpc.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_lpc.c 2007-06-14 12:02:38 UTC (rev 2720) +++ trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_lpc.c 2007-06-14 12:04:19 UTC (rev 2721) @@ -89,8 +89,8 @@ uint8_t reg8; uint32_t reg32; int rtc_failed; - byte = pci_read_config8(dev, GEN_PMCON_3); - rtc_failed = byte & RTC_BATTERY_DEAD; + reg8 = pci_read_config8(dev, GEN_PMCON_3); + rtc_failed = reg8 & RTC_BATTERY_DEAD; if (rtc_failed) { reg8 &= ~(1 << 1); /* preserve the power fail state */ pci_write_config8(dev, GEN_PMCON_3, reg8);

1 0

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coreboot June 2007