coreboot June 2007

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[LinuxBIOS] r2717 build service
by LinuxBIOS information 08 Jun '07

08 Jun '07

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "uwe" checked in revision 2717 to the LinuxBIOS source repository and caused the following changes: Change Log: Minor tweaks in the 440BX RAM init code (trivial). Still hardcoded for Tyan S1846. This slightly increases performance, but it's still pretty horrible. Some RAM settings are causing a dramatically slow system (confirmed by comparing memtest performance results of the proprietary BIOS and our code). Haven't found the problem, yet. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of arima:hdama is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2717&device=hdama&vendor=… Configuration of artecgroup:dbe61 is still broken Compilation of ibm:e325 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2717&device=e325&vendor=i… Compilation of ibm:e326 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2717&device=e326&vendor=i… Compilation of iei:juki-511p is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2717&device=juki-511p&ven… Compilation of iwill:dk8s2 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2717&device=dk8s2&vendor=… Compilation of iwill:dk8x is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2717&device=dk8x&vendor=i… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, LinuxBIOS automatic build system

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[LinuxBIOS] r2717 - trunk/LinuxBIOSv2/src/northbridge/intel/i440bx
by svn＠openbios.org 08 Jun '07

08 Jun '07

Author: uwe Date: 2007-06-08 00:16:30 +0200 (Fri, 08 Jun 2007) New Revision: 2717 Modified: trunk/LinuxBIOSv2/src/northbridge/intel/i440bx/raminit.c Log: Minor tweaks in the 440BX RAM init code (trivial). Still hardcoded for Tyan S1846. This slightly increases performance, but it's still pretty horrible. Some RAM settings are causing a dramatically slow system (confirmed by comparing memtest performance results of the proprietary BIOS and our code). Haven't found the problem, yet. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/LinuxBIOSv2/src/northbridge/intel/i440bx/raminit.c =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/intel/i440bx/raminit.c 2007-06-07 20:52:42 UTC (rev 2716) +++ trunk/LinuxBIOSv2/src/northbridge/intel/i440bx/raminit.c 2007-06-07 22:16:30 UTC (rev 2717) @@ -129,7 +129,11 @@ * [01:00] Reserved */ // TODO - NBXCFG, 0x00000000, 0xff00a00c, + NBXCFG + 0, 0x00, 0x0c, + // NBXCFG + 1, 0x00, 0xa0, + NBXCFG + 1, 0x00, 0x80, + NBXCFG + 2, 0x00, 0x00, + NBXCFG + 3, 0x00, 0xff, /* DRAMC - DRAM Control Register * 0x57 @@ -154,7 +158,7 @@ * 111 = Reserved */ /* Choose SDRAM (not registered), and disable refresh for now. */ - DRAMC, 0x00, 0x8, + DRAMC, 0x00, 0x08, /* * PAM[6:0] - Programmable Attribute Map Registers @@ -240,7 +244,8 @@ * TODO */ // TODO - RPS, 0x0000, 0x0000, + RPS + 0, 0x00, 0x00, + RPS + 1, 0x00, 0x00, /* SDRAMC - SDRAM Control Register * 0x76 - 0x77 @@ -276,7 +281,8 @@ * 0 = 3 clocks of RAS# precharge * 1 = 2 clocks of RAS# precharge */ - SDRAMC, 0x0000, 0x0000, + SDRAMC + 0, 0x00, 0x00, + SDRAMC + 0, 0x00, 0x00, /* PGPOL - Paging Policy Register * 0x78 - 0x79 @@ -299,7 +305,8 @@ * 1xxx = Infinite (pages are not closed for idle condition) */ // TODO - PGPOL, 0x0000, 0xff00, + PGPOL + 0, 0x00, 0x00, + PGPOL + 1, 0x00, 0xff, /* PMCR - Power Management Control Register * 0x7a @@ -418,7 +425,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl) { int i, max; - uint32_t reg; + uint8_t reg; PRINT_DEBUG("Northbridge prior to SDRAM init:\r\n"); DUMPNORTH(); @@ -427,15 +434,15 @@ /* Set registers as specified in the register_values[] array. */ for (i = 0; i < max; i += 3) { - reg = pci_read_config32(ctrl->d0, register_values[i]); + reg = pci_read_config8(ctrl->d0, register_values[i]); reg &= register_values[i + 1]; reg |= register_values[i + 2] & ~(register_values[i + 1]); - pci_write_config32(ctrl->d0, register_values[i], reg); + pci_write_config8(ctrl->d0, register_values[i], reg); PRINT_DEBUG(" Set register 0x"); - PRINT_DEBUG_HEX32(register_values[i]); + PRINT_DEBUG_HEX8(register_values[i]); PRINT_DEBUG(" to 0x"); - PRINT_DEBUG_HEX32(reg); + PRINT_DEBUG_HEX8(reg); PRINT_DEBUG("\r\n"); } } @@ -480,23 +487,26 @@ pci_write_config16(ctrl->d0, RPS, 0x0001); /* TODO: Set SDRAMC. */ - // pci_write_config16(ctrl->d0, SDRAMC, 0x0000); + // pci_write_config16(ctrl->d0, SDRAMC, 0x010f); // FIXME? + pci_write_config16(ctrl->d0, SDRAMC, 0x0003); // FIXME? /* TODO: Set PGPOL. */ - pci_write_config16(ctrl->d0, PGPOL, 0x0107); + // pci_write_config16(ctrl->d0, PGPOL, 0x0107); + pci_write_config16(ctrl->d0, PGPOL, 0x0123); /* TODO: Set NBXCFG. */ - // pci_write_config32(ctrl->d0, NBXCFG, 0x0100220c); + // pci_write_config32(ctrl->d0, NBXCFG, 0x0100220c); // FIXME? + pci_write_config32(ctrl->d0, NBXCFG, 0xff00800c); /* TODO: Set PMCR? */ // pci_write_config8(ctrl->d0, PMCR, 0x14); - // pci_write_config8(ctrl->d0, PMCR, 0x10); + pci_write_config8(ctrl->d0, PMCR, 0x10); /* TODO? */ - // pci_write_config8(ctrl->d0, MLT, 0x40); - // pci_write_config8(ctrl->d0, DRAMT, 0x03); - // pci_write_config8(ctrl->d0, MBSC, 0x03); - // pci_write_config8(ctrl->d0, SCRR, 0x38); + pci_write_config8(ctrl->d0, MLT, 0x40); + pci_write_config8(ctrl->d0, DRAMT, 0x03); + pci_write_config8(ctrl->d0, MBSC, 0x03); + pci_write_config8(ctrl->d0, SCRR, 0x38); } /**

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[LinuxBIOS] r2716 build service
by LinuxBIOS information 07 Jun '07

07 Jun '07

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "uwe" checked in revision 2716 to the LinuxBIOS source repository and caused the following changes: Change Log: Add support for the IEI JUKI-511P and IEI ROCKY-512 half-size boards. Both are very similar, thus both use the JUKI-511P target. Linux with patches from Juergen Beisert (http://www.linuxbios.org/pipermail/linuxbios/2007-May/020932.html) boots and work fine (ide, usb, ethernet, serial, keyboard and sound work normally). Problems: - Filo loads a bzImage only from ide0 (ide1 doesn't work yet). - Video doesn't work, yet. Signed-off-by: Nikolay Petukhov <nikolay.petukhov(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of arima:hdama is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2716&device=hdama&vendor=… Configuration of artecgroup:dbe61 is still broken Compilation of ibm:e325 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2716&device=e325&vendor=i… Compilation of ibm:e326 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2716&device=e326&vendor=i… Compilation of iei:juki-511p is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2716&device=juki-511p&ven… Compilation of iwill:dk8s2 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2716&device=dk8s2&vendor=… Compilation of iwill:dk8x is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2716&device=dk8x&vendor=i… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, LinuxBIOS automatic build system

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[LinuxBIOS] r2716 - in trunk/LinuxBIOSv2: src/mainboard/iei src/mainboard/iei/juki-511p targets/iei targets/iei/juki-511p
by svn＠openbios.org 07 Jun '07

07 Jun '07

Author: uwe Date: 2007-06-07 22:52:42 +0200 (Thu, 07 Jun 2007) New Revision: 2716 Added: trunk/LinuxBIOSv2/src/mainboard/iei/juki-511p/ trunk/LinuxBIOSv2/src/mainboard/iei/juki-511p/Config.lb trunk/LinuxBIOSv2/src/mainboard/iei/juki-511p/Options.lb trunk/LinuxBIOSv2/src/mainboard/iei/juki-511p/auto.c trunk/LinuxBIOSv2/src/mainboard/iei/juki-511p/chip.h trunk/LinuxBIOSv2/src/mainboard/iei/juki-511p/cmos.layout trunk/LinuxBIOSv2/src/mainboard/iei/juki-511p/failover.c trunk/LinuxBIOSv2/src/mainboard/iei/juki-511p/irq_tables.c trunk/LinuxBIOSv2/src/mainboard/iei/juki-511p/mainboard.c trunk/LinuxBIOSv2/targets/iei/juki-511p/ trunk/LinuxBIOSv2/targets/iei/juki-511p/Config.lb Log: Add support for the IEI JUKI-511P and IEI ROCKY-512 half-size boards. Both are very similar, thus both use the JUKI-511P target. Linux with patches from Juergen Beisert (http://www.linuxbios.org/pipermail/linuxbios/2007-May/020932.html) boots and work fine (ide, usb, ethernet, serial, keyboard and sound work normally). Problems: - Filo loads a bzImage only from ide0 (ide1 doesn't work yet). - Video doesn't work, yet. Signed-off-by: Nikolay Petukhov <nikolay.petukhov(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Added: trunk/LinuxBIOSv2/src/mainboard/iei/juki-511p/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/iei/juki-511p/Config.lb (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/iei/juki-511p/Config.lb 2007-06-07 20:52:42 UTC (rev 2716) @@ -0,0 +1,167 @@ +## +## Compute the location and size of where this firmware image +## (linuxBIOS plus bootloader) will live in the boot rom chip. +## +default ROM_SIZE = 256 * 1024 +default ROM_SECTION_SIZE = ROM_SIZE +default ROM_SECTION_OFFSET = 0 + +## +## Compute the start location and size size of +## The linuxBIOS bootloader. +## +default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) + +## +## Compute where this copy of linuxBIOS will start in the boot rom +## +default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) + +## +## Compute a range of ROM that can cached to speed up linuxBIOS, +## execution speed. +## +## XIP_ROM_SIZE must be a power of 2. +## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE +## +default XIP_ROM_SIZE=65536 +default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) + +## +## Set all of the defaults for an x86 architecture +## + +arch i386 end + +## +## Build the objects we have code for in this directory. +## + +driver mainboard.o + +if HAVE_PIRQ_TABLE object irq_tables.o end +#object reset.o + +## +## Romcc output +## +makerule ./failover.E + depends "$(MAINBOARD)/failover.c ./romcc" + action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" +end + +makerule ./failover.inc + depends "$(MAINBOARD)/failover.c ./romcc" + action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" +end + +makerule ./auto.E + depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + action "./romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end +makerule ./auto.inc + depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + action "./romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end + +## +## Build our 16 bit and 32 bit linuxBIOS entry code +## +mainboardinit cpu/x86/16bit/entry16.inc +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/16bit/entry16.lds +ldscript /cpu/x86/32bit/entry32.lds + +## +## Build our reset vector (This is where linuxBIOS is entered) +## +mainboardinit cpu/x86/16bit/reset16.inc +ldscript /cpu/x86/16bit/reset16.lds + +### Should this be in the northbridge code? +mainboardinit arch/i386/lib/cpu_reset.inc + +## +## Include an id string (For safe flashing) +## +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds + +### +### O.k. We aren't just an intermediary anymore! +### + +## +## Setup RAM +## +mainboardinit cpu/x86/fpu/enable_fpu.inc +mainboardinit cpu/amd/model_gx1/cpu_setup.inc +mainboardinit cpu/amd/model_gx1/gx_setup.inc +mainboardinit ./auto.inc + +## +## Include the secondary Configuration files +## +#dir /pc80 +#config chip.h + +chip northbridge/amd/gx1 + device pci_domain 0 on + device pci 0.0 on end + chip southbridge/amd/cs5530 + + device pci 12.0 on + chip superio/winbond/w83977f + device pnp 3f0.0 on # FDC + irq 0x70 = 6 + end + device pnp 3f0.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 3f0.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + register "com1" = "{115200}" + device pnp 3f0.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + register "com2" = "{115200}" + device pnp 3f0.4 on # RTC + io 0x60 = 0x070 + irq 0x70 = 8 + end + device pnp 3f0.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # Int 1 for PS/2 keyboard + irq 0x72 = 12 # Int 12 for PS/2 mouse + end + device pnp 3f0.6 off # IR + end + device pnp 3f0.7 off # GPIO1 + end + device pnp 3f0.8 off # GPIO + end + end + device pci 12.1 on end # SMI + device pci 12.2 on end # IDE + device pci 12.3 on end # Audio + device pci 12.4 on end # VGA onboard + + end + + device pci 0e.0 on end # ETH0 + device pci 13.0 on end # USB + + end + end + + chip cpu/amd/model_gx1 + end + +end + Added: trunk/LinuxBIOSv2/src/mainboard/iei/juki-511p/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/iei/juki-511p/Options.lb (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/iei/juki-511p/Options.lb 2007-06-07 20:52:42 UTC (rev 2716) @@ -0,0 +1,147 @@ +uses HAVE_MP_TABLE +uses HAVE_PIRQ_TABLE +uses USE_FALLBACK_IMAGE +uses HAVE_FALLBACK_BOOT +uses HAVE_HARD_RESET +uses CONFIG_UDELAY_IO +uses HAVE_OPTION_TABLE +uses USE_OPTION_TABLE +uses CONFIG_COMPRESS +uses CONFIG_COMPRESSED_PAYLOAD_NRV2B +uses CONFIG_COMPRESSED_PAYLOAD_LZMA +uses CONFIG_PRECOMPRESSED_PAYLOAD +uses CONFIG_ROM_PAYLOAD +uses IRQ_SLOT_COUNT +uses MAINBOARD +uses MAINBOARD_VENDOR +uses MAINBOARD_PART_NUMBER +uses LINUXBIOS_EXTRA_VERSION +uses ARCH +uses FALLBACK_SIZE +uses STACK_SIZE +uses HEAP_SIZE +uses ROM_SIZE +uses ROM_SECTION_SIZE +uses ROM_IMAGE_SIZE +uses ROM_SECTION_SIZE +uses ROM_SECTION_OFFSET +uses CONFIG_ROM_PAYLOAD_START +uses PAYLOAD_SIZE +uses _ROMBASE +uses _RAMBASE +uses XIP_ROM_SIZE +uses XIP_ROM_BASE +uses HAVE_MP_TABLE +uses CROSS_COMPILE +uses CC +uses HOSTCC + +uses OBJCOPY + +uses CONFIG_CONSOLE_SERIAL8250 +uses DEFAULT_CONSOLE_LOGLEVEL +uses MAXIMUM_CONSOLE_LOGLEVEL + +uses TTYS0_BAUD +uses TTYS0_BASE +uses TTYS0_LCS + + +## ROM_SIZE is the size of boot ROM that this board will use. +default ROM_SIZE = 256*1024 + +### +### Build options +### + +## +## Build code for the fallback boot +## +default HAVE_FALLBACK_BOOT=1 + +## +## no MP table +## +default HAVE_MP_TABLE=0 + +## +## Build code to reset the motherboard from linuxBIOS +## +default HAVE_HARD_RESET=0 + +default CONFIG_UDELAY_IO=1 +## +## Build code to export a programmable irq routing table +## +default HAVE_PIRQ_TABLE=0 +default IRQ_SLOT_COUNT=2 +#object irq_tables.o + +## +## Build code to export a CMOS option table +## +default HAVE_OPTION_TABLE=0 + +### +### LinuxBIOS layout values +### + +## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +default ROM_IMAGE_SIZE = 65536 +default FALLBACK_SIZE = 131072 + +## +## Use a small 8K stack +## +default STACK_SIZE=0x2000 + +## +## Use a small 16K heap +## +default HEAP_SIZE=0x4000 + +## +## Only use the option table in a normal image +## +#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default USE_OPTION_TABLE = 0 + +default _RAMBASE = 0x00004000 + +default CONFIG_ROM_PAYLOAD = 1 + +## +## The Serial Console +## + +# To Enable the Serial Console +default CONFIG_CONSOLE_SERIAL8250=1 +default DEFAULT_CONSOLE_LOGLEVEL=8 +default MAXIMUM_CONSOLE_LOGLEVEL=8 + +## Select the serial console baud rate +default TTYS0_BAUD=115200 +#default TTYS0_BAUD=57600 +#default TTYS0_BAUD=38400 +#default TTYS0_BAUD=19200 +#default TTYS0_BAUD=9600 +#default TTYS0_BAUD=4800 +#default TTYS0_BAUD=2400 +#default TTYS0_BAUD=1200 + +# Select the serial console base port +default TTYS0_BASE=0x3f8 + +# Select the serial protocol +# This defaults to 8 data bits, 1 stop bit, and no parity +default TTYS0_LCS=0x3 + +## +## The default compiler +## +default CROSS_COMPILE="" +default CC="$(CROSS_COMPILE)gcc -m32" +default HOSTCC="gcc" + +end + Added: trunk/LinuxBIOSv2/src/mainboard/iei/juki-511p/auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/iei/juki-511p/auto.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/iei/juki-511p/auto.c 2007-06-07 20:52:42 UTC (rev 2716) @@ -0,0 +1,59 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define ASSEMBLY 1 + +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <arch/hlt.h> +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" +#include "superio/winbond/w83977f/w83977f_early_serial.c" +#include "cpu/x86/bist.h" +#include "pc80/udelay_io.c" + +#define SERIAL_DEV PNP_DEV(0x3f0, W83977F_SP1) + +#include "northbridge/amd/gx1/raminit.c" + +static void main(unsigned long bist) +{ + /* Initialize the serial console. */ + w83977f_enable_serial(SERIAL_DEV, TTYS0_BASE); + uart_init(); + console_init(); + + /* Halt if there was a built in self test failure. */ + report_bist_failure(bist); + + /* Disable Watchdog Timer. */ + inb(0x043); + inb(0x843); + + /* Initialize RAM. */ + sdram_init(); + + /* Check RAM. */ + /* ram_check(0x00000000, 640 * 1024); */ +} Added: trunk/LinuxBIOSv2/src/mainboard/iei/juki-511p/chip.h =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/iei/juki-511p/chip.h (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/iei/juki-511p/chip.h 2007-06-07 20:52:42 UTC (rev 2716) @@ -0,0 +1,25 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_iei_juki_511p_ops; + +struct mainboard_iei_juki_511p_config { + int nothing; +}; Added: trunk/LinuxBIOSv2/src/mainboard/iei/juki-511p/cmos.layout =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/iei/juki-511p/cmos.layout (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/iei/juki-511p/cmos.layout 2007-06-07 20:52:42 UTC (rev 2716) @@ -0,0 +1,73 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +1008 16 h 0 check_sum + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM + +checksums + +checksum 392 1007 1008 + Added: trunk/LinuxBIOSv2/src/mainboard/iei/juki-511p/failover.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/iei/juki-511p/failover.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/iei/juki-511p/failover.c 2007-06-07 20:52:42 UTC (rev 2716) @@ -0,0 +1,53 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define ASSEMBLY 1 + +#include <stdint.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include "arch/romcc_io.h" +#include "pc80/mc146818rtc_early.c" + +static unsigned long main(unsigned long bist) +{ + /* This is the primary cpu how should I boot? */ + if (do_normal_boot()) { + goto normal_image; + } + else { + goto fallback_image; + } +normal_image: + asm volatile ("jmp __normal_image" + : /* outputs */ + : "a" (bist) /* inputs */ + : /* clobbers */ + ); +cpu_reset: + asm volatile ("jmp __cpu_reset" + : /* outputs */ + : "a"(bist) /* inputs */ + : /* clobbers */ + ); +fallback_image: + return bist; +} Added: trunk/LinuxBIOSv2/src/mainboard/iei/juki-511p/irq_tables.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/iei/juki-511p/irq_tables.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/iei/juki-511p/irq_tables.c 2007-06-07 20:52:42 UTC (rev 2716) @@ -0,0 +1,103 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> + +#define IRQ_BITMAP_LINK0 0x0800 /* chipset's INTA# input should be routed to IRQ11 */ +#define IRQ_BITMAP_LINK1 0x0400 /* chipset's INTB# input should be routed to IRQ10 */ +#define IRQ_BITMAP_LINK2 0x0000 /* chipset's INTC# input should be routed to nothing (disabled) */ +#define IRQ_BITMAP_LINK3 0x0000 /* chipset's INTD# input should be routed to nothing (disabled) */ + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32+16*2, /* There can be a total of 2 devices on the bus */ + 0x00, /* Where the interrupt router lies (bus) */ + (0x12<<3)|0x0, /* Where the interrupt router lies (dev) */ + 0xc00, /* IRQs devoted exclusively to PCI usage */ + 0x1078, /* Vendor */ + 0x2, /* Device */ + 0, /* Crap (miniport) */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0x57, /* u8 checksum. This has to be set to some + value that would give 0 after the sum of all + bytes for this structure (including checksum) */ + + .slots = { + [0] = { + .slot = 0x0, /* should be 0 when it is no real slot. My device is soldered */ + .bus = 0x00, + .devfn = (0x13<<3)|0x0, /* 0x13 is my USB OHCI */ + .irq = { + [0] = { /* <-- 0 means this is INTA# output from the device or slot */ + .link = 0x01, /* 0x01 means its connected to INTA# input at chipset */ + .bitmap = IRQ_BITMAP_LINK0 + }, + [1] = { /* <-- 1 means this is INTB# output from the device or slot */ + .link = 0x02, /* 0x02 means its connected to INTB# input at chipset */ + .bitmap = IRQ_BITMAP_LINK1 + }, + [2] = { /* <-- 2 means this is INTC# output from the device or slot */ + .link = 0x03, /* 0x03 means its connected to INTC# input at chipset */ + .bitmap = IRQ_BITMAP_LINK2 + }, + [3] = { /* <-- 3 means this is INTD# output from the device or slot */ + .link = 0x04, /* 0x04 means its connected to INTD# input at chipset */ + .bitmap = IRQ_BITMAP_LINK3 + } + } + }, + + [1] = { + .slot = 0x0, /* means also "on board" */ + .bus = 0x00, + .devfn = (0x0e<<3)|0x0, /* 0x0e is my Realtek Network device */ + .irq = { + [0] = { /* <-- 0 means this is INTA# output from the device or slot */ + .link = 0x02, /* 0x02 means its connected to INTB# input at chipset */ + .bitmap = IRQ_BITMAP_LINK1 + }, + [1] = { /* <-- 1 means this is INTB# output from the device or slot */ + .link = 0x03, /* 0x03 means its connected to INTC# input at chipset */ + .bitmap = IRQ_BITMAP_LINK2 + }, + [2] = { /* <-- 2 means this is INTC# output from the device or slot */ + .link = 0x04, /* 0x04 means its connected to INTD# input at chipset */ + .bitmap = IRQ_BITMAP_LINK3 + }, + [3] = { /* <-- 3 means this is INTD# output from the device or slot */ + .link = 0x01, /* 0x01 means its connected to INTA# input at chipset */ + .bitmap = IRQ_BITMAP_LINK0 + } + } + } + } +}; + +/** + * Copy the IRQ routing table to memory. + * + * @param addr Destination address (between 0xF0000...0x100000). + * @return The end address of the pirq routing table in memory. + */ +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} Added: trunk/LinuxBIOSv2/src/mainboard/iei/juki-511p/mainboard.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/iei/juki-511p/mainboard.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/iei/juki-511p/mainboard.c 2007-06-07 20:52:42 UTC (rev 2716) @@ -0,0 +1,31 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <arch/io.h> +#include "chip.h" + +struct chip_operations mainboard_iei_juki_511p_ops = { + CHIP_NAME("IEI JUKI-511P Mainboard") +}; Added: trunk/LinuxBIOSv2/targets/iei/juki-511p/Config.lb =================================================================== --- trunk/LinuxBIOSv2/targets/iei/juki-511p/Config.lb (rev 0) +++ trunk/LinuxBIOSv2/targets/iei/juki-511p/Config.lb 2007-06-07 20:52:42 UTC (rev 2716) @@ -0,0 +1,37 @@ +## +## This file is part of the LinuxBIOS project. +## +## Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov(a)gmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +target juki-511p +mainboard iei/juki-511p + +option ROM_SIZE=256*1024 + +option HAVE_PIRQ_TABLE=1 + +option CONFIG_COMPRESS=0 +option CONFIG_PRECOMPRESSED_PAYLOAD=0 + +romimage "image" + option ROM_IMAGE_SIZE=64*1024 + option LINUXBIOS_EXTRA_VERSION="-filo" + payload ../../filo.elf +end + +buildrom ./linuxbios.rom ROM_SIZE "image"

1 0

[LinuxBIOS] r349 - LinuxBIOSv3/include
by svn＠openbios.org 07 Jun '07

07 Jun '07

Author: rminnich Date: 2007-06-07 19:34:17 +0200 (Thu, 07 Jun 2007) New Revision: 349 Modified: LinuxBIOSv3/include/lib.h Log: prototypes for dram and smbus functions. We are experimenting a bit here; we are going to put all protos for lib/*.c into this file. Experience has shown this will not be a large or messy set of protos. Plan 9 has used this technique and it works well, as it avoids 100 files with one prototype per file. If you can't trust Ken Thompson, who can you trust? Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: LinuxBIOSv3/include/lib.h =================================================================== --- LinuxBIOSv3/include/lib.h 2007-06-07 00:07:39 UTC (rev 348) +++ LinuxBIOSv3/include/lib.h 2007-06-07 17:34:17 UTC (rev 349) @@ -30,4 +30,11 @@ void beep_short(void); void beep_long(void); +/* smbus functions */ +int smbus_read_byte(unsigned device, unsigned address); + +/* dram functions */ +void ram_failure(const char *why); +void ram_initialize(int controllers, void *ctrl); + #endif /* LIB_H */

1 0

[LinuxBIOS] Added mainboard commell/lv671 and compile works, but ...
by Dieter Bloms 07 Jun '07

07 Jun '07

Hi, I added my new board to mainboards and successfully compile with northbridge i855pm and i82801dbm southbridge. After flashing and reboot I get beep beep beep 2 times per second. And there is nothing to see on serial output. I know, that the i855pm is not fully supported and I'm waiting for the patches from Joe, but I thought the serial console may work without it. Maybe someone is willing to check my config so far. The most stuff is stolen from digitallogic/adl855pc directory. It would be nice to get the serial console to work in the first step, so I can see what is wrong with the other stuff. I've uploaded a tar.gz to: http://www.bloms.de/download/commel_lv671.tar.gz It is only 9K big ;) Thank you for your help. -- Gruß Dieter -- I do not get viruses because I do not use MS software. If you use Outlook then please do not put my email address in your address-book so that WHEN you get a virus it won't use my address in the From field.

7 25

[LinuxBIOS] r348 - in LinuxBIOSv3: device southbridge/amd/cs5536 util/x86emu/pcbios
by svn＠openbios.org 07 Jun '07

07 Jun '07

Author: uwe Date: 2007-06-07 02:07:39 +0200 (Thu, 07 Jun 2007) New Revision: 348 Modified: LinuxBIOSv3/device/device.c LinuxBIOSv3/device/pci_device.c LinuxBIOSv3/southbridge/amd/cs5536/smbus_initram.c LinuxBIOSv3/util/x86emu/pcbios/pcibios.h Log: Fix various Doxygen warnings (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: LinuxBIOSv3/device/device.c =================================================================== --- LinuxBIOSv3/device/device.c 2007-06-06 23:43:11 UTC (rev 347) +++ LinuxBIOSv3/device/device.c 2007-06-07 00:07:39 UTC (rev 348) @@ -166,6 +166,7 @@ * * @param parent Parent bus the newly created device is attached to. * @param path Path to the device to be created. + * @param devid TODO * @return Pointer to the newly created device structure. * @see device_path */ @@ -739,7 +740,7 @@ * bridges. If the setting up and tuning of the bus causes a reset to be * required, reset the bus and scan it again. * - * @param bus Pointer to the bus device. + * @param busdevice Pointer to the bus device. * @param max Current bus number. * @return The maximum bus number found, after scanning all subordinate buses. */ Modified: LinuxBIOSv3/device/pci_device.c =================================================================== --- LinuxBIOSv3/device/pci_device.c 2007-06-06 23:43:11 UTC (rev 347) +++ LinuxBIOSv3/device/pci_device.c 2007-06-07 00:07:39 UTC (rev 348) @@ -150,7 +150,6 @@ * Given a device and register, read the size of the BAR for that register. * * @param dev Pointer to the device structure. - * @param resource Pointer to the resource structure. * @param index Address of the PCI configuration register. */ struct resource *pci_get_resource(struct device *dev, unsigned long index) Modified: LinuxBIOSv3/southbridge/amd/cs5536/smbus_initram.c =================================================================== --- LinuxBIOSv3/southbridge/amd/cs5536/smbus_initram.c 2007-06-06 23:43:11 UTC (rev 347) +++ LinuxBIOSv3/southbridge/amd/cs5536/smbus_initram.c 2007-06-07 00:07:39 UTC (rev 348) @@ -249,7 +249,7 @@ * * @param smbus_io_base The SMBus I/O base. * @param device The device. - * @param command The command. + * @param address The address. * @return The data from the SMBus packet area. */ static u8 do_smbus_read_byte(u16 smbus_io_base, u8 device, u8 address) @@ -315,7 +315,7 @@ * one thing -- calling this function to read DRAM parameters. * * @param device The device. - * @param command The command. + * @param address The address. * @return The data from the SMBus packet area or an error of 0xff (i.e. -1). */ int smbus_read_byte(u16 device, u8 address) Modified: LinuxBIOSv3/util/x86emu/pcbios/pcibios.h =================================================================== --- LinuxBIOSv3/util/x86emu/pcbios/pcibios.h 2007-06-06 23:43:11 UTC (rev 347) +++ LinuxBIOSv3/util/x86emu/pcbios/pcibios.h 2007-06-07 00:07:39 UTC (rev 348) @@ -34,7 +34,9 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */#ifndef PCI_BIOS_H + */ + +#ifndef PCI_BIOS_H #define PCI_BIOS_H enum {

1 0

[LinuxBIOS] r2715 build service
by LinuxBIOS information 07 Jun '07

07 Jun '07

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "uwe" checked in revision 2715 to the LinuxBIOS source repository and caused the following changes: Change Log: Fix up and document the AMD CS5530/CS5530A support in flashrom. The previous code was pretty unreadable, undocumented and did some totally unrelated things (such as mucking with the game port or port 0x92). This version is tested with a 256 KB chip and should work for the CS5530 and CS5530A. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of arima:hdama is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2715&device=hdama&vendor=… Configuration of artecgroup:dbe61 is still broken Compilation of ibm:e325 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2715&device=e325&vendor=i… Compilation of ibm:e326 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2715&device=e326&vendor=i… Compilation of iwill:dk8s2 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2715&device=dk8s2&vendor=… Compilation of iwill:dk8x is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2715&device=dk8x&vendor=i… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, LinuxBIOS automatic build system

1 0

[LinuxBIOS] r347 - LinuxBIOSv3/southbridge/amd/cs5536
by svn＠openbios.org 07 Jun '07

07 Jun '07

Author: uwe Date: 2007-06-07 01:43:11 +0200 (Thu, 07 Jun 2007) New Revision: 347 Modified: LinuxBIOSv3/southbridge/amd/cs5536/cs5536_early_setup.c Log: Various cosmetic fixes (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: LinuxBIOSv3/southbridge/amd/cs5536/cs5536_early_setup.c =================================================================== --- LinuxBIOSv3/southbridge/amd/cs5536/cs5536_early_setup.c 2007-06-05 21:01:05 UTC (rev 346) +++ LinuxBIOSv3/southbridge/amd/cs5536/cs5536_early_setup.c 2007-06-06 23:43:11 UTC (rev 347) @@ -1,71 +1,75 @@ /* -* This file is part of the LinuxBIOS project. -* -* Copyright (C) 2007 Advanced Micro Devices -* -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License version 2 as -* published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License -* along with this program; if not, write to the Free Software -* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #include <console.h> #include <io.h> #include <msr.h> #include <amd_geodelx.h> #include "cs5536.h" + /* - * cs5536_early_setup.c:Early chipset initialization for CS5536 companion device - * This code is needed for setting up ram, since we need SMBUS working as - * well as serial port. - * This file implements the initialization sequence documented in section 4.2 of - * AMD Geode GX Processor CS5536 Companion Device GoedeROM Porting Guide. + * Early chipset initialization for the AMD CS5536 Companion Device. + * + * This code is needed for setting up RAM, since we need SMBus working as + * well as a serial port. + * + * This file implements the initialization sequence documented in section 4.2 + * of AMD Geode GX Processor CS5536 Companion Device GoedeROM Porting Guide. */ /** - * @brief Set up GLINK routing for this part. The routing is controlled by an MSR. - * This appears to be the - * same on all boards. - * If you don't know what GLINK routing is, there is no way to explain it here. + * Set up GLINK routing for this part. + * + * The routing is controlled by an MSR. This appears to be the same on + * all boards. */ void cs5536_setup_extmsr(void) { msr_t msr; - /* forward MSR access to CS5536_GLINK_PORT_NUM to CS5536_DEV_NUM */ + /* Forward MSR access to CS5536_GLINK_PORT_NUM to CS5536_DEV_NUM. */ msr.hi = msr.lo = 0x00000000; -#if CS5536_GLINK_PORT_NUM <= 4 + +#if CS5536_GLINK_PORT_NUM <= 4 msr.lo = CS5536_DEV_NUM << - (unsigned char)((CS5536_GLINK_PORT_NUM - 1) * 8); + (unsigned char)((CS5536_GLINK_PORT_NUM - 1) * 8); #else msr.hi = CS5536_DEV_NUM << - (unsigned char)((CS5536_GLINK_PORT_NUM - 5) * 8); + (unsigned char)((CS5536_GLINK_PORT_NUM - 5) * 8); #endif + wrmsr(GLPCI_ExtMSR, msr); } /** - * @brief Setup PCI IDSEL for CS5536. There is a Magic Register that must be + * Setup PCI IDSEL for CS5536. There is a Magic Register that must be * written so that the chip appears at the expected place in the PCI tree. */ void cs5536_setup_idsel(void) { - /* write IDSEL to the write once register at address 0x0000 */ + /* Write IDSEL to the write once register at address 0x0000. */ outl(0x1 << (CS5536_DEV_NUM + 10), 0); } /** - * @brief Magic Bits for undocumented register. - * You don' t need to see those papers. - * These are not the bits you're looking for. - * You can go about your business. + * Magic Bits for undocumented register. You don't need to see those papers. + * These are not the bits you're looking for. You can go about your business. * Move along, move along. */ void cs5536_usb_swapsif(void) @@ -73,57 +77,61 @@ msr_t msr; msr = rdmsr(USB1_SB_GLD_MSR_CAP + 0x5); - //USB Serial short detect bit. + + /* USB Serial short detect bit. */ if (msr.hi & 0x10) { /* We need to preserve bits 32,33,35 and not clear any BIST - * error, but clear the SERSHRT error bit */ - + * error, but clear the SERSHRT error bit. + */ msr.hi &= 0xFFFFFFFB; wrmsr(USB1_SB_GLD_MSR_CAP + 0x5, msr); } } /** - * @brief Set up IO bases for SMBUS, GPIO, MFGPT, ACPI, and PM. - * These can be changed by Linux later. We set some initial value so - * that the resources are there as needed. - * The values are hardcoded because, this early in the process, fancy - * allocation can do more harm than good. + * Set up I/O bases for SMBus, GPIO, MFGPT, ACPI, and PM. + * + * These can be changed by Linux later. We set some initial value so that + * the resources are there as needed. The values are hardcoded because, + * this early in the process, fancy allocation can do more harm than good. */ void cs5536_setup_iobase(void) { msr_t msr; - /* setup LBAR for SMBus controller */ + + /* Setup LBAR for SMBus controller. */ msr.hi = 0x0000f001; msr.lo = SMBUS_IO_BASE; wrmsr(MDD_LBAR_SMB, msr); - /* setup LBAR for GPIO */ + /* Setup LBAR for GPIO. */ msr.hi = 0x0000f001; msr.lo = GPIO_IO_BASE; wrmsr(MDD_LBAR_GPIO, msr); - /* setup LBAR for MFGPT */ + /* Setup LBAR for MFGPT. */ msr.hi = 0x0000f001; msr.lo = MFGPT_IO_BASE; wrmsr(MDD_LBAR_MFGPT, msr); - /* setup LBAR for ACPI */ + /* Setup LBAR for ACPI. */ msr.hi = 0x0000f001; msr.lo = ACPI_IO_BASE; wrmsr(MDD_LBAR_ACPI, msr); - /* setup LBAR for PM Support */ + /* Setup LBAR for PM support. */ msr.hi = 0x0000f001; msr.lo = PMS_IO_BASE; wrmsr(MDD_LBAR_PMS, msr); } /** - * @brief Power Button Setup - * setup GPIO24, it is the external signal for 5536 vsb_work_aux - * which controls all voltage rails except Vstandby & Vmem. - * We need to enable, OUT_AUX1 and OUTPUT_ENABLE in this order. + * Power Button Setup. + * + * Setup GPIO24, it is the external signal for CS5536 vsb_work_aux which + * controls all voltage rails except Vstandby & Vmem. We need to enable, + * OUT_AUX1 and OUTPUT_ENABLE in this order. + * * If GPIO24 is not enabled then soft-off will not work. */ void cs5536_setup_power_button(void) @@ -131,39 +139,45 @@ outl(0x40020000, PMS_IO_BASE + 0x40); outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUT_AUX1_SELECT); outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE); - } /** - * @brief Set the various GPIOs. An unknown question at this point is - * how general this is to all mainboards. At the same time, many - * boards seem to follow this particular reference spec. + * Set the various GPIOs. + * + * An unknown question at this point is how general this is to all mainboards. + * At the same time, many boards seem to follow this particular reference spec. */ void cs5536_setup_smbus_gpio(void) { u32 val; - /* setup GPIO pins 14/15 for SDA/SCL */ + /* Setup GPIO pins 14/15 for SDA/SCL. */ val = GPIOL_15_SET | GPIOL_14_SET; + /* Output Enable */ outl(val, GPIO_IO_BASE + GPIOL_OUT_AUX1_SELECT); + /* Output AUX1 */ outl(val, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE); + /* Input Enable */ outl(val, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT); + /* Input AUX1 */ outl(val, GPIO_IO_BASE + GPIOL_INPUT_ENABLE); } /** - * @brief Disable the internal UART. + * Disable the internal UART. + * * Different boards have different UARTs for COM1. */ void cs5536_disable_internal_uart(void) { msr_t msr; + /* The UARTs default to enabled. - * Disable and reset them and configure them later. (SIO init) + * Disable and reset them and configure them later (SIO init). */ msr = rdmsr(MDD_UART1_CONF); msr.lo = 1; // reset @@ -179,15 +193,17 @@ } /** - * @brief Set up the cs5536 CIS interface to CPU interface to match modes. - * The CIS is related to the interrupt system. It is important to match the - * south and the cpu chips. At the same time, they always seem to use mode B. + * Set up the CS5536 CIS interface to CPU interface to match modes. + * + * The CIS is related to the interrupt system. It is important to match + * the southbridge and the CPU chips. At the same time, they always seem + * to use mode B. */ void cs5536_setup_cis_mode(void) { msr_t msr; - /* setup CPU interface serial to mode B to match CPU */ + /* Setup CPU interface serial to mode B to match CPU. */ msr = rdmsr(GLPCI_SB_CTRL); msr.lo &= ~0x18; msr.lo |= 0x10; @@ -195,92 +211,89 @@ } /** - * @brief Enable the on chip UART.see page 412 of the cs5536 companion book + * Enable the on chip UART. + * + * See page 412 of the AMD Geode CS5536 Companion Device data book. */ void cs5536_setup_onchipuart(void) { msr_t msr; /* Setup early for polling only mode. - * 1. Eanble GPIO 8 to OUT_AUX1, 9 to IN_AUX1 + * 1. Eanble GPIO 8 to OUT_AUX1, 9 to IN_AUX1. * GPIO LBAR + 0x04, LBAR + 0x10, LBAR + 0x20, LBAR + 34 - * 2. Enable UART IO space in MDD + * 2. Enable UART I/O space in MDD. * MSR 0x51400014 bit 18:16 - * 3. Enable UART controller + * 3. Enable UART controller. * MSR 0x5140003A bit 0, 1 */ /* GPIO8 - UART1_TX */ - /* Set: Output Enable (0x4) */ + /* Set: Output Enable (0x4) */ outl(GPIOL_8_SET, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE); /* Set: OUTAUX1 Select (0x10) */ outl(GPIOL_8_SET, GPIO_IO_BASE + GPIOL_OUT_AUX1_SELECT); + /* GPIO9 - UART1_RX */ - /* Set: Input Enable (0x20) */ + /* Set: Input Enable (0x20) */ outl(GPIOL_9_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE); - /* Set: INAUX1 Select (0x34) */ + /* Set: INAUX1 Select (0x34) */ outl(GPIOL_9_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT); - /* set address to 3F8 */ + /* Set address to 0x3F8. */ msr = rdmsr(MDD_LEG_IO); msr.lo |= 0x7 << 16; wrmsr(MDD_LEG_IO, msr); - /* Bit 1 = DEVEN (device enable) - * Bit 4 = EN_BANKS (allow access to the upper banks + /* Bit 1 = DEVEN (device enable) + * Bit 4 = EN_BANKS (allow access to the upper banks) */ msr.lo = (1 << 4) | (1 << 1); msr.hi = 0; - /* enable COM1 */ + /* Enable COM1. */ wrmsr(MDD_UART1_CONF, msr); } - /** - * @brief Board setup. Known to work on norwich and digitial logic boards. - * The extmsr and cis_mode are common for sure. - * The RSTPLL check is mandatory. - * IDSEl of course is required, so the chip appears in PCI config space, + * Board setup. + * + * Known to work on the AMD Norwich and DIGITIAL-LOGIC boards. + * + * The extmsr and cis_mode are common for sure. The RSTPLL check is mandatory. + * IDSEL of course is required, so the chip appears in PCI config space, * and the swapsif covers a necessary chip fix. - * Finally, the iobase is needed for DRAM, the GPIOs - * are likely common to all boards, and the power button - * seems to be the same on all. At the same time, - * we may need to move gpio and power button - * out as developments demand. - * Note we do NOT do any UART - * setup here -- this is done later by the mainboard setup, - * since UART usage is not universal. - * A comment from Marc Jones: - "It - would be difficult to move this to early mainboard (car_auto) because - the IObase needs to be setup first and then SMBus setup would be - optional etc. I think that any platform that uses the SMBus GPIOs for - something other than SMBus will need a lot of customization anyway and - they would have to override the generic file. I understand the desire to - make everything generic but that really over complicates 99% of the - designs." + * + * Finally, the iobase is needed for DRAM, the GPIOs are likely common to all + * boards, and the power button seems to be the same on all. At the same time, + * we may need to move GPIO and power button out as developments demand. + * + * Note we do NOT do any UART setup here -- this is done later by the + * mainboard setup, since UART usage is not universal. + * + * See also a comment from Marc Jones: + * http://www.linuxbios.org/pipermail/linuxbios/2007-June/021958.html */ void cs5536_early_setup(void) { msr_t msr; - /* note: you can't do prints in here in most cases, - * and we don't want to hang on serial, so they are - * commented out - */ + /* Note: you can't do prints in here in most cases, and we don't want + * to hang on serial, so they are commented out. + */ cs5536_setup_extmsr(); cs5536_setup_cis_mode(); msr = rdmsr(GLCP_SYS_RSTPLL); if (msr.lo & (0x3f << 26)) { - /* PLL is already set and we are reboot from PLL reset */ + /* PLL is already set and we are reboot from PLL reset. */ return; } + cs5536_setup_idsel(); cs5536_usb_swapsif(); cs5536_setup_iobase(); cs5536_setup_smbus_gpio(); - /* cs5536_enable_smbus(); -- leave this out for now */ + /* cs5536_enable_smbus(); -- Leave this out for now. */ cs5536_setup_power_button(); }

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[LinuxBIOS] r2714 build service
by LinuxBIOS information 07 Jun '07

07 Jun '07

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "uwe" checked in revision 2714 to the LinuxBIOS source repository and caused the following changes: Change Log: Add support for the Winbond W83977F-A Super I/O. Signed-off-by: Nikolay Petukhov <nikolay.petukhov(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of arima:hdama is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2714&device=hdama&vendor=… Configuration of artecgroup:dbe61 is still broken Compilation of ibm:e325 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2714&device=e325&vendor=i… Compilation of ibm:e326 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2714&device=e326&vendor=i… Compilation of iwill:dk8s2 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2714&device=dk8s2&vendor=… Compilation of iwill:dk8x is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2714&device=dk8x&vendor=i… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, LinuxBIOS automatic build system

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coreboot June 2007