coreboot May 2003

coreboot@coreboot.org

70 participants
143 discussions

cvs co error
by Frank 14 May '03

14 May '03

I am getting the following error when trying to co linuxbios for the first time: cvs [checkout aborted]: could not chdir to freebios/src/arch/alpha/config: Not a directory anyone have an idea as to what is going on... __________________________________ Do you Yahoo!? The New Yahoo! Search - Faster. Easier. Bingo. http://search.yahoo.com

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Re: cvs co error
by Richard Smith 14 May '03

14 May '03

Frank wrote: > It looks like cvs under cygwin is the culprit. Anyone know how > to resolve this... I don't think there is a solution currently for use on a non-case sensitive filesystem. > --- Richard Smith <rsmith(a)bitworks.com> wrote: > >>>I am getting the following error when trying to co linuxbios >>>the first time: >>>cvs [checkout aborted]: could not chdir to >>>freebios/src/arch/alpha/config: Not a directory >> >>Do you per chance have that on a filesystem that isn't case >>sensitive? >>In the alpha directory there is both a 'Config' file and a >>'config' >>directory. -- Richard A. Smith rsmith(a)bitworks.com

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RFC:new superio proposal
by ron minnich 14 May '03

14 May '03

Abstract: The superio architecture for linuxbios has worked for the last 2 years but is being stretched to the limit by the changes in superio chips. The architecture depended on superio resources being relatively constant between chips, but this assumption no longer holds. In this document we propose several alternatives and solicit comments. Overview: The superio architecture in linuxbios was developed over time, and modified as circumstances required. In the beginning it was relatively simple and assumed only one superio per mainboard. The latest version allows an arbitrary number of superios per mainboard, and allows complete specification of the superio base I/O address along with the specification of reasonable default valures for both the base I/O address and the superio parameters such as serial enable, baud rate, and so on. Specification of superio control parameters is done by a configuration line such as: nsuperio sis/950 com1={1} floppy=1 lpt=1 This fragment sets the superio type to sis/950; sets com1, floppy, and lpt to enabled; and leaves the defaults to com1 (baud rate, etc.) to the default values. While it is not obvious, these configuration parameters are fragments of a C initializer. The initializers are used to build a statically initialized structure of this type: struct superio { struct superio_control *super; // the ops for the device. unsigned int port; // if non-zero, overrides the default port // com ports. This is not done as an array (yet). // We think it's easier to set up from python if it is not an // array. struct com_ports com1, com2, com3, com4; // DMA, if it exists. struct lpt_ports lpt1, lpt2; /* flags for each device type. Unsigned int. */ // low order bit ALWAYS means enable. Next bit means to enable // LPT is in transition, so we leave this here for the moment. // The winbond chips really stretched the way this works. // so many functions! unsigned int ide, floppy, lpt; unsigned int keyboard, cir, game; unsigned int gpio1, gpio2, gpio3; unsigned int acpi,hwmonitor; }; These structures are, in turn, created and statically initialized by a config-tool-generated structure that defines all the superios. This file is called nsuperio.c, is created for each mainboard you build, only appears in the build directory, and looks like this: === extern struct superio_control superio_winbond_w83627hf_control; struct superio superio_winbond_w83627hf= { &superio_winbond_w83627hf_control, .com1={1}, .com2={1}, .floppy=1, .lpt=1, .keyboard=1, .hwmonitor=1}; struct superio *all_superio[] = {&superio_winbond_w83627hf, }; unsigned long nsuperio = 1; === This example shows a board with one superio (nsuperio). The superio consists of a winbond w83627hf, with com1, com2, floppy, lpt, keyboard, and hwmonitor enabled. Note that this structure also allows for over-riding the default superio base, although that capability is rarely used. The control structure is used to define how to access the superio for purposes of control. It looks like this: === struct superio_control { void (*pre_pci_init)(struct superio *s); void (*init)(struct superio *s); void (*finishup)(struct superio *s); unsigned int defaultport; /* the defaultport. Can be overridden * by commands in config */ // This is the print name for debugging char *name; }; === There are three methods for stages of hardwaremain. First is pre_pci_init (for chips like the acer southbridge that require you to enable some resources BEFORE pci scan); init, called during the 'middle' phase of hardwaremain; and finishup, called before the payload is loaded. This approach was inspired by and borrows heavily on the Plan 9 kernel configuration tools. The problem: When the first version of the superio structure came out it was much smaller. It has grown and in the limit this structure is the union of all possibly superio chips. Obviously, in the long term, this is not practical: we can not anticipate all possible superio chips for all time. The common PC BIOS solution to this type of problem is to continue with binary structures but add version numbers to them, so that all code that uses a given structure has to check the version number. Personally, I find this grotesque and would rather not work this way. Using textual strings for configuration is something I find far more attractive. Plan 9 has shown that this approach has no real limits and suffices for configuration tasks. The Linux kernel does more limited use of strings for configuration, but still depends on them. Strings are easier to read and work with than binary structures, and more important, a lot easier to deal with when things start going wrong. The proposed solution: What follows are three possible ideas for specifying superio resources and their settings. A common part of the new idea is to eliminate the common superio structure, due to the many variations in chips, and make it invisible outside a given superio source file -- the superio structure is now private to a given superio. Thus, sis/950/superio.c would contain its own superio structure definitions, and also might contain more than once instance of these structures (consider a board with 2 sis 950 chips). The control structure would change as follows: struct superio_control { int (*create)(struct superio *s); void (*pre_pci_init)(struct superio *s); void (*init)(struct superio *s); void (*finishup)(struct superio *s); unsigned int defaultport; /* the defaultport. Can be overridden * by commands in config */ // This is the print name for debugging char *name; }; I.e. we add a new function for creating the superio. Communication of superio settings from linuxbios to the superio would be via textual strings. The superio structure becomes this: struct superio { struct superio_control *super; // the ops for the device. unsigned int port; // if non-zero, overrides the default port struct configuration *config; }; So now the question becomes, what is the configuration structure? There are several choices. The simplest, from my point of view, are keyword-value pairs: struct configuration { const char *keyword; const char *value; }; These get filled in by the config tool as before. The linuxbios libary can then provide a generic parsing function for the superios to use. The remaining question is how should the superio command look in freebios2? superio sis/950 "com1=115200,8n1 lpt=1 com2=9600" or superio sis/950 "com1baud=115200 lpt=1 com1chars=8n1" or superio sis/950 ((com1 115200 8n1) (lpt 1)) So, my questions: 1. Does this new scheme look workable. If not, what needs to change? 2. What should the 'struct configuration' be? does keyword/value work? 3. what should the superio command look like? Comments welcome. I'd like to adopt this "RFC" approach for freebios2 as much as we can. There was a lot of give-and-take in the early days of linuxbios about structure and it proved useful. There's a lot that will start happening in freebios2 now, and we need to try to make sure it will work for everyone. Those of you who are doing mainboards, please look at freebios2 and see how it looks for you. There's a lot of good work that has been done (not by me so far, thanks Eric and Stefan), and more that needs to be done. Consider trying out romcc as an "assembly code killer". See how it fits together and if you can work with it or need changes. Bring comments back to this list. thanks ron

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hello
by Serafino Sorrenti 14 May '03

14 May '03

Hello Richard, i'm very crazy for this problem, i have done the modify at the config file for etherboot but i don't see any log in to serial port, and i don't see the linuxbios status. Tnx any more Serafino

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Re: TUSL2-C almost work.....
by Yap Ee Huey 14 May '03

14 May '03

> > This has to be seek=1, not skip=1. Otherwise you overwrite your > > partition table with an incomplete elf file instead of leaving > > your partition table there and writing the complete file. > > > >I am going to regret that particular typo of mine for a long time. > >Sorry. Doesn't matter, both not working for me. I follow Richard's etherboot instructions on etherboot 5.1.8 but still no luck. Could it be my IDE harddisk not recognized ? OUTPUTS: ------------------------------------------------------------------------------------------------------ Welcome to elfboot, the open sourced starter. January 2002, Eric Biederman. Version 1.2 203:init_bytes() - zkernel_start:0xfff00000 zkernel_mask:0x0000ffff Searching for 16 byte tags 64:rom_read_bytes() - overflowed source buffer. max_block = 15 init_bytes found 0 tags Found ELF candiate at offset 0 Loading Etherboot version: 5.1.8 Dropping non PT_LOAD segment New segment addr 0x20000 size 0xeee0 offset 0xb0 filesize 0x617c (cleaned up) New segment addr 0x20000 size 0xeee0 offset 0xb0 filesize 0x617c Loading Segment: addr: 0x000000000ff7ece8 memsz: 0x000000000000eee0 filesz: 0x000000000000617c Clearing Segment: addr: 0x000000000ff84e64 memsz: 0x0000000000008d64 Jumping to boot code at 0x20000 ------------------------------------------------------------------------------------------------------------ Then it restarts. > >I think the solution of using sfdisk to build a /dev/hda1 that starts at >sector 1 is better. Fixing etherboot to scan 64k in each direction is >best. I tried that but it still didn't find the elfimage. > >ron > _________________________________________________________________ Download ringtones, logos and picture messages from MSN Malaysia http://www.msn.com.my/mobile/ringtones/default.asp

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doesn't support 2Mbit rom?
by bendany 14 May '03

14 May '03

I am testing another mainboard with linuxbios. base on 440bx chipset. onboard 82558 netcard, ati rage 128 videocard and ess 1938 soundcard. the eprom is MX29F004, 4Mbit. I use the config of digitallogic/smartcore-p3.use the etherboot 5.06 payload. I build a 1M romimage. burn it into Atmel 29c010a. linuxbios can succeed load the etherboot payload. but the etherboot failed detecting the onboard netcard. so I try ADLO, and I replace the etherboot payload with ADLO. build a 2Mbit romimage. burn it into SST 29EE020. but the elfboot cannot find the ELF image of ADLO. ---------output message---------------- done. Copying IRQ routing tables to 0xf0000...done. Verifing priq routing tables copy at 0xf0000...failed Wrote linuxbios table at: 00000500 - 00000680 checksum fe7c Welcome to elfboot, the open sourced starter. January 2002, Eric Biederman. Version 1.2 37:init_bytes() - zkernel_start:0xfffc0000 zkernel_mask:0x0000007f Cannot Load ELF Image ----------------------------------------- ----------my config file ---------------- target 440bx mainboard digitallogic/smartcore-p3 option SERIAL_CONSOLE=1 option DEFAULT_CONSOLE_LOGLEVEL=8 option MAXIMUM_CONSOLE_LOGLEVEL=8 option DEBUG=1 option USE_GENERIC_ROM=1 option ROM_SIZE=262144 option PAYLOAD_SIZE=196608 option USE_ELF_BOOT=1 #payload ../eepro100.ebi payload ../payload.adlo nooption RAMTEST -------------------------------- I have no idea how to deal with. any tips? BTW: if I use polled IDE patch + ADLO. videocard can init correctly. Regards.

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[Status] freebios1.1
by ebiederman＠lnxi.com 13 May '03

13 May '03

I have just merged a driver update from SuSE. IDE should now work. Resets new work to some extent. Romcc continues to stabilize. I have just found a bug in the register allocator and added a runtime check so the code will fail at compile time. In addition I have added a work around for the common case to let development continue. The problem is that some instructions must use a specific register, and when two of those instructions exist, use the same register and there is not an intermediate instruction that would move the value from one register to another then romcc fails to put the value into a different register. It skips the instruction because the register is already allocated. Fixing this problem and in general implement spilling from one register into another in romcc is now on the todo list. Doing this cleanly will take a little time. But it is also required to support storing values in the sse/mmx registers and other places. Eric

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intel firmware hub parts
by ron minnich 13 May '03

13 May '03

has anyone found a distributor for these parts? this is really amazing, but nobody I have talked to sells them. They get them via hook and crook from intel, but actually buy them? never happens. ron

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TUSL2-C almost work.....
by Yap Ee Huey 13 May '03

13 May '03

Hi, I have some improvement on my TUSL2-C board (intel 82815ep chipset). The ram initialization is successful . However, it boots neither etherboot elf nor adlo payload. It hangs after the following messages from serial port . I put the tagged bzImage (not elf) on hda using : dd if=bzImage.ether of=/dev/hda bs=4096 skip=1 as suggested by ron but it does not seem to be recognized by linuxbios . I am using sis900.ebi as ide etherboot. Any idea ? Thanks. LinuxBIOS-1.0.0 Tue May 13 12:12:08 EDT 2003 starting... Ram1 Ram2 Ram3 Ram Enable 1 Ram Enable 2 Ram Enable 3 Ram Enable 4 Ram Enable 5 Ram4 Ram5 Ram6 Testing SDRAM : 00000000-0009ffff SDRAM fill: 00000000 00010000 00020000 LinuxBIOS-1.0.0 Tue May 13 12:12:08 EDT 2003 starting... Ram1 Ram2 Ram3 Ram Enable 1 Ram Enable 2 Ram Enable 3 Ram Enable 4 Ram Enable 5 Ram4 Ram5 Ram6 Testing SDRAM : 00000000-0009ffff SDRAM fill: 00000000 00010000 00020000 00030000 00040000 00050000 00060000 00070000 00080000 00090000 0009ffff SDRAM verify: 00000000 00010000 00020000 00030000 00040000 00050000 00060000 00070000 00080000 00090000 0009ffff Done. Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-1.0.0 Tue May 13 12:12:08 EDT 2003 booting... Finding PCI configuration type. PCI: Using configuration type 1 Scanning PCI bus...PCI: pci_scan_bus for bus 0 PCI: 00:00.0 [8086/1130] PCI: 00:01.0 [8086/1131] PCI: 00:1e.0 [8086/244e] PCI: 00:1f.0 [8086/2440] PCI: 00:1f.1 [8086/244b] PCI: 00:1f.2 [8086/2442] PCI: 00:1f.3 [8086/2443] PCI: 00:1f.4 [8086/2444] PCI: 00:1f.5 [8086/2445] PCI: 00:1f.6 [8086/2446] PCI: pci_scan_bus for bus 1 PCI: 01:00.0 [1002/5144] PCI: pci_scan_bus returning with max=01 PCI: pci_scan_bus for bus 2 PCI: 02:07.0 [13f6/0111] PCI: 02:0a.0 [10b7/9055] PCI: pci_scan_bus returning with max=02 PCI: pci_scan_bus returning with max=02 done Allocating PCI resources... ASSIGN RESOURCES, bus 0 PCI: 00:00.0 10 <- [0xf8000000 - 0xfbffffff] prefmem PCI: 00:01.0 1c <- [0x00001000 - 0x00001fff] bus 1 io PCI: 00:01.0 24 <- [0xf0000000 - 0xf7ffffff] bus 1 prefmem PCI: 00:01.0 20 <- [0xfc000000 - 0xfc0fffff] bus 1 mem ASSIGN RESOURCES, bus 1 PCI: 01:00.0 10 <- [0xf0000000 - 0xf7ffffff] prefmem PCI: 01:00.0 14 <- [0x00001000 - 0x000010ff] io PCI: 01:00.0 18 <- [0xfc000000 - 0xfc07ffff] mem ASSIGNED RESOURCES, bus 1 PCI: 00:1e.0 1c <- [0x00002000 - 0x00002fff] bus 2 io PCI: 00:1e.0 24 <- [0xfc200000 - 0xfc1fffff] bus 2 prefmem PCI: 00:1e.0 20 <- [0xfc100000 - 0xfc1fffff] bus 2 mem ASSIGN RESOURCES, bus 2 PCI: 02:07.0 10 <- [0x00002000 - 0x000020ff] io PCI: 02:0a.0 10 <- [0x00002400 - 0x0000247f] io PCI: 02:0a.0 14 <- [0xfc100000 - 0xfc10007f] mem ASSIGNED RESOURCES, bus 2 PCI: 00:1f.1 20 <- [0x00003c00 - 0x00003c0f] io PCI: 00:1f.2 20 <- [0x000038c0 - 0x000038df] io PCI: 00:1f.3 20 <- [0x00003c10 - 0x00003c1f] io PCI: 00:1f.4 20 <- [0x000038e0 - 0x000038ff] io PCI: 00:1f.5 10 <- [0x00003000 - 0x000030ff] io PCI: 00:1f.5 14 <- [0x00003880 - 0x000038bf] io PCI: 00:1f.6 10 <- [0x00003400 - 0x000034ff] io PCI: 00:1f.6 14 <- [0x00003800 - 0x0000387f] io ASSIGNED RESOURCES, bus 0 Allocating VGA resource done. Enabling PCI resourcess...PCI: 00:00.0 cmd <- 06 PCI: 00:01.0 cmd <- 07 PCI: 00:1e.0 cmd <- 07 PCI: 00:1f.0 cmd <- 0f PCI: 00:1f.1 cmd <- 01 PCI: 00:1f.2 cmd <- 01 PCI: 00:1f.3 cmd <- 01 PCI: 00:1f.4 cmd <- 01 PCI: 00:1f.5 cmd <- 01 PCI: 00:1f.6 cmd <- 01 PCI: 01:00.0 cmd <- 83 PCI: 02:07.0 cmd <- 81 PCI: 02:0a.0 cmd <- 03 done. Initializing PCI devices... PCI devices initialized DRP0 = 0xc DIMM0 - size = 256M DIMM1 - size = 0M DRP1 = 0x0 DIMM2 - size = 0M totalram: 256M Initializing CPU #0 Updating microcode microcode_info: sig = 0x000006b1 pf=0x00000010 rev = 0x00000000 Enabling cache... Setting fixed MTRRs(0-88) type: UC inside set_fixed_mtrrs going out set_fixed_mtrrs Setting fixed MTRRs(0-16) type: WB inside set_fixed_mtrrs going out set_fixed_mtrrs DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 256MB, type WB DONE variable MTRRs Clear out the extra MTRR's call intel_enable_fixed_mtrr() call intel_enable_var_mtrr() Leave setup_mtrrs done. Max cpuid index : 2 Vendor ID : GenuineIntel Processor Type : 0x00 Processor Family : 0x06 Processor Model : 0x0b Processor Mask : 0x00 Processor Stepping : 0x01 Feature flags : 0x0383fbff Cache/TLB descriptor values: 1 reads required Desc 0x01 : Instr TLB: 4KB pages, 4-way set assoc, 32 entries Desc 0x02 : Instr TLB: 4MB pages, fully assoc, 2 entries Desc 0x03 : Data TLB: 4KB pages, 4-way set assoc, 64 entries Desc 0x00 : null Desc 0x00 : null Desc 0x00 : null Desc 0x00 : null Desc 0x00 : null Desc 0x00 : null Desc 0x00 : null Desc 0x00 : null Desc 0x82 : L2 Unified cache: 256K bytes, 8-way set assoc, 32 byte line size Desc 0x08 : Inst cache: 16K bytes, 4-way set assoc, 32 byte line size Desc 0x04 : Data TLB: 4MB pages, 4-way set assoc, 8 entries Desc 0x0c : Data cache: 16K bytes, 2-way or 4-way set assoc, 32 byte line size MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Configuring L2 cache...CPU signature of 6b0 so no L2 cache configuration Enable Cache done. Disabling local apic...done. CPU #0 Initialized Please turn on nvram Copying IRQ routing tables to 0xf0000...done. Verifing priq routing tables copy at 0xf0000...failed Wrote linuxbios table at: 00000500 - 00000660 checksum 393b Welcome to elfboot, the open sourced starter. January 2002, Eric Biederman. Version 1.2 203:init_bytes() - zkernel_start:0xfff00000 zkernel_mask:0x0000ffff Searching for 16 byte tags 64:rom_read_bytes() - overflowed source buffer. max_block = 15 init_bytes found 0 tags Found ELF candiate at offset 0 New segment addr 0x7c00 size 0x20400 offset 0x100 filesize 0x20400 (cleaned up) New segment addr 0x7c00 size 0x20400 offset 0x100 filesize 0x20400 Loading Segment: addr: 0x000000000ff667e8 memsz: 0x0000000000020400 filesz: 0x0000000000020400 Jumping to boot code at 0x7c00 regards, eehuey _________________________________________________________________ Download ringtones, logos and picture messages from MSN Malaysia http://www.msn.com.my/mobile/ringtones/default.asp

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After make the linuxbios.rom
by Serafino Sorrenti 13 May '03

13 May '03

After make the linuxbios.rom with this config file i don't see any log in the serial ports, and the monitor is out of signal. tnx Serafino # Sample config file for PCCHIPS M810LMR with DoC Millennium (as root) # This will make a target directory of ./pcchips target pcchips # PCCHIPS M810LMR mainboard mainboard pcchips/m810lmr # We are using a k7 cpu (???) cpu k7 # Set up udelay - needed option CONFIG_UDELAY_TSC=1 # This SHOULD enable the video console with messages about what's going on #option VIDEO_CONSOLE=1 # Enable Serial Console for debugging option SERIAL_CONSOLE=1 # Sets the log level, from 9 to 1 (???) option DEFAULT_CONSOLE_LOGLEVEL=6 # More debug options option SERIAL_POST=1 # Enables ethernet (?) option ENABLE_MII=1 # use DOC MIL option USE_DOC_MIL=1 docipl northsouthbridge/sis/730/ipl.S # Use the internal VGA frame buffer device option HAVE_FRAMEBUFFER=1 # Sets the amount of framebuffer memory # 0x80 (2MB/4MB) # 0x90 (4MB/8MB) # 0xA0 (8MB/16MB) # 0xB0 (16MB/32MB) # 0xC0 (32MB/64MB) # 0xD0 (64MB/na) option SMA_SIZE=0xC0 # Enables IDE boot option BOOT_IDE=1 # Selects which IDE device should boot from, using the following table: # /dev/hda -> 0 # /dev/hdb -> 1 # /dev/hdc -> 2 # /dev/hdd -> 3 option IDE_BOOT_DRIVE=0 payload /home/fino/ide_disk.zelf # Partition table size (should be left untouched?) option ONE_TRACK=32 # Need to "relocate the gdt" to use a standard flash part (???) biosbase 0xffff0000 # Path to your kernel (vmlinux) linux /usr/src/linux # Kernel command line parameters commandline root=/dev/hda1 console=ttyS0,115200 console=tty0 single

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coreboot May 2003